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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id s185-v6sm4834201pfb.116.2018.07.03.08.17.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Jul 2018 08:17:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=x2t1XFI2QFPK2VzG0H6uB4M9ibalVxnRLpzzWNvPaFo=; b=eMQZWc/sw7hB9QWhhfnqh1BxXPNc4BdZM8QgKiRX/2Hp4YtKyjXCI0hgojchkFovhp BxjCjaWfMheb/pMx8n1bFR+SVXJPQNHOXrFfy49Tp37E0UwTLX52moY1GRq3wF5O8L7v tkspR2bL8HCX6k9LoKGzyruI/l0mug1cfMM5E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=x2t1XFI2QFPK2VzG0H6uB4M9ibalVxnRLpzzWNvPaFo=; b=kZP3CWmeBcxT4dF+Nv9wHEDZ2g34T8ZLd2qDbS4rkNRR1xLtRqDlO3hZ1X02NKXEO+ w1kB8xtYOZZkapaFKd88sd7xg7przk5mcQ0KY7NIZ5nD/LjR32VCUXqIVYtFbU88FE22 sbtw596AQUGmf2RoRH/pulyJ1PM0xxIbUp29Jj6JJ8vMELuzfIDGN6BKN/6aRc3z2oMe 6bJFQ+P3cgOmkuy/eGk/y0uBYaAE6TX7O/lFMTTJ0jOS83CfGQKgC5HJ17xSBUPT6LU0 x+icnnFzrRAm+neOK5h7EcNSMsdtcAgZw9I9gJX0WsLc1042dhwo6nNweKsc9r7WKS4g I1kQ== X-Gm-Message-State: APt69E3ccwyJNlaip2KWo0Q99JjkcQOt+JDnLZb+oZPOgrJncW9981bi eYC9SR7IMxkAUJBqMvML/IaySlGm/jY= X-Google-Smtp-Source: ADUXVKJAF9cUR+AelxmEyntW4g4L3XQ5yMpRcBqStGshXqALf4O9R39s6vJoTcr/Ml3pacFVNJoBpg== X-Received: by 2002:a65:4e09:: with SMTP id r9-v6mr25493523pgt.369.1530631057244; Tue, 03 Jul 2018 08:17:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 3 Jul 2018 08:17:27 -0700 Message-Id: <20180703151732.29843-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703151732.29843-1-richard.henderson@linaro.org> References: <20180703151732.29843-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 2/7] target/ppc: Honor fpscr_ze semantics and tidy fdiv X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: programmingkidx@gmail.com, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Divide by zero, exception taken, leaves the destination register unmodified. Therefore we must raise the exception before returning from helper_fdiv. Move the check from do_float_check_status into helper_fdiv. At the same time, tidy the invalid exception checking so that we rely on softfloat for initial argument validation, and select the kind of invalid operand exception only when we know we must. At the same time, pass and return float64 values directly rather than bounce through the CPU_DoubleU union. Signed-off-by: Richard Henderson --- target/ppc/helper.h | 2 +- target/ppc/fpu_helper.c | 44 ++++++++++++++++++++--------------------- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index d751f0e219..151437d8fc 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -88,7 +88,7 @@ DEF_HELPER_2(frim, i64, env, i64) DEF_HELPER_3(fadd, i64, env, i64, i64) DEF_HELPER_3(fsub, i64, env, i64, i64) DEF_HELPER_3(fmul, i64, env, i64, i64) -DEF_HELPER_3(fdiv, i64, env, i64, i64) +DEF_HELPER_3(fdiv, f64, env, f64, f64) DEF_HELPER_4(fmadd, i64, env, i64, i64, i64) DEF_HELPER_4(fmsub, i64, env, i64, i64, i64) DEF_HELPER_4(fnmadd, i64, env, i64, i64, i64) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 119826b5a7..0df7e31c10 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -543,9 +543,7 @@ static void do_float_check_status(CPUPPCState *env, uin= tptr_t raddr) CPUState *cs =3D CPU(ppc_env_get_cpu(env)); int status =3D get_float_exception_flags(&env->fp_status); =20 - if (status & float_flag_divbyzero) { - float_zero_divide_excp(env, raddr); - } else if (status & float_flag_overflow) { + if (status & float_flag_overflow) { float_overflow_excp(env); } else if (status & float_flag_underflow) { float_underflow_excp(env); @@ -653,30 +651,32 @@ uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1,= uint64_t arg2) } =20 /* fdiv - fdiv. */ -uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2) +float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2) { - CPU_DoubleU farg1, farg2; + float64 ret =3D float64_div(arg1, arg2, &env->fp_status); + int status =3D get_float_exception_flags(&env->fp_status); =20 - farg1.ll =3D arg1; - farg2.ll =3D arg2; - - if (unlikely(float64_is_infinity(farg1.d) && - float64_is_infinity(farg2.d))) { - /* Division of infinity by infinity */ - farg1.ll =3D float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1); - } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.= d))) { - /* Division of zero by zero */ - farg1.ll =3D float_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1); - } else { - if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) || - float64_is_signaling_nan(farg2.d, &env->fp_status))) { - /* sNaN division */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + if (unlikely(status)) { + if (status & float_flag_invalid) { + /* Determine what kind of invalid operation was seen. */ + if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { + /* Division of infinity by infinity */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1); + } else if (float64_is_zero(arg1) && float64_is_zero(arg2)) { + /* Division of zero by zero */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1); + } else if (float64_is_signaling_nan(arg1, &env->fp_status) || + float64_is_signaling_nan(arg2, &env->fp_status)) { + /* sNaN division */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + } + } + if (status & float_flag_divbyzero) { + float_zero_divide_excp(env, GETPC()); } - farg1.d =3D float64_div(farg1.d, farg2.d, &env->fp_status); } =20 - return farg1.ll; + return ret; } =20 =20 --=20 2.17.1