From nobody Tue Nov 4 18:52:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530598510453270.8132418639709; Mon, 2 Jul 2018 23:15:10 -0700 (PDT) Received: from localhost ([::1]:38022 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEaj-00082w-Iq for importer@patchew.org; Tue, 03 Jul 2018 02:15:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39599) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKQ-0002mP-Go for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKO-0006tk-Tj for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:18 -0400 Received: from ozlabs.org ([203.11.71.1]:58165) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKO-0006nw-9e; Tue, 03 Jul 2018 01:58:16 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYM71Tmqz9s4b; Tue, 3 Jul 2018 15:58:09 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597491; bh=BFS+CaF6e/fPU1/AdTgciCz0H8UI/GWeYHQ8r8Hc9n8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JAHcwkHh53XUo9uYp6dQ37guyRQ2uzkL8nOJseMq4JTz/LNTcdKkuw1PDoX8JUi+4 FGLwEwezeL+AMgpzYkWWRKJo+zQTa0W3rcEuPOfNpFLeB4JPxCD/al82hYhCSoed7j V7jeVfhUiqexWSD4Y2F3/c1vNI7tG15JL6ENbloU= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:36 +1000 Message-Id: <20180703055804.13449-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 07/35] ppx/xics: introduce a parent_reset in ICSStateClass X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: C=C3=A9dric Le Goater Just like for the realize handlers, this makes possible to move the common ICSState code of the reset handlers in the ics-base class. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: David Gibson --- hw/intc/xics.c | 45 ++++++++++++++++++++++++++++--------------- hw/intc/xics_kvm.c | 26 ++++++++++--------------- include/hw/ppc/xics.h | 1 + 3 files changed, 41 insertions(+), 31 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 83340770f7..8cfe223153 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -537,23 +537,16 @@ static void ics_simple_eoi(ICSState *ics, uint32_t nr) } } =20 -static void ics_simple_reset(void *dev) +static void ics_simple_reset(DeviceState *dev) { - ICSState *ics =3D ICS_SIMPLE(dev); - int i; - uint8_t flags[ics->nr_irqs]; + ICSStateClass *icsc =3D ICS_BASE_GET_CLASS(dev); =20 - for (i =3D 0; i < ics->nr_irqs; i++) { - flags[i] =3D ics->irqs[i].flags; - } - - memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs); + icsc->parent_reset(dev); +} =20 - for (i =3D 0; i < ics->nr_irqs; i++) { - ics->irqs[i].priority =3D 0xff; - ics->irqs[i].saved_priority =3D 0xff; - ics->irqs[i].flags =3D flags[i]; - } +static void ics_simple_reset_handler(void *dev) +{ + ics_simple_reset(dev); } =20 static int ics_simple_dispatch_pre_save(void *opaque) @@ -625,7 +618,7 @@ static void ics_simple_realize(DeviceState *dev, Error = **errp) =20 ics->qirqs =3D qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irq= s); =20 - qemu_register_reset(ics_simple_reset, ics); + qemu_register_reset(ics_simple_reset_handler, ics); } =20 static void ics_simple_class_init(ObjectClass *klass, void *data) @@ -635,6 +628,8 @@ static void ics_simple_class_init(ObjectClass *klass, v= oid *data) =20 device_class_set_parent_realize(dc, ics_simple_realize, &isc->parent_realize); + device_class_set_parent_reset(dc, ics_simple_reset, + &isc->parent_reset); =20 dc->vmsd =3D &vmstate_ics_simple; isc->reject =3D ics_simple_reject; @@ -650,6 +645,25 @@ static const TypeInfo ics_simple_info =3D { .class_size =3D sizeof(ICSStateClass), }; =20 +static void ics_base_reset(DeviceState *dev) +{ + ICSState *ics =3D ICS_BASE(dev); + int i; + uint8_t flags[ics->nr_irqs]; + + for (i =3D 0; i < ics->nr_irqs; i++) { + flags[i] =3D ics->irqs[i].flags; + } + + memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs); + + for (i =3D 0; i < ics->nr_irqs; i++) { + ics->irqs[i].priority =3D 0xff; + ics->irqs[i].saved_priority =3D 0xff; + ics->irqs[i].flags =3D flags[i]; + } +} + static void ics_base_realize(DeviceState *dev, Error **errp) { ICSState *ics =3D ICS_BASE(dev); @@ -689,6 +703,7 @@ static void ics_base_class_init(ObjectClass *klass, voi= d *data) =20 dc->realize =3D ics_base_realize; dc->props =3D ics_base_properties; + dc->reset =3D ics_base_reset; } =20 static const TypeInfo ics_base_info =3D { diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c index 1f27eb4979..b314eb7d16 100644 --- a/hw/intc/xics_kvm.c +++ b/hw/intc/xics_kvm.c @@ -324,25 +324,18 @@ static void ics_kvm_set_irq(void *opaque, int srcno, = int val) } } =20 -static void ics_kvm_reset(void *dev) +static void ics_kvm_reset(DeviceState *dev) { - ICSState *ics =3D ICS_SIMPLE(dev); - int i; - uint8_t flags[ics->nr_irqs]; - - for (i =3D 0; i < ics->nr_irqs; i++) { - flags[i] =3D ics->irqs[i].flags; - } + ICSStateClass *icsc =3D ICS_BASE_GET_CLASS(dev); =20 - memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs); + icsc->parent_reset(dev); =20 - for (i =3D 0; i < ics->nr_irqs; i++) { - ics->irqs[i].priority =3D 0xff; - ics->irqs[i].saved_priority =3D 0xff; - ics->irqs[i].flags =3D flags[i]; - } + ics_set_kvm_state(ICS_KVM(dev), 1); +} =20 - ics_set_kvm_state(ics, 1); +static void ics_kvm_reset_handler(void *dev) +{ + ics_kvm_reset(dev); } =20 static void ics_kvm_realize(DeviceState *dev, Error **errp) @@ -358,7 +351,7 @@ static void ics_kvm_realize(DeviceState *dev, Error **e= rrp) } ics->qirqs =3D qemu_allocate_irqs(ics_kvm_set_irq, ics, ics->nr_irqs); =20 - qemu_register_reset(ics_kvm_reset, ics); + qemu_register_reset(ics_kvm_reset_handler, ics); } =20 static void ics_kvm_class_init(ObjectClass *klass, void *data) @@ -371,6 +364,7 @@ static void ics_kvm_class_init(ObjectClass *klass, void= *data) * directly from ics-base and not from ics-simple anymore. */ dc->realize =3D ics_kvm_realize; + dc->reset =3D ics_kvm_reset; =20 icsc->pre_save =3D ics_get_kvm_state; icsc->post_load =3D ics_set_kvm_state; diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 44e96e6400..6ac8a9392d 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -116,6 +116,7 @@ struct ICSStateClass { DeviceClass parent_class; =20 DeviceRealize parent_realize; + DeviceReset parent_reset; =20 void (*pre_save)(ICSState *s); int (*post_load)(ICSState *s, int version_id); --=20 2.17.1