From nobody Tue Nov 4 18:35:15 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530598551530705.5886275926389; Mon, 2 Jul 2018 23:15:51 -0700 (PDT) Received: from localhost ([::1]:38030 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEbO-0000Gg-Jb for importer@patchew.org; Tue, 03 Jul 2018 02:15:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39988) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKb-0002wG-0y for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKY-00076V-DB for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:28 -0400 Received: from ozlabs.org ([203.11.71.1]:35063) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKX-00071Z-Uo; Tue, 03 Jul 2018 01:58:26 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYMD1lsdz9sC7; Tue, 3 Jul 2018 15:58:15 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597496; bh=qMoYBT3owSKVOG4/9A+iznCQCBdNL3iK6qWdcZoh68g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FJawAaYqcKWctuvMUacqrfUjDCSzcvpPatDrdYhzqM1AU+zJEwMOhXDMxFI8CzMuv pP3tMQGo8Yh4JshqRJy0EuXbYFA4eGZVR1t4jRMB9Q1m5ScsGS7i3gq0QK1+7f3nWu etgUInuUmJRiqs0iE0J6PasMBPi1B+tP8XJj8+as= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:58:03 +1000 Message-Id: <20180703055804.13449-35-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 34/35] target/ppc: Relax reserved bitmask of indexed store instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: BALATON Zoltan The PPC440 User Manual says that if bit 31 is set, the contents of CR[CR0] are undefined for indexed store instructions but this form is not invalid. Other PPC variants confirming to recent ISA where this bit may be reserved should ignore reserved bits and not raise invalid instruction exception. In particular, MorphOS has an stwx instruction with bit 31 set and fails to boot currently because of this. With this patch it gets further. Signed-off-by: David Gibson --- target/ppc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 65c8cc94e7..9eaa10b421 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7054,7 +7054,7 @@ GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, typ= e), #define GEN_STUX(name, stop, opc2, opc3, type) = \ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) = \ -GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), +GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), #define GEN_STS(name, stop, op, type) = \ GEN_ST(name, stop, op | 0x20, type) = \ GEN_STU(name, stop, op | 0x21, type) = \ --=20 2.17.1