From nobody Tue Nov 4 18:34:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530599129604168.45644042564925; Mon, 2 Jul 2018 23:25:29 -0700 (PDT) Received: from localhost ([::1]:38090 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEkd-000819-P6 for importer@patchew.org; Tue, 03 Jul 2018 02:25:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39932) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKZ-0002tZ-6l for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKU-000707-RH for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:27 -0400 Received: from ozlabs.org ([203.11.71.1]:60631) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKU-0006x6-5V; Tue, 03 Jul 2018 01:58:22 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYMB4n6Tz9sBr; Tue, 3 Jul 2018 15:58:13 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597494; bh=R3JFOmTGoiKEtvzTZVqZcIkXcRYR7egn46W/BiEKJYU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KaSzsVnp1f4UHsKjtbJFP86I8nspRDC1Wh1uJDtCDtSSAtQpPTiYHkBy8HMKxWHB3 q9RTqr/eeNoUpQYrIAlkTpcJUJA+Qs3f3bsFVOMMo1BjTMNNFblyDFxjLuRuabmZKv iE366ov+bycmG9A3QNQC1sjduzGXV4d6ZyJ/yaQo= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:53 +1000 Message-Id: <20180703055804.13449-25-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 24/35] fpu_helper.c: fix setting FPSCR[FI] bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Arbuckle , qemu-devel@nongnu.org, mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: John Arbuckle The FPSCR[FI] bit indicates if the last floating point instruction had a re= sult that was rounded. Each consecutive floating point instruction is suppo= se to set this bit to the correct value. What currently happens is this bit= is not set as often as it should be. I have verified that this is the beha= vior of a real PowerPC 950. This patch fixes that problem by deciding to se= t this bit after each floating point instruction. https://www.pdfdrive.net/powerpc-microprocessor-family-the-programming-envi= ronments-for-32-e3087633.html Page 63 in table 2-4 is where the description of this bit can be found. Signed-off-by: John Arbuckle Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 7714bfe0f9..8675d931b6 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -274,6 +274,7 @@ static inline void float_inexact_excp(CPUPPCState *env) { CPUState *cs =3D CPU(ppc_env_get_cpu(env)); =20 + env->fpscr |=3D 1 << FPSCR_FI; env->fpscr |=3D 1 << FPSCR_XX; /* Update the floating-point exception summary */ env->fpscr |=3D FP_FX; @@ -533,6 +534,7 @@ static void do_float_check_status(CPUPPCState *env, uin= tptr_t raddr) { CPUState *cs =3D CPU(ppc_env_get_cpu(env)); int status =3D get_float_exception_flags(&env->fp_status); + bool inexact_happened =3D false; =20 if (status & float_flag_divbyzero) { float_zero_divide_excp(env, raddr); @@ -542,6 +544,12 @@ static void do_float_check_status(CPUPPCState *env, ui= ntptr_t raddr) float_underflow_excp(env); } else if (status & float_flag_inexact) { float_inexact_excp(env); + inexact_happened =3D true; + } + + /* if the inexact flag was not set */ + if (inexact_happened =3D=3D false) { + env->fpscr &=3D ~(1 << FPSCR_FI); /* clear the FPSCR[FI] bit */ } =20 if (cs->exception_index =3D=3D POWERPC_EXCP_PROGRAM && --=20 2.17.1