From nobody Tue Nov 4 18:52:28 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530598958464707.654099295664; Mon, 2 Jul 2018 23:22:38 -0700 (PDT) Received: from localhost ([::1]:38072 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEhx-0005XN-IZ for importer@patchew.org; Tue, 03 Jul 2018 02:22:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39803) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKV-0002rC-P7 for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKS-0006xs-IT for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:23 -0400 Received: from ozlabs.org ([203.11.71.1]:48151) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKR-0006uF-P6; Tue, 03 Jul 2018 01:58:20 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYM95kgWz9s9y; Tue, 3 Jul 2018 15:58:11 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597493; bh=b9K6lgAlIlXGzW0zb2bBBQrlnAX0Fz3I1exeWmRL6qk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BiZ3C1T91IVzidnguaTAMzKkEVb63YvVUJuEIFDVFTeAAJGT/O1EURTIl2tufHags wax2xynIWN/Oc4Ugbb+sR5Z6MP9Ae6mmGofKX5soAgikNGAym0WFtzcBnyF+09XhuK v8kTfrJektBuTaIcTnIgpZyCs4r5zlh65bAyeeLc= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:44 +1000 Message-Id: <20180703055804.13449-16-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 15/35] target/ppc: Remove POWERPC_EXCP_STCX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Always use the gen_conditional_store implementation that uses atomic_cmpxchg. Make sure and clear reserve_addr across most interrupts crossing the cpu_loop. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- linux-user/ppc/cpu_loop.c | 121 +++++++------------------------------- target/ppc/cpu.h | 5 -- target/ppc/translate.c | 14 ----- 3 files changed, 22 insertions(+), 118 deletions(-) diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 2fb516cb00..133a87f349 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -65,99 +65,23 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32= _t val) return -1; } =20 -static int do_store_exclusive(CPUPPCState *env) -{ - target_ulong addr; - target_ulong page_addr; - target_ulong val, val2 __attribute__((unused)) =3D 0; - int flags; - int segv =3D 0; - - addr =3D env->reserve_ea; - page_addr =3D addr & TARGET_PAGE_MASK; - start_exclusive(); - mmap_lock(); - flags =3D page_get_flags(page_addr); - if ((flags & PAGE_READ) =3D=3D 0) { - segv =3D 1; - } else { - int reg =3D env->reserve_info & 0x1f; - int size =3D env->reserve_info >> 5; - int stored =3D 0; - - if (addr =3D=3D env->reserve_addr) { - switch (size) { - case 1: segv =3D get_user_u8(val, addr); break; - case 2: segv =3D get_user_u16(val, addr); break; - case 4: segv =3D get_user_u32(val, addr); break; -#if defined(TARGET_PPC64) - case 8: segv =3D get_user_u64(val, addr); break; - case 16: { - segv =3D get_user_u64(val, addr); - if (!segv) { - segv =3D get_user_u64(val2, addr + 8); - } - break; - } -#endif - default: abort(); - } - if (!segv && val =3D=3D env->reserve_val) { - val =3D env->gpr[reg]; - switch (size) { - case 1: segv =3D put_user_u8(val, addr); break; - case 2: segv =3D put_user_u16(val, addr); break; - case 4: segv =3D put_user_u32(val, addr); break; -#if defined(TARGET_PPC64) - case 8: segv =3D put_user_u64(val, addr); break; - case 16: { - if (val2 =3D=3D env->reserve_val2) { - if (msr_le) { - val2 =3D val; - val =3D env->gpr[reg+1]; - } else { - val2 =3D env->gpr[reg+1]; - } - segv =3D put_user_u64(val, addr); - if (!segv) { - segv =3D put_user_u64(val2, addr + 8); - } - } - break; - } -#endif - default: abort(); - } - if (!segv) { - stored =3D 1; - } - } - } - env->crf[0] =3D (stored << 1) | xer_so; - env->reserve_addr =3D (target_ulong)-1; - } - if (!segv) { - env->nip +=3D 4; - } - mmap_unlock(); - end_exclusive(); - return segv; -} - void cpu_loop(CPUPPCState *env) { CPUState *cs =3D CPU(ppc_env_get_cpu(env)); target_siginfo_t info; - int trapnr; + int trapnr, sig; target_ulong ret; =20 for(;;) { + bool arch_interrupt; + cpu_exec_start(cs); trapnr =3D cpu_exec(cs); cpu_exec_end(cs); process_queued_cpu_work(cs); =20 - switch(trapnr) { + arch_interrupt =3D true; + switch (trapnr) { case POWERPC_EXCP_NONE: /* Just go on */ break; @@ -524,26 +448,15 @@ void cpu_loop(CPUPPCState *env) } env->gpr[3] =3D ret; break; - case POWERPC_EXCP_STCX: - if (do_store_exclusive(env)) { - info.si_signo =3D TARGET_SIGSEGV; + case EXCP_DEBUG: + sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) { + info.si_signo =3D sig; info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->nip; + info.si_code =3D TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP_DEBUG: - { - int sig; - - sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) { - info.si_signo =3D sig; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } + } else { + arch_interrupt =3D false; } break; case EXCP_INTERRUPT: @@ -551,12 +464,22 @@ void cpu_loop(CPUPPCState *env) break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); + arch_interrupt =3D false; break; default: cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr); break; } process_pending_signals(env); + + /* Most of the traps imply a transition through kernel mode, + * which implies an REI instruction has been executed. Which + * means that RX and LOCK_ADDR should be cleared. But there + * are a few exceptions for traps internal to QEMU. + */ + if (arch_interrupt) { + env->reserve_addr =3D -1; + } } } =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 973cf44cda..4edcf62cf7 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -196,7 +196,6 @@ enum { /* QEMU exceptions: special cases we want to stop translation = */ POWERPC_EXCP_SYNC =3D 0x202, /* context synchronizing instruct= ion */ POWERPC_EXCP_SYSCALL_USER =3D 0x203, /* System call in user mode only = */ - POWERPC_EXCP_STCX =3D 0x204 /* Conditional stores in user mode= */ }; =20 /* Exceptions error codes = */ @@ -994,10 +993,6 @@ struct CPUPPCState { /* Reservation value */ target_ulong reserve_val; target_ulong reserve_val2; - /* Reservation store address */ - target_ulong reserve_ea; - /* Reserved store source register and size */ - target_ulong reserve_info; =20 /* Those ones are used in supervisor mode only */ /* machine state register */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c7b9d226eb..03e8c5df03 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3201,19 +3201,6 @@ ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) #endif =20 -#if defined(CONFIG_USER_ONLY) -static void gen_conditional_store(DisasContext *ctx, TCGv EA, - int reg, int memop) -{ - TCGv t0 =3D tcg_temp_new(); - - tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); - tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg); - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); - tcg_temp_free(t0); - gen_exception_err(ctx, POWERPC_EXCP_STCX, 0); -} -#else static void gen_conditional_store(DisasContext *ctx, TCGv EA, int reg, int memop) { @@ -3244,7 +3231,6 @@ static void gen_conditional_store(DisasContext *ctx, = TCGv EA, gen_set_label(l2); tcg_gen_movi_tl(cpu_reserve, -1); } -#endif =20 #define STCX(name, memop) \ static void gen_##name(DisasContext *ctx) \ --=20 2.17.1