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[124.44.6.90]) by smtp.gmail.com with ESMTPSA id j133-v6sm33300282pgc.75.2018.07.02.08.11.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 02 Jul 2018 08:11:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pNLpyMH2MtrDqswU9mlulZblcEuP061D6R6k4Avg5bA=; b=s/VaV3COqRMvbK5zqqBMYWvpz1BIHNXfqlXWcDaRTYnq8Fi09Cf9zLTeaXJS594ptm eH7zoXNk7khxoG/kWo2H2C7J58U9tJ2OAlquI2RqdHf7XAr/abZcc3SsNRLEs3H6HeR8 cDITc7QDPn+NYsFbAjCoX9zENbRtqkS7GSxS6rfWX4JHbveZostJm6kEfmqwQoI0ZKV0 767QiqgWqlELlJevGGyfXqVcEQUOiQjRSmK1L5z+ltxG3CgUjMVre33Pf82//C3ujLRR J/nQ47BH1wOJl8b2kLa4wcfO4mUvDrouu3uY50Xh5adC7Y1tPivpLn5JbO2AKJ08DOTG PqhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pNLpyMH2MtrDqswU9mlulZblcEuP061D6R6k4Avg5bA=; b=razTcf05FqHBr3rp7g2HQ1GiMGRdFKtqnXRQT1rsucTdl6hpGvuuu6z8pFw7gyXqjf NI+fbba5/PKsp6h5Br0lxCnY7g57Uc16+IUAkPGWsxF8GoMXe0yWiMKVV1DZKdsOnCLR EPi3Hy/4cqwh3SuthnTY3cpKSxK+0sZu3Gk81ui3VKAcEZ8OM45OXqTmKbffdwMVANRI QWXYxrotQXsAXQ0qJVtWnI4yEzkjK//j+9H/pVLYwPX2vESPxc0MXCUHRPhi/xsrSbZI KZ8lD1CWoq264drnBm0RPchqaYncnosx9Yt/Wp4vRte2Ma0hnBTr8SmlbSKtWBcF0fZF wOLg== X-Gm-Message-State: APt69E0NN1Iu/2Pb0yPKfEZ1mfCPotiB/coBHprOheDQGn3UcnXNby8g BywngUl9sPOe4/4OOKbEqGA= X-Google-Smtp-Source: ADUXVKI/SRE3CmAH6rKVM+fJaxjy4n0Rgt7IqxgidyV9jJKKE4FCBHEK2VvAx0gaddvBrGT2P2TJMw== X-Received: by 2002:a17:902:2983:: with SMTP id h3-v6mr26365717plb.232.1530544285670; Mon, 02 Jul 2018 08:11:25 -0700 (PDT) From: Stafford Horne To: Peter Maydell Date: Tue, 3 Jul 2018 00:10:17 +0900 Message-Id: <20180702151023.24532-20-shorne@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180702151023.24532-1-shorne@gmail.com> References: <20180702151023.24532-1-shorne@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22b Subject: [Qemu-devel] [PULL v2 19/25] target/openrisc: Increase the TLB size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Richard Henderson , QEMU Development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson The architecture supports 128 TLB entries. There is no reason not to provide all of them. In the process we need to fix a bug that failed to parameterize the configuration register that tells the operating system the number of entries. Signed-off-by: Richard Henderson Signed-off-by: Stafford Horne --- v2: - Change VMState version. --- target/openrisc/cpu.c | 6 ++++-- target/openrisc/cpu.h | 2 +- target/openrisc/machine.c | 5 ++--- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b92de51ecf..e01ce9ed1c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -57,8 +57,10 @@ static void openrisc_cpu_reset(CPUState *s) =20 cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; - cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 <= < 2)); - cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 <= < 2)); + cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) + | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); + cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) + | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); =20 #ifndef CONFIG_USER_ONLY cpu->env.picmr =3D 0x00000000; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 47e94659e1..b180e30e9e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,7 +222,7 @@ enum { =20 /* TLB size */ enum { - TLB_SIZE =3D 64, + TLB_SIZE =3D 128, TLB_MASK =3D TLB_SIZE - 1, }; =20 diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 3fc837b925..1eedbf3dbe 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -38,9 +38,8 @@ static const VMStateDescription vmstate_tlb_entry =3D { =20 static const VMStateDescription vmstate_cpu_tlb =3D { .name =3D "cpu_tlb", - .version_id =3D 1, - .minimum_version_id =3D 1, - .minimum_version_id_old =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), --=20 2.17.0