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[124.44.6.90]) by smtp.gmail.com with ESMTPSA id r77-v6sm10359036pfr.117.2018.07.02.06.59.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 02 Jul 2018 06:59:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=efDCn0n+AeRfqOb3vCf/lumK4UA9AxiW92CgAjMjKNo=; b=hsvZ+n7ZOrdh7yg0bnGipfF0w1/p6fszbLJZeJzq7NAZ4Q4iUdyo5sQw/KaaW3F6ro eGKDfWuELELsKHDQdi6ym59CYqzrb1CVkfcATQlcr+TxVu4alqNARrYTOV9/YCKihD7H x3lhBede7LzvV02Wlfv8syOsSk6ms1W1p2jZ0ecH/PGvb5VeAq0n8sTZbFUdrVRZwCjq DpHw4FGPSl0SE5t+KfdmL85hvpfzemicU3c7clNG1W91eGHr2nXeoi6KgWwtJTEM/3ze m7IaImXJZb6iKWButXQyoEWTk1D96vsj7b29z0i4YYBODGEoltuOB+RNUvKt1+wBJY/L MjFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=efDCn0n+AeRfqOb3vCf/lumK4UA9AxiW92CgAjMjKNo=; b=iA3UBVRmIIW8GfdE2sc5GufSLkoATxdfmN9d9AdNHRtElceDHVYtYiWVJhZGOb5fNy HpuRS/XoX92fU4r1ILV19kwKcTQrbkJrq9SnCS07HZPgxsWaFINVudRTPSRs29dXsncJ O0UOWppV86L3P+tk6zkZ14EY9793WygitNN7YT9BvThu/4Hqo2QXaUVtOFqd+5ObKixp NHa+top2Q4bXbdlbkaqgETggqE3SYGjzBCZSSq6DCfIuAD322mblA8sCGGgSoO+ge+oJ RfTMW6HAj/UqbLmdFnvFEjNkgpFCKBEZmKi6QyU8T2lvqaz/aDDQv359HAUBS0kuCrHW aurQ== X-Gm-Message-State: APt69E1BhBy9MO1lQtU/TAOOL/jDh4Wi8lDqE8qJXw7Scd4T4SDj4mKV 5zISvITId2Mcx4hAO4Joe+M= X-Google-Smtp-Source: ADUXVKIWbjIoNB51i8Ah2OOFgakppKYSu76ivW2w3TlMyjsAnJlSUvI92YbiWf7ztemrn5DQw0820Q== X-Received: by 2002:a17:902:bb8a:: with SMTP id m10-v6mr25877893pls.236.1530539952154; Mon, 02 Jul 2018 06:59:12 -0700 (PDT) From: Stafford Horne To: Peter Maydell Date: Mon, 2 Jul 2018 22:58:05 +0900 Message-Id: <20180702135806.7087-25-shorne@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180702135806.7087-1-shorne@gmail.com> References: <20180702135806.7087-1-shorne@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PULL 24/25] target/openrisc: Fix delay slot exception flag to match spec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , QEMU Development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The delay slot exception flag is only set on the SR register during exception. Previously it was being set on both the ESR and SR this caused QEMU to differ from the spec. The was apparent as the linux kernel had a bug where it could boot on QEMU but not on real hardware. The fixed logic now matches hardware. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/interrupt.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 138ad17f00..bbae956361 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -35,13 +35,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) int exception =3D cs->exception_index; =20 env->epcr =3D env->pc; - if (env->dflag) { - env->dflag =3D 0; - env->sr |=3D SR_DSX; - env->epcr -=3D 4; - } else { - env->sr &=3D ~SR_DSX; - } if (exception =3D=3D EXCP_SYSCALL) { env->epcr +=3D 4; } @@ -51,7 +44,10 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->eear =3D env->pc; } =20 + /* During exceptions esr is populared with the pre-exception sr. */ env->esr =3D cpu_get_sr(env); + /* In parallel sr is updated to disable mmu, interrupts, timers and + set the delay slot exception flag. */ env->sr &=3D ~SR_DME; env->sr &=3D ~SR_IME; env->sr |=3D SR_SM; @@ -61,6 +57,15 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->pmr &=3D ~PMR_SME; env->lock_addr =3D -1; =20 + /* Set/clear dsx to indicate if we are in a delay slot exception. */ + if (env->dflag) { + env->dflag =3D 0; + env->sr |=3D SR_DSX; + env->epcr -=3D 4; + } else { + env->sr &=3D ~SR_DSX; + } + if (exception > 0 && exception < EXCP_NR) { static const char * const int_name[EXCP_NR] =3D { [EXCP_RESET] =3D "RESET", --=20 2.17.0