From nobody Tue Nov 4 19:03:28 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530540357064598.7184353461782; Mon, 2 Jul 2018 07:05:57 -0700 (PDT) Received: from localhost ([::1]:32980 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fZzSh-0007mn-8b for importer@patchew.org; Mon, 02 Jul 2018 10:05:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47390) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fZzLp-0002Tq-1N for qemu-devel@nongnu.org; Mon, 02 Jul 2018 09:58:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fZzLn-0008AY-I9 for qemu-devel@nongnu.org; Mon, 02 Jul 2018 09:58:45 -0400 Received: from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:34248) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fZzLn-0008AF-8b for qemu-devel@nongnu.org; Mon, 02 Jul 2018 09:58:43 -0400 Received: by mail-pg0-x22a.google.com with SMTP id y5-v6so917431pgv.1 for ; Mon, 02 Jul 2018 06:58:43 -0700 (PDT) Received: from localhost (g90.124-44-6.ppp.wakwak.ne.jp. [124.44.6.90]) by smtp.gmail.com with ESMTPSA id i188-v6sm17044357pfc.3.2018.07.02.06.58.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 02 Jul 2018 06:58:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u+YJliszgwkY8rbcE/JLOHssHRTMCNlXvsTX0k06qok=; b=SxqODgB+zW2UCdwuMXdePb+ZVbRRMC2TXMzfujN289jK2QDOF/CEVU0DpuyoipFBnz trSYGjyaVHUja9+kdmNHC4uKSMsPZ3rMTXOuZr5FlLYQlW2TZ3Dnig6qmBNcAAyhOJk5 55GMGhs9jugBoxpumLf7kPpmH3RJjsZ0vqVAPCoDYuQGOWBq8jh23R3kBsSiUq8Cyj/T EQi6vakdqA7qNyKh55xg1YhblcPkpc6fyyze01O7+TxmNpqOeR+4n/sGVAhIeU5mF2q5 7vIBZY3P62TFIzqNCw1F79H3YnEqSGSYtj33KD6OCwDOKmNBz8Z0oAtnkOyZOgALGsL4 qiAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u+YJliszgwkY8rbcE/JLOHssHRTMCNlXvsTX0k06qok=; b=MUUT4lWiInKEr9gJErixL3gyf45opPR5/h+bm4ZDZYXz0p+TvInLmIMlJ6uH9hC0s8 RmJABS1hrgL2YknEBXmOewaMe7/vRKYFa4/AX0YQCPoF3xuROVyOXl90sBFbUsMmCgqC 99zG5qF6CQDxqAyX0/rOSI9QTrwYq//xiiJQcAh4+tVwNIfg4KFTLPJ/aO2dnok5u2oE ZlS4GgTOJ4BXkBafZGnaLPoMTYGswZy60xFz2IeqR+Uemdp2rnxt98nv22U8z8RMq5dA VYNPScl4yJK0vGrsIoLHFMxZGUp6sJKEPG0wUz8LabCbTvOFh+a8f0kOcms9BBR9UBpo KdsA== X-Gm-Message-State: APt69E2LjYEyRpyYEtqOeWrTM3RYGMLEbNUMUwkhqkFO4L2LouvzYfs5 98nJx6SUakMjIfpRRQ+UP8Y= X-Google-Smtp-Source: AAOMgpcTP8o8udb9/OKw8eMO2JB2cH1uLWQENhp3U/KU4a1B/ITfQqM3TcZNN+lCkqhkGXTgEte0xA== X-Received: by 2002:a62:c8c2:: with SMTP id i63-v6mr9709810pfk.73.1530539922209; Mon, 02 Jul 2018 06:58:42 -0700 (PDT) From: Stafford Horne To: Peter Maydell Date: Mon, 2 Jul 2018 22:57:53 +0900 Message-Id: <20180702135806.7087-13-shorne@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180702135806.7087-1-shorne@gmail.com> References: <20180702135806.7087-1-shorne@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PULL 12/25] target/openrisc: Remove indirect function calls for mmu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Richard Henderson , QEMU Development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson There is no reason to use an indirect branch instead of simply testing the SR bits that control mmu state. Signed-off-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/cpu.c | 4 -- target/openrisc/cpu.h | 11 ----- target/openrisc/interrupt.c | 2 - target/openrisc/interrupt_helper.c | 25 ++--------- target/openrisc/machine.c | 26 ------------ target/openrisc/mmu.c | 68 +++++++++++++----------------- target/openrisc/sys_helper.c | 15 ------- 7 files changed, 32 insertions(+), 119 deletions(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index fa8e342ff7..b92de51ecf 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -92,10 +92,6 @@ static void openrisc_cpu_initfn(Object *obj) OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 cs->env_ptr =3D &cpu->env; - -#ifndef CONFIG_USER_ONLY - cpu_openrisc_mmu_init(cpu); -#endif } =20 /* CPU models */ diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 96b7f58659..a27adad085 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -379,17 +379,6 @@ void cpu_openrisc_count_update(OpenRISCCPU *cpu); void cpu_openrisc_timer_update(OpenRISCCPU *cpu); void cpu_openrisc_count_start(OpenRISCCPU *cpu); void cpu_openrisc_count_stop(OpenRISCCPU *cpu); - -void cpu_openrisc_mmu_init(OpenRISCCPU *cpu); -int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw); -int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw); -int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw); #endif =20 #define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 2d0b55afa9..23abcf29ed 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -63,8 +63,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr &=3D ~SR_TEE; env->pmr &=3D ~PMR_DME; env->pmr &=3D ~PMR_SME; - env->tlb.cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_nomm= u; - env->tlb.cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_nomm= u; env->lock_addr =3D -1; =20 if (exception > 0 && exception < EXCP_NR) { diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt= _helper.c index dc97b38704..a2e9003969 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -29,31 +29,12 @@ void HELPER(rfe)(CPUOpenRISCState *env) #ifndef CONFIG_USER_ONLY int need_flush_tlb =3D (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^ (cpu->env.esr & (SR_SM | SR_IME | SR_DME)); -#endif - cpu->env.pc =3D cpu->env.epcr; - cpu_set_sr(&cpu->env, cpu->env.esr); - cpu->env.lock_addr =3D -1; - -#ifndef CONFIG_USER_ONLY - if (cpu->env.sr & SR_DME) { - cpu->env.tlb.cpu_openrisc_map_address_data =3D - &cpu_openrisc_get_phys_data; - } else { - cpu->env.tlb.cpu_openrisc_map_address_data =3D - &cpu_openrisc_get_phys_nommu; - } - - if (cpu->env.sr & SR_IME) { - cpu->env.tlb.cpu_openrisc_map_address_code =3D - &cpu_openrisc_get_phys_code; - } else { - cpu->env.tlb.cpu_openrisc_map_address_code =3D - &cpu_openrisc_get_phys_nommu; - } - if (need_flush_tlb) { CPUState *cs =3D CPU(cpu); tlb_flush(cs); } #endif + cpu->env.pc =3D cpu->env.epcr; + cpu->env.lock_addr =3D -1; + cpu_set_sr(&cpu->env, cpu->env.esr); } diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index c10d28b055..73e0abcfd7 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -24,31 +24,6 @@ #include "hw/boards.h" #include "migration/cpu.h" =20 -static int env_post_load(void *opaque, int version_id) -{ - CPUOpenRISCState *env =3D opaque; - - /* Restore MMU handlers */ - if (env->sr & SR_DME) { - env->tlb.cpu_openrisc_map_address_data =3D - &cpu_openrisc_get_phys_data; - } else { - env->tlb.cpu_openrisc_map_address_data =3D - &cpu_openrisc_get_phys_nommu; - } - - if (env->sr & SR_IME) { - env->tlb.cpu_openrisc_map_address_code =3D - &cpu_openrisc_get_phys_code; - } else { - env->tlb.cpu_openrisc_map_address_code =3D - &cpu_openrisc_get_phys_nommu; - } - - - return 0; -} - static const VMStateDescription vmstate_tlb_entry =3D { .name =3D "tlb_entry", .version_id =3D 1, @@ -102,7 +77,6 @@ static const VMStateDescription vmstate_env =3D { .name =3D "env", .version_id =3D 6, .minimum_version_id =3D 6, - .post_load =3D env_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), VMSTATE_UINTTL(pc, CPUOpenRISCState), diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 5665bb7cc9..b2effaa6d7 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -29,18 +29,16 @@ #endif =20 #ifndef CONFIG_USER_ONLY -int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw) +static inline int get_phys_nommu(hwaddr *physical, int *prot, + target_ulong address) { *physical =3D address; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TLBRET_MATCH; } =20 -int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw) +static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, + target_ulong address, int rw, bool supervisor) { int vpn =3D address >> TARGET_PAGE_BITS; int idx =3D vpn & ITLB_MASK; @@ -52,8 +50,7 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) { return TLBRET_INVALID; } - - if (cpu->env.sr & SR_SM) { /* supervisor mode */ + if (supervisor) { if (cpu->env.tlb.itlb[0][idx].tr & SXE) { right |=3D PAGE_EXEC; } @@ -62,7 +59,6 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, right |=3D PAGE_EXEC; } } - if ((rw & 2) && ((right & PAGE_EXEC) =3D=3D 0)) { return TLBRET_BADADDR; } @@ -73,9 +69,8 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, return TLBRET_MATCH; } =20 -int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw) +static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, + target_ulong address, int rw, bool supervisor) { int vpn =3D address >> TARGET_PAGE_BITS; int idx =3D vpn & DTLB_MASK; @@ -87,8 +82,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) { return TLBRET_INVALID; } - - if (cpu->env.sr & SR_SM) { /* supervisor mode */ + if (supervisor) { if (cpu->env.tlb.dtlb[0][idx].tr & SRE) { right |=3D PAGE_READ; } @@ -117,20 +111,24 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, return TLBRET_MATCH; } =20 -static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, - int rw) +static int get_phys_addr(OpenRISCCPU *cpu, hwaddr *physical, + int *prot, target_ulong address, int rw) { - int ret =3D TLBRET_MATCH; - - if (rw =3D=3D MMU_INST_FETCH) { /* ITLB */ - *physical =3D 0; - ret =3D cpu->env.tlb.cpu_openrisc_map_address_code(cpu, physical, - prot, address, r= w); - } else { /* DTLB */ - ret =3D cpu->env.tlb.cpu_openrisc_map_address_data(cpu, physical, - prot, address, r= w); + bool supervisor =3D (cpu->env.sr & SR_SM) !=3D 0; + int ret; + + /* Assume nommu results for a moment. */ + ret =3D get_phys_nommu(physical, prot, address); + + /* Overwrite with TLB lookup if enabled. */ + if (rw =3D=3D MMU_INST_FETCH) { + if (cpu->env.sr & SR_IME) { + ret =3D get_phys_code(cpu, physical, prot, address, rw, superv= isor); + } + } else { + if (cpu->env.sr & SR_DME) { + ret =3D get_phys_data(cpu, physical, prot, address, rw, superv= isor); + } } =20 return ret; @@ -186,8 +184,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr a= ddress, int size, hwaddr physical =3D 0; int prot =3D 0; =20 - ret =3D cpu_openrisc_get_phys_addr(cpu, &physical, &prot, - address, rw); + ret =3D get_phys_addr(cpu, &physical, &prot, address, rw); =20 if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, @@ -225,17 +222,16 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs,= vaddr addr) =20 /* Check memory for any kind of address, since during debug the gdb can ask for anything, check data tlb for address */ - miss =3D cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0); + miss =3D get_phys_addr(cpu, &phys_addr, &prot, addr, 0); =20 /* Check instruction tlb */ if (miss) { - miss =3D cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, - MMU_INST_FETCH); + miss =3D get_phys_addr(cpu, &phys_addr, &prot, addr, MMU_INST_FETC= H); } =20 /* Last, fall back to a plain address */ if (miss) { - miss =3D cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr,= 0); + miss =3D get_phys_nommu(&phys_addr, &prot, addr); } =20 if (miss) { @@ -244,10 +240,4 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) return phys_addr; } } - -void cpu_openrisc_mmu_init(OpenRISCCPU *cpu) -{ - cpu->env.tlb.cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_= nommu; - cpu->env.tlb.cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_= nommu; -} #endif diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index ff315f6f1a..9b4339b34e 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -60,21 +60,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong s= pr, target_ulong rb) tlb_flush(cs); } cpu_set_sr(env, rb); - if (env->sr & SR_DME) { - env->tlb.cpu_openrisc_map_address_data =3D - &cpu_openrisc_get_phys_data; - } else { - env->tlb.cpu_openrisc_map_address_data =3D - &cpu_openrisc_get_phys_nommu; - } - - if (env->sr & SR_IME) { - env->tlb.cpu_openrisc_map_address_code =3D - &cpu_openrisc_get_phys_code; - } else { - env->tlb.cpu_openrisc_map_address_code =3D - &cpu_openrisc_get_phys_nommu; - } break; =20 case TO_SPR(0, 18): /* PPC */ --=20 2.17.0