From nobody Mon Feb 9 03:15:51 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530302928688997.3261024079163; Fri, 29 Jun 2018 13:08:48 -0700 (PDT) Received: from localhost ([::1]:44242 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYzhH-00066x-WA for importer@patchew.org; Fri, 29 Jun 2018 16:08:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47156) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYzfx-0005Nq-6h for qemu-devel@nongnu.org; Fri, 29 Jun 2018 16:07:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYzfs-0002x8-77 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 16:07:25 -0400 Received: from mail-qk0-x231.google.com ([2607:f8b0:400d:c09::231]:44176) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYzfr-0002wT-VO for qemu-devel@nongnu.org; Fri, 29 Jun 2018 16:07:20 -0400 Received: by mail-qk0-x231.google.com with SMTP id i188-v6so5620358qkc.11 for ; Fri, 29 Jun 2018 13:07:19 -0700 (PDT) Received: from x1.local ([138.117.48.222]) by smtp.gmail.com with ESMTPSA id b40-v6sm9340991qtb.87.2018.06.29.13.07.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 29 Jun 2018 13:07:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=JnB4AIyedyF0Pyn6Kv5RxDj6fCRzyYpQxiefB2b4SQI=; b=K0pHse4RI6drW06skUM6KEc2Z6lNKvn+L2pcVieKupyg9WGJUrVfZZ1FiBEUul/zvc gJ/v6nJhfWxw+c1MpWz/LkVAGTP2nnrB4dhuu3uPlscKSMdN1A6q0jlBfVM7+gOYkzBE yOgnZwCjAUyZN42m4slNk16SkUKpJZLVy4XAV3A3DooyOjr5axBv05DdeP4jGLQ84ciw szZDFZ/bn3f5z8v7J9/++4KlfZ0OyhUeNcQV0akjguDLYb5T/zbKrGLqcvkPK8P47ILP KjIntci6bjPWzjfHsFhJxVV9CA28uXinbRqRfDiHbfnBg4Dct18mUmNgytRxp15zHacl FpvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=JnB4AIyedyF0Pyn6Kv5RxDj6fCRzyYpQxiefB2b4SQI=; b=qiiqPoxGlM6jMR53Iy/WGRrAQjFNsPr7k/uwBJG0SIZf4+XlwZ+TYozRF2A56F3gZa V8QS9+9qDbsUew02z3uvKkfCuqYOH7ZIPJ1E1XGWOxzLPvJ4UYeu2rl9Jv2Qnyeqz9IQ LCKjVTl4Xv4kuKDSfkJU7E6jN/pvJ/Gac1GLWeeFkUKR0NoxlTZsWQfoD20bZvCER0mU q6d62vYvvq7BDH5i/qNXKEF/Gl+OHGKcxRN61/hFB3+WtL+JiCkInjdZqqPh+DjAr2gF 9EgLtO013mg3QvSrwI1WemexoOFMRr4CDxmFR7JDPhLDtxGv3cgcJdQzf0mY9qpU/KLg +EJQ== X-Gm-Message-State: APt69E32OpHxjIdnC3C8y4tKtPenA+4cxlINTDI429kwcm0mzBFvyaPF I+V6YUKW7crw2Zy6bYungi4= X-Google-Smtp-Source: AAOMgpc9AugGwSFxgL7YW81fLW5VUCUSuXeoploVD2X/A4mVTnIZm0lbPaMBHqHKL4D/lo+Yq4qszw== X-Received: by 2002:a37:8fc3:: with SMTP id r186-v6mr14202291qkd.27.1530302839424; Fri, 29 Jun 2018 13:07:19 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Peter Maydell , Richard Henderson Date: Fri, 29 Jun 2018 17:07:10 -0300 Message-Id: <20180629200710.27626-1-f4bug@amsat.org> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::231 Subject: [Qemu-devel] [PATCH] tcg: Fix --disable-tcg build breakage X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Crosthwaite , "Emilio G . Cota" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Fix the --disable-tcg breakage introduced by 8bca9a03ec60d: $ configure --disable-tcg [...] $ make -C i386-softmmu exec.o make: Entering directory 'i386-softmmu' CC exec.o In file included from source/qemu/exec.c:62:0: source/qemu/include/exec/ram_addr.h:96:6: error: conflicting types for = =E2=80=98tb_invalidate_phys_range=E2=80=99 void tb_invalidate_phys_range(ram_addr_t start, ram_addr_t end); ^~~~~~~~~~~~~~~~~~~~~~~~ In file included from source/qemu/exec.c:24:0: source/qemu/include/exec/exec-all.h:309:6: note: previous declaration o= f =E2=80=98tb_invalidate_phys_range=E2=80=99 was here void tb_invalidate_phys_range(target_ulong start, target_ulong end); ^~~~~~~~~~~~~~~~~~~~~~~~ source/qemu/exec.c:1043:6: error: conflicting types for =E2=80=98tb_inv= alidate_phys_addr=E2=80=99 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs= attrs) ^~~~~~~~~~~~~~~~~~~~~~~ In file included from source/qemu/exec.c:24:0: source/qemu/include/exec/exec-all.h:308:6: note: previous declaration o= f =E2=80=98tb_invalidate_phys_addr=E2=80=99 was here void tb_invalidate_phys_addr(target_ulong addr); ^~~~~~~~~~~~~~~~~~~~~~~ make: *** [source/qemu/rules.mak:69: exec.o] Error 1 make: Leaving directory 'i386-softmmu' Tested to build x86_64-softmmu and i386-softmmu targets. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/exec-all.h | 13 +++++++++---- accel/stubs/tcg-stub.c | 6 ++++++ exec.c | 2 +- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 6a7e7a866e..cb497dee0b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -255,7 +255,6 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs att= rs); void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_i= dx, uintptr_t retaddr); #else @@ -304,9 +303,6 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(= CPUState *cpu, uint16_t idxmap) { } - -void tb_invalidate_phys_addr(target_ulong addr); -void tb_invalidate_phys_range(target_ulong start, target_ulong end); #endif =20 #define CODE_GEN_ALIGN 16 /* must be >=3D of the size of a icach= e line */ @@ -415,6 +411,15 @@ static inline uint32_t curr_cflags(void) | (use_icount ? CF_USE_ICOUNT : 0); } =20 +/* TranslationBlock invalidate API */ +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) +void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs att= rs); +#else +void tb_invalidate_phys_addr(target_ulong addr); +#endif +#if defined(CONFIG_USER_ONLY) +void tb_invalidate_phys_range(target_ulong start, target_ulong end); +#endif void tb_flush(CPUState *cpu); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index 76ae461749..8ee85ed665 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -16,6 +16,7 @@ #include "tcg/tcg.h" #include "exec/cpu-common.h" #include "exec/exec-all.h" +#include "translate-all.h" =20 void tb_flush(CPUState *cpu) { @@ -24,3 +25,8 @@ void tb_flush(CPUState *cpu) void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) { } + +void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t en= d, + int is_cpu_write_access) +{ +} diff --git a/exec.c b/exec.c index cdcf769daa..ee726888a5 100644 --- a/exec.c +++ b/exec.c @@ -1027,7 +1027,7 @@ const char *parse_cpu_model(const char *cpu_model) return cpu_type; } =20 -#if defined(CONFIG_USER_ONLY) +#if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG) void tb_invalidate_phys_addr(target_ulong addr) { mmap_lock(); --=20 2.18.0