From nobody Sun Feb 8 19:58:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530286572092382.29783825337506; Fri, 29 Jun 2018 08:36:12 -0700 (PDT) Received: from localhost ([::1]:42998 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYvRT-0000j1-52 for importer@patchew.org; Fri, 29 Jun 2018 11:36:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34341) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYunB-0007w7-Ul for qemu-devel@nongnu.org; Fri, 29 Jun 2018 10:54:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYunA-0007ur-Of for qemu-devel@nongnu.org; Fri, 29 Jun 2018 10:54:34 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43132) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fYunA-0007rD-HL for qemu-devel@nongnu.org; Fri, 29 Jun 2018 10:54:32 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fYun9-0004qz-EK for qemu-devel@nongnu.org; Fri, 29 Jun 2018 15:54:31 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:53:44 +0100 Message-Id: <20180629145347.652-53-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629145347.652-1-peter.maydell@linaro.org> References: <20180629145347.652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 52/55] target/arm: Fix SVE system register access checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Richard Henderson Leave ARM_CP_SVE, removing ARM_CP_FPU; the sve_access_check produced by the flag already includes fp_access_check. If we also check ARM_CP_FPU the double fp_access_check asserts. Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Reviewed-by: Laurent Desnogues Message-id: 20180629001538.11415-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 8 ++++---- target/arm/translate-a64.c | 5 ++--- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 60589b7eaf9..ae70b874c71 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4414,7 +4414,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, static const ARMCPRegInfo zcr_el1_reginfo =3D { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, + .access =3D PL1_RW, .type =3D ARM_CP_SVE, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; @@ -4422,7 +4422,7 @@ static const ARMCPRegInfo zcr_el1_reginfo =3D { static const ARMCPRegInfo zcr_el2_reginfo =3D { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, + .access =3D PL2_RW, .type =3D ARM_CP_SVE, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; @@ -4430,14 +4430,14 @@ static const ARMCPRegInfo zcr_el2_reginfo =3D { static const ARMCPRegInfo zcr_no_el2_reginfo =3D { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, + .access =3D PL2_RW, .type =3D ARM_CP_SVE, .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }; =20 static const ARMCPRegInfo zcr_el3_reginfo =3D { .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, + .access =3D PL3_RW, .type =3D ARM_CP_SVE, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f9863408324..45a6c2a3aa1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1633,11 +1633,10 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, default: break; } - if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { - return; - } if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { return; + } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { + return; } =20 if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO))= { --=20 2.17.1