From nobody Thu Dec 18 19:37:01 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530285967499569.7079540342029; Fri, 29 Jun 2018 08:26:07 -0700 (PDT) Received: from localhost ([::1]:42943 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYvHi-000151-K9 for importer@patchew.org; Fri, 29 Jun 2018 11:26:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34143) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYun0-0007hE-OX for qemu-devel@nongnu.org; Fri, 29 Jun 2018 10:54:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYumz-0007MV-H7 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 10:54:22 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43116) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fYumz-0007Hs-7u for qemu-devel@nongnu.org; Fri, 29 Jun 2018 10:54:21 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fYumy-0004k8-3K for qemu-devel@nongnu.org; Fri, 29 Jun 2018 15:54:20 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:53:29 +0100 Message-Id: <20180629145347.652-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629145347.652-1-peter.maydell@linaro.org> References: <20180629145347.652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 37/55] target/arm: Implement SVE fp complex multiply add (indexed) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Richard Henderson Enhance the existing helpers to support SVE, which takes the index from each 128-bit segment. The change has no effect for AdvSIMD, since there is only one such segment. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Message-id: 20180627043328.11531-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-sve.c | 23 ++++++++++++++++++ target/arm/vec_helper.c | 50 +++++++++++++++++++++++--------------- target/arm/sve.decode | 6 +++++ 3 files changed, 59 insertions(+), 20 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index c47bcec5349..7912bceb1e0 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4005,6 +4005,29 @@ static bool trans_FCMLA_zpzzz(DisasContext *s, return true; } =20 +static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a, uint32_t = insn) +{ + static gen_helper_gvec_3_ptr * const fns[2] =3D { + gen_helper_gvec_fcmlah_idx, + gen_helper_gvec_fcmlas_idx, + }; + + tcg_debug_assert(a->esz =3D=3D 1 || a->esz =3D=3D 2); + tcg_debug_assert(a->rd =3D=3D a->ra); + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + status, vsz, vsz, + a->index * 4 + a->rot, + fns[a->esz - 1]); + tcg_temp_free_ptr(status); + } + return true; +} + /* *** SVE Floating Point Unary Operations Predicated Group */ diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 8f2dc4b9893..db5aeb9f24f 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -319,22 +319,27 @@ void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void= *vm, uint32_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); intptr_t index =3D extract32(desc, SIMD_DATA_SHIFT + 2, 2); uint32_t neg_real =3D flip ^ neg_imag; - uintptr_t i; - float16 e1 =3D m[H2(2 * index + flip)]; - float16 e3 =3D m[H2(2 * index + 1 - flip)]; + intptr_t elements =3D opr_sz / sizeof(float16); + intptr_t eltspersegment =3D 16 / sizeof(float16); + intptr_t i, j; =20 /* Shift boolean to the sign bit so we can xor to negate. */ neg_real <<=3D 15; neg_imag <<=3D 15; - e1 ^=3D neg_real; - e3 ^=3D neg_imag; =20 - for (i =3D 0; i < opr_sz / 2; i +=3D 2) { - float16 e2 =3D n[H2(i + flip)]; - float16 e4 =3D e2; + for (i =3D 0; i < elements; i +=3D eltspersegment) { + float16 mr =3D m[H2(i + 2 * index + 0)]; + float16 mi =3D m[H2(i + 2 * index + 1)]; + float16 e1 =3D neg_real ^ (flip ? mi : mr); + float16 e3 =3D neg_imag ^ (flip ? mr : mi); =20 - d[H2(i)] =3D float16_muladd(e2, e1, d[H2(i)], 0, fpst); - d[H2(i + 1)] =3D float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst); + for (j =3D i; j < i + eltspersegment; j +=3D 2) { + float16 e2 =3D n[H2(j + flip)]; + float16 e4 =3D e2; + + d[H2(j)] =3D float16_muladd(e2, e1, d[H2(j)], 0, fpst); + d[H2(j + 1)] =3D float16_muladd(e4, e3, d[H2(j + 1)], 0, fpst); + } } clear_tail(d, opr_sz, simd_maxsz(desc)); } @@ -380,22 +385,27 @@ void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void= *vm, uint32_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); intptr_t index =3D extract32(desc, SIMD_DATA_SHIFT + 2, 2); uint32_t neg_real =3D flip ^ neg_imag; - uintptr_t i; - float32 e1 =3D m[H4(2 * index + flip)]; - float32 e3 =3D m[H4(2 * index + 1 - flip)]; + intptr_t elements =3D opr_sz / sizeof(float32); + intptr_t eltspersegment =3D 16 / sizeof(float32); + intptr_t i, j; =20 /* Shift boolean to the sign bit so we can xor to negate. */ neg_real <<=3D 31; neg_imag <<=3D 31; - e1 ^=3D neg_real; - e3 ^=3D neg_imag; =20 - for (i =3D 0; i < opr_sz / 4; i +=3D 2) { - float32 e2 =3D n[H4(i + flip)]; - float32 e4 =3D e2; + for (i =3D 0; i < elements; i +=3D eltspersegment) { + float32 mr =3D m[H4(i + 2 * index + 0)]; + float32 mi =3D m[H4(i + 2 * index + 1)]; + float32 e1 =3D neg_real ^ (flip ? mi : mr); + float32 e3 =3D neg_imag ^ (flip ? mr : mi); =20 - d[H4(i)] =3D float32_muladd(e2, e1, d[H4(i)], 0, fpst); - d[H4(i + 1)] =3D float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst); + for (j =3D i; j < i + eltspersegment; j +=3D 2) { + float32 e2 =3D n[H4(j + flip)]; + float32 e4 =3D e2; + + d[H4(j)] =3D float32_muladd(e2, e1, d[H4(j)], 0, fpst); + d[H4(j + 1)] =3D float32_muladd(e4, e3, d[H4(j + 1)], 0, fpst); + } } clear_tail(d, opr_sz, simd_maxsz(desc)); } diff --git a/target/arm/sve.decode b/target/arm/sve.decode index e342cfdf146..62365ed90f6 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -733,6 +733,12 @@ FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm= :5 rd:5 \ FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \ ra=3D%reg_movprfx =20 +# SVE floating-point complex multiply-add (indexed) +FCMLA_zzxz 01100100 10 1 index:2 rm:3 0001 rot:2 rn:5 rd:5 \ + ra=3D%reg_movprfx esz=3D1 +FCMLA_zzxz 01100100 11 1 index:1 rm:4 0001 rot:2 rn:5 rd:5 \ + ra=3D%reg_movprfx esz=3D2 + ### SVE FP Multiply-Add Indexed Group =20 # SVE floating-point multiply-add (indexed) --=20 2.17.1