From nobody Tue Feb 10 07:42:19 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530280518641295.2781777840896; Fri, 29 Jun 2018 06:55:18 -0700 (PDT) Received: from localhost ([::1]:42294 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtrp-0001jY-Qm for importer@patchew.org; Fri, 29 Jun 2018 09:55:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38257) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtUO-0007rK-EA for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:31:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYtUM-0007ie-5W for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:31:04 -0400 Received: from greensocs.com ([193.104.36.180]:58611) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtU2-0006m5-8w; Fri, 29 Jun 2018 09:30:42 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id CED264434B2; Fri, 29 Jun 2018 15:30:34 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HbcaejfxgBQh; Fri, 29 Jun 2018 15:30:33 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 4BA684434B1; Fri, 29 Jun 2018 15:30:33 +0200 (CEST) Received: from michell-laptop.hive.antfield.fr (LFbn-LYO-1-488-36.w2-7.abo.wanadoo.fr [2.7.77.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 925DE4434A8; Fri, 29 Jun 2018 15:30:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279034; bh=B6zK56OBGB4g91rZGkZo0kAVasfVo6Uky406CxylDOE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=EWEnCt95vFqSMnVe+qpy4TEtMiqbcNnmn27OlGdqlbOgda+vfx6AIJvzNfWan9Vct rUlN4AjKEuK9Zuy88Y4cCJxE4LaF1V5qN7XJQ6qbBU5qyxZnQC/l4csfdfMqs+03+v OJvrprdCCGgEXdPiCWBBs8zTnLm2FPk1mZXd28uA= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=Dv+cZVXd; dkim=pass (1024-bit key) header.d=greensocs.com header.b=7CZ+UJF7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279033; bh=B6zK56OBGB4g91rZGkZo0kAVasfVo6Uky406CxylDOE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Dv+cZVXdmcT3Rg1JLI4fVGn+dRcwGZSwKdLxKLTGjM9MuoUHEyyMnAI+xvSPnwzyf xuG9R70klNHmx86HmrKv20aiqCAZScWWoaGgDisFiKpba+WeuAzp9q8fgosNCP7g7U 8Ba+UCTBYIPlKfMjuN4jWs7P7bdtAj+epiIlImkA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279032; bh=B6zK56OBGB4g91rZGkZo0kAVasfVo6Uky406CxylDOE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=7CZ+UJF796wt17uQc8W9C8mm8yZHGT4blWqlCPYnyLXWmCpQSCAv/76o0DOZ14DGj y1ZSdJu6vw51+UsO6Lj8g+EQcc1T2cveHJQLIjKjAAkMLiFkRb4owat04OMRV9re2k WUc+LTzmm8/2QfnQVUCcl0QHsP9yj1xDCPHqplbY= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:39 +0200 Message-Id: <20180629132954.24269-6-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 05/20] intc/arm_gic: Add the virtualization extensions to the GIC state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 3 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the necessary parts of the virtualization extensions state to the GIC state. We choose to increase the size of the CPU interfaces state to add space for the vCPU interfaces (the GIC_NCPU_VCPU macro). This way, we'll be able to reuse most of the CPU interface code for the vCPUs. The only exception is the APR value, which is stored in h_apr in the virtual interface state for vCPUs. This is due to some complications with the GIC VMState, for which we don't want to break backward compatibility. APRs being stored in 2D arrays, increasing the second dimension would lead to some ugly VMState description. To avoid that, we keep it in h_apr for vCPUs. The vCPUs are numbered from GIC_NCPU to (GIC_NCPU * 2) - 1. The `gic_is_vcpu` function help to determine if a given CPU id correspond to a physical CPU or a virtual one. For the in-kernel KVM VGIC, since the exposed VGIC does not implement the virtualization extensions, we report an error if the corresponding property is set to true. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 2 +- hw/intc/arm_gic_common.c | 148 ++++++++++++++++++++++++++----- hw/intc/arm_gic_kvm.c | 8 +- hw/intc/gic_internal.h | 5 ++ include/hw/intc/arm_gic_common.h | 43 +++++++-- 5 files changed, 173 insertions(+), 33 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 6bed3d3e0b..b2dd379bd2 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1465,7 +1465,7 @@ static void arm_gic_realize(DeviceState *dev, Error *= *errp) } =20 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ - gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); + gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, NULL); =20 /* Extra core-specific regions for the CPU interfaces. This is * necessary for "franken-GIC" implementations, for example on diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 295ee9cc5e..75352d439e 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -46,6 +46,13 @@ static int gic_post_load(void *opaque, int version_id) return 0; } =20 +static bool gic_virt_state_needed(void *opaque) +{ + GICState *s =3D (GICState *)opaque; + + return s->virt_extn; +} + static const VMStateDescription vmstate_gic_irq_state =3D { .name =3D "arm_gic_irq_state", .version_id =3D 1, @@ -62,6 +69,30 @@ static const VMStateDescription vmstate_gic_irq_state = =3D { } }; =20 +static const VMStateDescription vmstate_gic_virt_state =3D { + .name =3D "arm_gic_virt_state", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D gic_virt_state_needed, + .fields =3D (VMStateField[]) { + /* Virtual interface */ + VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU), + VMSTATE_UINT32_ARRAY(h_misr, GICState, GIC_NCPU), + VMSTATE_UINT32_2DARRAY(h_lr, GICState, GIC_MAX_LR, GIC_NCPU), + VMSTATE_UINT32_ARRAY(h_apr, GICState, GIC_NCPU), + + /* Virtual CPU interfaces */ + VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, GIC_NCPU, GIC_NCPU), + VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, GIC_NCPU, GIC_NC= PU), + VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, GIC_NCPU, GIC= _NCPU), + VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, GIC_NCPU, GIC_= NCPU), + VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, GIC_NCPU, GIC_NCPU), + VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, GIC_NCPU, GIC_NCPU), + + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_gic =3D { .name =3D "arm_gic", .version_id =3D 12, @@ -70,26 +101,31 @@ static const VMStateDescription vmstate_gic =3D { .post_load =3D gic_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINT32(ctlr, GICState), - VMSTATE_UINT32_ARRAY(cpu_ctlr, GICState, GIC_NCPU), + VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, 0, GIC_NCPU), VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1, vmstate_gic_irq_state, gic_irq_state), VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ), VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU), VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL= ), VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU= ), - VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU), - VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU), - VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU), - VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU), - VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU), + VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, 0, GIC_NCPU), + VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, 0, GIC_NCPU), + VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, 0, GIC_NCPU), + VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, 0, GIC_NCPU), + VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, 0, GIC_NCPU), VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU), VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * []) { + &vmstate_gic_virt_state, + NULL } }; =20 void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler, - const MemoryRegionOps *ops) + const MemoryRegionOps *ops, + const MemoryRegionOps *virt_ops) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(s); int i =3D s->num_irq - GIC_INTERNAL; @@ -116,6 +152,11 @@ void gic_init_irqs_and_mmio(GICState *s, qemu_irq_hand= ler handler, for (i =3D 0; i < s->num_cpu; i++) { sysbus_init_irq(sbd, &s->parent_vfiq[i]); } + if (s->virt_extn) { + for (i =3D 0; i < s->num_cpu; i++) { + sysbus_init_irq(sbd, &s->maintenance_irq[i]); + } + } =20 /* Distributor */ memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000= ); @@ -127,6 +168,17 @@ void gic_init_irqs_and_mmio(GICState *s, qemu_irq_hand= ler handler, memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL, s, "gic_cpu", s->revision =3D=3D 2 ? 0x2000 : 0x= 100); sysbus_init_mmio(sbd, &s->cpuiomem[0]); + + if (s->virt_extn) { + memory_region_init_io(&s->vifaceiomem, OBJECT(s), virt_ops, + s, "gic_viface", 0x1000); + sysbus_init_mmio(sbd, &s->vifaceiomem); + + memory_region_init_io(&s->vcpuiomem[0], OBJECT(s), + virt_ops ? &virt_ops[1] : NULL, + s, "gic_vcpu", 0x2000); + sysbus_init_mmio(sbd, &s->vcpuiomem[0]); + } } =20 static void arm_gic_common_realize(DeviceState *dev, Error **errp) @@ -163,6 +215,48 @@ static void arm_gic_common_realize(DeviceState *dev, E= rror **errp) "the security extensions"); return; } + + if (s->virt_extn) { + if (s->revision !=3D 2) { + error_setg(errp, "GIC virtualization extensions are only " + "supported by revision 2"); + return; + } + + /* For now, set the number of implemented LRs to 4, as found in mo= st + * real GICv2. This could be promoted as a QOM property if we need= to + * emulate a variant with another num_lrs. + */ + s->num_lrs =3D 4; + } +} + +static inline void arm_gic_common_reset_irq_state(GICState *s, int first_c= pu, + int resetprio) +{ + int i, j; + + for (i =3D first_cpu; i < first_cpu + s->num_cpu; i++) { + if (s->revision =3D=3D REV_11MPCORE) { + s->priority_mask[i] =3D 0xf0; + } else { + s->priority_mask[i] =3D resetprio; + } + s->current_pending[i] =3D 1023; + s->running_priority[i] =3D 0x100; + s->cpu_ctlr[i] =3D 0; + s->bpr[i] =3D gic_is_vcpu(i) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR; + s->abpr[i] =3D gic_is_vcpu(i) ? GIC_VIRT_MIN_ABPR : GIC_MIN_ABPR; + + if (!gic_is_vcpu(i)) { + for (j =3D 0; j < GIC_INTERNAL; j++) { + s->priority1[j][i] =3D resetprio; + } + for (j =3D 0; j < GIC_NR_SGIS; j++) { + s->sgi_pending[j][i] =3D 0; + } + } + } } =20 static void arm_gic_common_reset(DeviceState *dev) @@ -185,24 +279,15 @@ static void arm_gic_common_reset(DeviceState *dev) } =20 memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); - for (i =3D 0 ; i < s->num_cpu; i++) { - if (s->revision =3D=3D REV_11MPCORE) { - s->priority_mask[i] =3D 0xf0; - } else { - s->priority_mask[i] =3D resetprio; - } - s->current_pending[i] =3D 1023; - s->running_priority[i] =3D 0x100; - s->cpu_ctlr[i] =3D 0; - s->bpr[i] =3D GIC_MIN_BPR; - s->abpr[i] =3D GIC_MIN_ABPR; - for (j =3D 0; j < GIC_INTERNAL; j++) { - s->priority1[j][i] =3D resetprio; - } - for (j =3D 0; j < GIC_NR_SGIS; j++) { - s->sgi_pending[j][i] =3D 0; - } + arm_gic_common_reset_irq_state(s, 0, resetprio); + + if (s->virt_extn) { + /* vCPU states are stored at indexes GIC_NCPU .. GIC_NCPU+num_cpu. + * The exposed vCPU interface does not have security extensions. + */ + arm_gic_common_reset_irq_state(s, GIC_NCPU, 0); } + for (i =3D 0; i < GIC_NR_SGIS; i++) { GIC_DIST_SET_ENABLED(i, ALL_CPU_MASK); GIC_DIST_SET_EDGE_TRIGGER(i); @@ -226,6 +311,19 @@ static void arm_gic_common_reset(DeviceState *dev) } } =20 + if (s->virt_extn) { + for (i =3D 0; i < s->num_lrs; i++) { + for (j =3D 0; j < s->num_cpu; j++) { + s->h_lr[i][j] =3D 0; + } + } + + for (i =3D 0; i < s->num_cpu; i++) { + s->h_hcr[i] =3D 0; + s->h_misr[i] =3D 0; + } + } + s->ctlr =3D 0; } =20 @@ -255,6 +353,8 @@ static Property arm_gic_common_properties[] =3D { DEFINE_PROP_UINT32("revision", GICState, revision, 1), /* True if the GIC should implement the security extensions */ DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0= ), + /* True if the GIC should implement the virtualization extensions */ + DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn,= 0), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 4b611c8d6d..a611e8ee12 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -511,6 +511,12 @@ static void kvm_arm_gic_realize(DeviceState *dev, Erro= r **errp) return; } =20 + if (s->virt_extn) { + error_setg(errp, "the in-kernel VGIC does not implement the " + "virtualization extensions"); + return; + } + if (!kvm_arm_gic_can_save_restore(s)) { error_setg(&s->migration_blocker, "This operating system kernel do= es " "not support vGICv2 migration"); @@ -522,7 +528,7 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error= **errp) } } =20 - gic_init_irqs_and_mmio(s, kvm_arm_gicv2_set_irq, NULL); + gic_init_irqs_and_mmio(s, kvm_arm_gicv2_set_irq, NULL, NULL); =20 for (i =3D 0; i < s->num_irq - GIC_INTERNAL; i++) { qemu_irq irq =3D qdev_get_gpio_in(dev, i); diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index a2075a94db..c85427c8e3 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -94,4 +94,9 @@ static inline bool gic_test_pending(GICState *s, int irq,= int cm) } } =20 +static inline bool gic_is_vcpu(int cpu) +{ + return cpu >=3D GIC_NCPU; +} + #endif /* QEMU_ARM_GIC_INTERNAL_H */ diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_com= mon.h index af3ca18e2f..9aa1aa5188 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -30,6 +30,8 @@ #define GIC_NR_SGIS 16 /* Maximum number of possible CPU interfaces, determined by GIC architectu= re */ #define GIC_NCPU 8 +/* Maximum number of possible CPU interfaces with their respective vCPU */ +#define GIC_NCPU_VCPU (GIC_NCPU * 2) =20 #define MAX_NR_GROUP_PRIO 128 #define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32) @@ -37,6 +39,17 @@ #define GIC_MIN_BPR 0 #define GIC_MIN_ABPR (GIC_MIN_BPR + 1) =20 +/* Architectural maximum number of list registers in the virtual interface= */ +#define GIC_MAX_LR 64 + +/* Only 32 priority levels and 32 preemption levels in the vCPU interfaces= */ +#define GIC_VIRT_MAX_GROUP_PRIO_BITS 5 +#define GIC_VIRT_MAX_NR_GROUP_PRIO (1 << GIC_VIRT_MAX_GROUP_PRIO_BITS) +#define GIC_VIRT_NR_APRS (GIC_VIRT_MAX_NR_GROUP_PRIO / 32) + +#define GIC_VIRT_MIN_BPR 2 +#define GIC_VIRT_MIN_ABPR (GIC_VIRT_MIN_BPR + 1) + typedef struct gic_irq_state { /* The enable bits are only banked for per-cpu interrupts. */ uint8_t enabled; @@ -57,6 +70,8 @@ typedef struct GICState { qemu_irq parent_fiq[GIC_NCPU]; qemu_irq parent_virq[GIC_NCPU]; qemu_irq parent_vfiq[GIC_NCPU]; + qemu_irq maintenance_irq[GIC_NCPU]; + /* GICD_CTLR; for a GIC with the security extensions the NS banked ver= sion * of this register is just an alias of bit 1 of the S banked version. */ @@ -64,7 +79,7 @@ typedef struct GICState { /* GICC_CTLR; again, the NS banked version is just aliases of bits of * the S banked register, so our state only needs to store the S versi= on. */ - uint32_t cpu_ctlr[GIC_NCPU]; + uint32_t cpu_ctlr[GIC_NCPU_VCPU]; =20 gic_irq_state irq_state[GIC_MAXIRQ]; uint8_t irq_target[GIC_MAXIRQ]; @@ -78,9 +93,9 @@ typedef struct GICState { */ uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU]; =20 - uint16_t priority_mask[GIC_NCPU]; - uint16_t running_priority[GIC_NCPU]; - uint16_t current_pending[GIC_NCPU]; + uint16_t priority_mask[GIC_NCPU_VCPU]; + uint16_t running_priority[GIC_NCPU_VCPU]; + uint16_t current_pending[GIC_NCPU_VCPU]; =20 /* If we present the GICv2 without security extensions to a guest, * the guest can configure the GICC_CTLR to configure group 1 binary p= oint @@ -88,8 +103,8 @@ typedef struct GICState { * For a GIC with Security Extensions we use use bpr for the * secure copy and abpr as storage for the non-secure copy of the regi= ster. */ - uint8_t bpr[GIC_NCPU]; - uint8_t abpr[GIC_NCPU]; + uint8_t bpr[GIC_NCPU_VCPU]; + uint8_t abpr[GIC_NCPU_VCPU]; =20 /* The APR is implementation defined, so we choose a layout identical = to * the KVM ABI layout for QEMU's implementation of the gic: @@ -100,6 +115,15 @@ typedef struct GICState { uint32_t apr[GIC_NR_APRS][GIC_NCPU]; uint32_t nsapr[GIC_NR_APRS][GIC_NCPU]; =20 + /* Virtual interface control registers */ + uint32_t h_hcr[GIC_NCPU]; + uint32_t h_misr[GIC_NCPU]; + uint32_t h_lr[GIC_MAX_LR][GIC_NCPU]; + uint32_t h_apr[GIC_NCPU]; + + /* Number of LRs implemented in this GIC instance */ + uint32_t num_lrs; + uint32_t num_cpu; =20 MemoryRegion iomem; /* Distributor */ @@ -108,9 +132,13 @@ typedef struct GICState { */ struct GICState *backref[GIC_NCPU]; MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ + MemoryRegion vifaceiomem; /* Virtual interface */ + MemoryRegion vcpuiomem[GIC_NCPU + 1]; /* vCPU interface */ + uint32_t num_irq; uint32_t revision; bool security_extn; + bool virt_extn; bool irq_reset_nonsecure; /* configure IRQs as group 1 (NS) on reset? = */ int dev_fd; /* kvm device fd if backed by kvm vgic support */ Error *migration_blocker; @@ -134,6 +162,7 @@ typedef struct ARMGICCommonClass { } ARMGICCommonClass; =20 void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler, - const MemoryRegionOps *ops); + const MemoryRegionOps *ops, + const MemoryRegionOps *virt_ops); =20 #endif --=20 2.17.1