From nobody Tue Feb 10 06:43:19 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530279673168950.309368575948; Fri, 29 Jun 2018 06:41:13 -0700 (PDT) Received: from localhost ([::1]:42210 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYteA-00087s-SX for importer@patchew.org; Fri, 29 Jun 2018 09:41:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38225) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtUL-0007lo-8p for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:31:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYtUI-0007YL-8h for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:31:01 -0400 Received: from greensocs.com ([193.104.36.180]:58658) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtU4-0006v9-JD; Fri, 29 Jun 2018 09:30:44 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 054B4443496; Fri, 29 Jun 2018 15:30:44 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gkue42HIsZWZ; Fri, 29 Jun 2018 15:30:43 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id EA6D64434AB; Fri, 29 Jun 2018 15:30:42 +0200 (CEST) Received: from michell-laptop.hive.antfield.fr (LFbn-LYO-1-488-36.w2-7.abo.wanadoo.fr [2.7.77.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 702444434A8; Fri, 29 Jun 2018 15:30:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279044; bh=Hcm6iL2d/lKqBaMAJY5X4I3zo8s+b1ZDK/eC0Gwqqm4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=X74LQXq5cKH6n5ko6ejMCYxgEctVvYcv8lOFPsRXWBlCdcTI0KckdIQuDIqOWSZCY GONIliY58Gb4ZmO6R1MwbvRjONBAn2q6RqMz6wPIvIJeVnibjvTMnHGRUZ2cQh4PKo m2km4+gLOrGzWAPVUQeoxuQ9DaK6u8HlvumyG+zI= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=sQ6J4Ovi; dkim=pass (1024-bit key) header.d=greensocs.com header.b=sQ6J4Ovi DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279042; bh=Hcm6iL2d/lKqBaMAJY5X4I3zo8s+b1ZDK/eC0Gwqqm4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=sQ6J4OvioQ3L+ZtrgTtKhPx6/D8vDBwNv3l2u72F9wDrb0DjwFDmJnbQiUUoarFHM yEFYHJ5/BkjbbHhma84yXOa20naNQvmSPrCGMsDquIax6QitZf8Q8sTWpB1u4m7szp KlYqDXmAbq9E2Bq8T/qdgmthzUudpzbEdsa6ar34= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279042; bh=Hcm6iL2d/lKqBaMAJY5X4I3zo8s+b1ZDK/eC0Gwqqm4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=sQ6J4OvioQ3L+ZtrgTtKhPx6/D8vDBwNv3l2u72F9wDrb0DjwFDmJnbQiUUoarFHM yEFYHJ5/BkjbbHhma84yXOa20naNQvmSPrCGMsDquIax6QitZf8Q8sTWpB1u4m7szp KlYqDXmAbq9E2Bq8T/qdgmthzUudpzbEdsa6ar34= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:54 +0200 Message-Id: <20180629132954.24269-21-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 20/20] arm/virt: Add support for GICv2 virtualization extensions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for GICv2 virtualization extensions by mapping the necessary I/O regions and connecting the maintenance IRQ lines. Declare those additions in the device tree and in the ACPI tables. Signed-off-by: Luc Michel --- hw/arm/virt-acpi-build.c | 4 ++++ hw/arm/virt.c | 50 +++++++++++++++++++++++++++++++++------- include/hw/arm/virt.h | 3 +++ 3 files changed, 49 insertions(+), 8 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 6ea47e2588..3b74bf0372 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -659,6 +659,8 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) gicc->length =3D sizeof(*gicc); if (vms->gic_version =3D=3D 2) { gicc->base_address =3D cpu_to_le64(memmap[VIRT_GIC_CPU].base); + gicc->gich_base_address =3D cpu_to_le64(memmap[VIRT_GIC_HYP].b= ase); + gicc->gicv_base_address =3D cpu_to_le64(memmap[VIRT_GIC_VCPU].= base); } gicc->cpu_interface_number =3D cpu_to_le32(i); gicc->arm_mpidr =3D cpu_to_le64(armcpu->mp_affinity); @@ -670,6 +672,8 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } if (vms->virt && vms->gic_version =3D=3D 3) { gicc->vgic_interrupt =3D cpu_to_le32(PPI(ARCH_GICV3_MAINT_IRQ)= ); + } else if (vms->virt && vms->gic_version =3D=3D 2) { + gicc->vgic_interrupt =3D cpu_to_le32(PPI(ARCH_GICV2_MAINT_IRQ)= ); } } =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 742f68afca..e45b9de3be 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -131,6 +131,8 @@ static const MemMapEntry a15memmap[] =3D { [VIRT_GIC_DIST] =3D { 0x08000000, 0x00010000 }, [VIRT_GIC_CPU] =3D { 0x08010000, 0x00010000 }, [VIRT_GIC_V2M] =3D { 0x08020000, 0x00001000 }, + [VIRT_GIC_HYP] =3D { 0x08030000, 0x00001000 }, + [VIRT_GIC_VCPU] =3D { 0x08040000, 0x00001000 }, /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ [VIRT_GIC_ITS] =3D { 0x08080000, 0x00020000 }, /* This redistributor space allows up to 2*64kB*123 CPUs */ @@ -438,11 +440,26 @@ static void fdt_add_gic_node(VirtMachineState *vms) /* 'cortex-a15-gic' means 'GIC v2' */ qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", "arm,cortex-a15-gic"); - qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", - 2, vms->memmap[VIRT_GIC_DIST].base, - 2, vms->memmap[VIRT_GIC_DIST].size, - 2, vms->memmap[VIRT_GIC_CPU].base, - 2, vms->memmap[VIRT_GIC_CPU].size); + if (!vms->virt) { + qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", + 2, vms->memmap[VIRT_GIC_DIST].bas= e, + 2, vms->memmap[VIRT_GIC_DIST].siz= e, + 2, vms->memmap[VIRT_GIC_CPU].base, + 2, vms->memmap[VIRT_GIC_CPU].size= ); + } else { + qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", + 2, vms->memmap[VIRT_GIC_DIST].bas= e, + 2, vms->memmap[VIRT_GIC_DIST].siz= e, + 2, vms->memmap[VIRT_GIC_CPU].base, + 2, vms->memmap[VIRT_GIC_CPU].size, + 2, vms->memmap[VIRT_GIC_HYP].base, + 2, vms->memmap[VIRT_GIC_HYP].size, + 2, vms->memmap[VIRT_GIC_VCPU].bas= e, + 2, vms->memmap[VIRT_GIC_VCPU].siz= e); + qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts", + GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV2_MAINT_= IRQ, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + } } =20 qemu_fdt_setprop_cell(vms->fdt, "/intc", "phandle", vms->gic_phandle); @@ -563,6 +580,11 @@ static void create_gic(VirtMachineState *vms, qemu_irq= *pic) qdev_prop_set_uint32(gicdev, "redist-region-count[1]", MIN(smp_cpus - redist0_count, redist1_capacity)); } + } else { + if (!kvm_irqchip_in_kernel()) { + qdev_prop_set_bit(gicdev, "has-virtualization-extensions", + vms->virt); + } } qdev_init_nofail(gicdev); gicbusdev =3D SYS_BUS_DEVICE(gicdev); @@ -574,6 +596,10 @@ static void create_gic(VirtMachineState *vms, qemu_irq= *pic) } } else { sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); + if (vms->virt) { + sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); + sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); + } } =20 /* Wire the outputs from each CPU's generic timer and the GICv3 @@ -600,9 +626,17 @@ static void create_gic(VirtMachineState *vms, qemu_irq= *pic) ppibase + timer_irq[irq= ])); } =20 - qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",= 0, - qdev_get_gpio_in(gicdev, ppibase - + ARCH_GICV3_MAINT_IR= Q)); + if (type =3D=3D 3) { + qemu_irq irq =3D qdev_get_gpio_in(gicdev, + ppibase + ARCH_GICV3_MAINT_IRQ= ); + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", + 0, irq); + } else if (vms->virt) { + qemu_irq irq =3D qdev_get_gpio_in(gicdev, + ppibase + ARCH_GICV2_MAINT_IRQ= ); + sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); + } + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, qdev_get_gpio_in(gicdev, ppibase + VIRTUAL_PMU_IRQ)); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 9a870ccb6a..9e2f33f2d1 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -42,6 +42,7 @@ #define NUM_VIRTIO_TRANSPORTS 32 #define NUM_SMMU_IRQS 4 =20 +#define ARCH_GICV2_MAINT_IRQ 9 #define ARCH_GICV3_MAINT_IRQ 9 =20 #define ARCH_TIMER_VIRT_IRQ 11 @@ -60,6 +61,8 @@ enum { VIRT_GIC_DIST, VIRT_GIC_CPU, VIRT_GIC_V2M, + VIRT_GIC_HYP, + VIRT_GIC_VCPU, VIRT_GIC_ITS, VIRT_GIC_REDIST, VIRT_GIC_REDIST2, --=20 2.17.1