From nobody Tue Feb 10 11:14:49 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530279272358412.8454842715761; Fri, 29 Jun 2018 06:34:32 -0700 (PDT) Received: from localhost ([::1]:42170 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtXV-0001Gw-Hz for importer@patchew.org; Fri, 29 Jun 2018 09:34:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38115) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtUH-0007hd-CL for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:31:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYtUD-0007LC-Ih for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:30:57 -0400 Received: from greensocs.com ([193.104.36.180]:58614) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtU2-0006mO-RI; Fri, 29 Jun 2018 09:30:43 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 82210443496; Fri, 29 Jun 2018 15:30:42 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7RNe5SvmtaYu; Fri, 29 Jun 2018 15:30:41 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 905504434B8; Fri, 29 Jun 2018 15:30:41 +0200 (CEST) Received: from michell-laptop.hive.antfield.fr (LFbn-LYO-1-488-36.w2-7.abo.wanadoo.fr [2.7.77.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 1A26E4434BD; Fri, 29 Jun 2018 15:30:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279042; bh=Tcn8vA+NQ6UjfzqAXfFdIrJgo/nDdngNZUAvIGiaw7s=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=RjTMQhog3E7EN8vBhke1r2HSa3kU57ldblI3vhdwCUj7XpFIwrNHTQ76WYhORA+ty x0X0kq3j+2HMInVHIceE7P8xCLWSWcU/nj3izBAFkYpRMiTk3XcVMYn81sN7ud2MPH OkXEIKtbuWrXZvqxMjbG3M9xEd0JKyS0LnCFpSgg= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=4EDH6Ht3; dkim=pass (1024-bit key) header.d=greensocs.com header.b=4EDH6Ht3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279041; bh=Tcn8vA+NQ6UjfzqAXfFdIrJgo/nDdngNZUAvIGiaw7s=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=4EDH6Ht3BsXdO8vC2TiVt+BN6XLtFjec0gsJt6fJvZV4m2DJYNkqYRwy784cEU8Ci SDikZYr6my5GAdEdeTTz+VcoonmTkzsINiVnleF8DvwUv1bcaeCIKf8EnnAewVWQUA X0CEfrPW7VhmManBLtmiYGpD7K6XfagZqsW7MbQs= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279041; bh=Tcn8vA+NQ6UjfzqAXfFdIrJgo/nDdngNZUAvIGiaw7s=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=4EDH6Ht3BsXdO8vC2TiVt+BN6XLtFjec0gsJt6fJvZV4m2DJYNkqYRwy784cEU8Ci SDikZYr6my5GAdEdeTTz+VcoonmTkzsINiVnleF8DvwUv1bcaeCIKf8EnnAewVWQUA X0CEfrPW7VhmManBLtmiYGpD7K6XfagZqsW7MbQs= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:51 +0200 Message-Id: <20180629132954.24269-18-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 17/20] intc/arm_gic: Implement maintenance interrupt generation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement the maintenance interrupt generation that is part of the GICv2 virtualization extensions. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index a3ff4b89d1..10300e9b4c 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -206,6 +206,94 @@ static inline void gic_update_internal(GICState *s, bo= ol virt) } } =20 +static inline void gic_extract_lr_info(GICState *s, int cpu, + int *num_eoi, int *num_valid, int *num_pen= ding) +{ + int lr_idx; + + *num_eoi =3D 0; + *num_valid =3D 0; + *num_pending =3D 0; + + for (lr_idx =3D 0; lr_idx < s->num_lrs; lr_idx++) { + uint32_t *entry =3D &s->h_lr[lr_idx][cpu]; + + if (gic_lr_entry_is_eoi(*entry)) { + (*num_eoi)++; + } + + if (GICH_LR_STATE(*entry) !=3D GICH_LR_STATE_INVALID) { + (*num_valid)++; + } + + if (GICH_LR_STATE(*entry) =3D=3D GICH_LR_STATE_PENDING) { + (*num_pending)++; + } + } +} + +static void gic_compute_misr(GICState *s, int cpu) +{ + int val; + int vcpu =3D cpu + GIC_NCPU; + + int num_eoi, num_valid, num_pending; + + gic_extract_lr_info(s, cpu, &num_eoi, &num_valid, &num_pending); + + /* EOI */ + val =3D (num_eoi !=3D 0); + s->h_misr[cpu] =3D FIELD_DP32(0, GICH_MISR, EOI, val); + + /* U: true if only 0 or 1 LR entry is valid */ + val =3D s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK && + (num_valid < 2); + s->h_misr[cpu] =3D FIELD_DP32(s->h_misr[cpu], GICH_MISR, U, val); + + /* LRENP: EOICount is not 0 */ + val =3D s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK && + ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) !=3D 0); + s->h_misr[cpu] =3D FIELD_DP32(s->h_misr[cpu], GICH_MISR, LRENP, val); + + /* NP: no pending interrupts */ + val =3D s->h_hcr[cpu] & R_GICH_HCR_NPIE_MASK && + (num_pending =3D=3D 0); + s->h_misr[cpu] =3D FIELD_DP32(s->h_misr[cpu], GICH_MISR, NP, val); + + /* VGrp0E: group0 virq signaling enabled */ + val =3D s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK && + (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0); + s->h_misr[cpu] =3D FIELD_DP32(s->h_misr[cpu], GICH_MISR, VGrp0E, val); + + /* VGrp0D: group0 virq signaling disabled */ + val =3D s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK && + !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0); + s->h_misr[cpu] =3D FIELD_DP32(s->h_misr[cpu], GICH_MISR, VGrp0D, val); + + /* VGrp1E: group1 virq signaling enabled */ + val =3D s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK && + (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1); + s->h_misr[cpu] =3D FIELD_DP32(s->h_misr[cpu], GICH_MISR, VGrp1E, val); + + /* VGrp1D: group1 virq signaling disabled */ + val =3D s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK && + !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1); + s->h_misr[cpu] =3D FIELD_DP32(s->h_misr[cpu], GICH_MISR, VGrp1D, val); +} + +static void gic_update_maintenance(GICState *s) +{ + int cpu =3D 0; + int maint_level; + + for (cpu =3D 0; cpu < s->num_cpu; cpu++) { + gic_compute_misr(s, cpu); + maint_level =3D (s->h_hcr[cpu] & R_GICH_HCR_EN_MASK) && s->h_misr[= cpu]; + + qemu_set_irq(s->maintenance_irq[cpu], maint_level); + } +} + static void gic_update(GICState *s) { gic_update_internal(s, false); @@ -214,6 +302,7 @@ static void gic_update(GICState *s) static void gic_update_virt(GICState *s) { gic_update_internal(s, true); + gic_update_maintenance(s); } =20 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, --=20 2.17.1