From nobody Tue Feb 10 11:14:49 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530280219655100.82954740067669; Fri, 29 Jun 2018 06:50:19 -0700 (PDT) Received: from localhost ([::1]:42270 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtn0-0006KP-1t for importer@patchew.org; Fri, 29 Jun 2018 09:50:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38185) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtUJ-0007jh-QK for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:31:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYtUG-0007Su-Aw for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:30:59 -0400 Received: from greensocs.com ([193.104.36.180]:58633) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtU3-0006pe-28; Fri, 29 Jun 2018 09:30:43 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 1B7FB4434B9; Fri, 29 Jun 2018 15:30:41 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dFzOXjb6y8b0; Fri, 29 Jun 2018 15:30:39 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id BEB9A4434BB; Fri, 29 Jun 2018 15:30:39 +0200 (CEST) Received: from michell-laptop.hive.antfield.fr (LFbn-LYO-1-488-36.w2-7.abo.wanadoo.fr [2.7.77.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 35AB04434B5; Fri, 29 Jun 2018 15:30:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279041; bh=2fqRjrhfWPHXK4V2w3JDrR9pnrx5hmv8Gk3+ejSLdqM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=tWmI//A8JVvSrp3Tt+NlAap70OvU7ITNHhP+JtjO71Ythb5pZAJmw4qIZuHkkWRj8 jsaY0n8wbU1HTGE0NOjG2wS+eOQ27smjKB22MrjYTOKgC7IG7QGyYB/LOtE+6T1+mq 6ictB8kE6EX9snlHnUu1UMf0KSNtkM+gzExQFcmQ= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=3ucvNkp0; dkim=pass (1024-bit key) header.d=greensocs.com header.b=3ucvNkp0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279039; bh=2fqRjrhfWPHXK4V2w3JDrR9pnrx5hmv8Gk3+ejSLdqM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=3ucvNkp0Za+iCc673B9NBTbvg39SFMs5dueGSUmmlXdh0EAj94aZrKJvqJWmWy66D ZgSnlPrOL5F04ylLZG5zN10pdRlHWGeGXoN10grDhrGnYjjXBzXbVa1B8XxgQFnPvF VSXjL3WuMiDnClew1PpJWK8zkOOT2CRR9bHPM9cI= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279039; bh=2fqRjrhfWPHXK4V2w3JDrR9pnrx5hmv8Gk3+ejSLdqM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=3ucvNkp0Za+iCc673B9NBTbvg39SFMs5dueGSUmmlXdh0EAj94aZrKJvqJWmWy66D ZgSnlPrOL5F04ylLZG5zN10pdRlHWGeGXoN10grDhrGnYjjXBzXbVa1B8XxgQFnPvF VSXjL3WuMiDnClew1PpJWK8zkOOT2CRR9bHPM9cI= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:49 +0200 Message-Id: <20180629132954.24269-16-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 15/20] intc/arm_gic: Implement the virtual interface registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement the read and write functions for the virtual interface of the virtualization extensions in the GICv2. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 161 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 159 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 9bbd544a5c..a29042f291 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1530,6 +1530,163 @@ static MemTxResult gic_do_vcpu_write(void *opaque, = hwaddr addr, =20 } =20 +static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start) +{ + int lr_idx; + uint32_t ret =3D 0; + + for (lr_idx =3D lr_start; lr_idx < s->num_lrs; lr_idx++) { + uint32_t *entry =3D &s->h_lr[lr_idx][cpu]; + ret =3D deposit32(ret, lr_idx - lr_start, 1, + gic_lr_entry_is_eoi(*entry)); + } + + return ret; +} + +static uint32_t gic_compute_elrsr(GICState *s, int cpu, int lr_start) +{ + int lr_idx; + uint32_t ret =3D 0; + + for (lr_idx =3D lr_start; lr_idx < s->num_lrs; lr_idx++) { + uint32_t *entry =3D &s->h_lr[lr_idx][cpu]; + ret =3D deposit32(ret, lr_idx - lr_start, 1, + gic_lr_entry_is_free(*entry)); + } + + return ret; +} + +static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs) +{ + int vcpu =3D gic_get_current_vcpu(s); + uint32_t ctlr; + uint32_t abpr; + uint32_t bpr; + uint32_t prio_mask; + + ctlr =3D FIELD_EX32(value, GICH_VMCR, VMCCtlr); + abpr =3D FIELD_EX32(value, GICH_VMCR, VMABP); + bpr =3D FIELD_EX32(value, GICH_VMCR, VMBP); + prio_mask =3D FIELD_EX32(value, GICH_VMCR, VMPriMask) << 3; + + gic_set_cpu_control(s, vcpu, ctlr, attrs); + s->abpr[vcpu] =3D MAX(abpr, GIC_VIRT_MIN_ABPR); + s->bpr[vcpu] =3D MAX(bpr, GIC_VIRT_MIN_BPR); + gic_set_priority_mask(s, vcpu, prio_mask, attrs); +} + +static MemTxResult gic_hyp_read(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) +{ + GICState *s =3D ARM_GIC(opaque); + int cpu =3D gic_get_current_cpu(s); + int vcpu =3D gic_get_current_vcpu(s); + + switch (addr) { + case A_GICH_HCR: /* Hypervisor Control */ + *data =3D s->h_hcr[cpu]; + break; + + case A_GICH_VTR: /* VGIC Type */ + *data =3D FIELD_DP32(0, GICH_VTR, ListRegs, s->num_lrs - 1); + *data =3D FIELD_DP32(*data, GICH_VTR, PREbits, + GIC_VIRT_MAX_GROUP_PRIO_BITS - 1); + *data =3D FIELD_DP32(*data, GICH_VTR, PRIbits, + (7 - GIC_VIRT_MIN_BPR) - 1); + break; + + case A_GICH_VMCR: /* Virtual Machine Control */ + *data =3D FIELD_DP32(0, GICH_VMCR, VMCCtlr, + extract32(s->cpu_ctlr[vcpu], 0, 10)); + *data =3D FIELD_DP32(*data, GICH_VMCR, VMABP, s->abpr[vcpu]); + *data =3D FIELD_DP32(*data, GICH_VMCR, VMBP, s->bpr[vcpu]); + *data =3D FIELD_DP32(*data, GICH_VMCR, VMPriMask, + extract32(s->priority_mask[vcpu], 3, 5)); + break; + + case A_GICH_MISR: /* Maintenance Interrupt Status */ + *data =3D s->h_misr[cpu]; + break; + + case A_GICH_EISR0: /* End of Interrupt Status 0 and 1 */ + case A_GICH_EISR1: + *data =3D gic_compute_eisr(s, cpu, (addr - A_GICH_EISR0) * 8); + break; + + case A_GICH_ELRSR0: /* Empty List Status 0 and 1 */ + case A_GICH_ELRSR1: + *data =3D gic_compute_elrsr(s, cpu, (addr - A_GICH_ELRSR0) * 8); + break; + + case A_GICH_APR: /* Active Priorities */ + *data =3D s->h_apr[cpu]; + break; + + case A_GICH_LR0 ... A_GICH_LR63: /* List Registers */ + { + int lr_idx =3D (addr - A_GICH_LR0) / 4; + + if (lr_idx > s->num_lrs) { + *data =3D 0; + } else { + *data =3D s->h_lr[lr_idx][cpu]; + } + break; + } + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "gic_hyp_read: Bad offset %" HWADDR_PRIx "\n", addr); + return MEMTX_OK; + } + + return MEMTX_OK; +} + +static MemTxResult gic_hyp_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size, MemTxAttrs attrs) +{ + GICState *s =3D ARM_GIC(opaque); + int cpu =3D gic_get_current_cpu(s); + int vcpu =3D gic_get_current_vcpu(s); + + switch (addr) { + case A_GICH_HCR: /* Hypervisor Control */ + s->h_hcr[cpu] =3D value & GICH_HCR_MASK; + break; + + case A_GICH_VMCR: /* Virtual Machine Control */ + gic_vmcr_write(s, value, attrs); + break; + + case A_GICH_APR: /* Active Priorities */ + s->h_apr[cpu] =3D value; + s->running_priority[vcpu] =3D gic_get_prio_from_apr_bits(s, vcpu); + break; + + case A_GICH_LR0 ... A_GICH_LR63: /* List Registers */ + { + int lr_idx =3D (addr - A_GICH_LR0) / 4; + + if (lr_idx > s->num_lrs) { + return MEMTX_OK; + } + + s->h_lr[lr_idx][cpu] =3D value & GICH_LR_MASK; + break; + } + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "gic_hyp_write: Bad offset %" HWADDR_PRIx "\n", addr= ); + return MEMTX_OK; + } + + return MEMTX_OK; +} + static const MemoryRegionOps gic_ops[2] =3D { { .read_with_attrs =3D gic_dist_read, @@ -1551,8 +1708,8 @@ static const MemoryRegionOps gic_cpu_ops =3D { =20 static const MemoryRegionOps gic_virt_ops[2] =3D { { - .read_with_attrs =3D NULL, - .write_with_attrs =3D NULL, + .read_with_attrs =3D gic_hyp_read, + .write_with_attrs =3D gic_hyp_write, .endianness =3D DEVICE_NATIVE_ENDIAN, }, { --=20 2.17.1