From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15302793212304.560926784915523; Fri, 29 Jun 2018 06:35:21 -0700 (PDT) Received: from localhost ([::1]:42174 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtYW-0002JS-EL for importer@patchew.org; Fri, 29 Jun 2018 09:35:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38088) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtUG-0007gf-2d for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:30:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYtUA-0007CO-Fs for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:30:56 -0400 Received: from greensocs.com ([193.104.36.180]:58558) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtU1-0006ZS-I7; Fri, 29 Jun 2018 09:30:41 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 00E32443496; Fri, 29 Jun 2018 15:30:31 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id alurRsX1RDHy; Fri, 29 Jun 2018 15:30:31 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 0C3584434A8; Fri, 29 Jun 2018 15:30:30 +0200 (CEST) Received: from michell-laptop.hive.antfield.fr (LFbn-LYO-1-488-36.w2-7.abo.wanadoo.fr [2.7.77.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 87CA1443496; Fri, 29 Jun 2018 15:30:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279032; bh=gkFgsq3m5Nx9eJGMBEBFQpu3WOu84eY5r+uz8s7ufGI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=BeJFg3IQWYFAkCAOq47bWcDjMaOz+inMkXwa/4fpZDMPV7qnZYDE9War7/27hD1pR qmORJPTds4XNEerttIiFJsO7d9KGqCdvRpTlJMZf1z9LdpVNPsDzzIkK0ZFdTa2UAh QOaBW5DmBoSNj7vwbuqYhhHGpHMHmI+4I09ajg3c= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=vEuTvO/j; dkim=pass (1024-bit key) header.d=greensocs.com header.b=zPDar/Ek DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279031; bh=gkFgsq3m5Nx9eJGMBEBFQpu3WOu84eY5r+uz8s7ufGI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=vEuTvO/jUBYB9ZBBG5v8A6OMMsLaaIUCE7GKz21KK1NXB0oMGp1Jj17tfzCeeccZ+ 9bIUi2ckDBEYg2/qxCsxrlBSnN8NCct+6h8NYRg/gDFIh/tsLmpEzd8n2NTaxB96yS cC6DsoYNaM4HKCE23Ol2lmNq4qQrSrk+vVLVFMEo= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279030; bh=gkFgsq3m5Nx9eJGMBEBFQpu3WOu84eY5r+uz8s7ufGI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=zPDar/EkRtr8EptT1wu8VLxdfKylAuSZ4PdYv7YcU1fmOHh2vFWfvQhrrnS+WFTjq ucPjWRHOMIuf/iCI7dEBvVAB9Cy+uHCD3F6FAOMCiBx+XcCoUBRl6GbTC0gSpqqd6W f4zH2F/A/ZImNoV7AUOiqc7c34E6iVMPKsAm4jBk= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:35 +0200 Message-Id: <20180629132954.24269-2-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 01/20] intc/arm_gic: Implement write to GICD_ISACTIVERn and GICD_ICACTIVERn registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 3 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement write access to GICD_ISACTIVERn and GICD_ICACTIVERn registers in the GICv2. Those registers allow to set or clear the active state of an IRQ in the distributor. Signed-off-by: Luc Michel --- hw/intc/arm_gic.c | 41 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index ea0323f969..5755a4fb2c 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -982,9 +982,46 @@ static void gic_dist_writeb(void *opaque, hwaddr offse= t, GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); } } + } else if (offset < 0x380) { + /* Interrupt Set Active. */ + irq =3D (offset - 0x300) * 8 + GIC_BASE_IRQ; + if (irq >=3D s->num_irq) { + goto bad_reg; + } + + /* This register is banked per-cpu for PPIs */ + int cm =3D irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; + + for (i =3D 0; i < 8; i++) { + if (s->security_extn && !attrs.secure && + !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { + continue; /* Ignore Non-secure access of Group0 IRQ */ + } + + if (value & (1 << i)) { + GIC_DIST_SET_ACTIVE(irq + i, cm); + } + } } else if (offset < 0x400) { - /* Interrupt Active. */ - goto bad_reg; + /* Interrupt Clear Active. */ + irq =3D (offset - 0x380) * 8 + GIC_BASE_IRQ; + if (irq >=3D s->num_irq) { + goto bad_reg; + } + + /* This register is banked per-cpu for PPIs */ + int cm =3D irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; + + for (i =3D 0; i < 8; i++) { + if (s->security_extn && !attrs.secure && + !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { + continue; /* Ignore Non-secure access of Group0 IRQ */ + } + + if (value & (1 << i)) { + GIC_DIST_CLEAR_ACTIVE(irq + i, cm); + } + } } else if (offset < 0x800) { /* Interrupt Priority. */ irq =3D (offset - 0x400) + GIC_BASE_IRQ; --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530279707368443.1610727283345; Fri, 29 Jun 2018 06:41:47 -0700 (PDT) Received: from localhost ([::1]:42213 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYteg-00009e-1u for importer@patchew.org; Fri, 29 Jun 2018 09:41:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38251) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtUN-0007qg-Mf for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:31:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYtUJ-0007aa-68 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:31:03 -0400 Received: from greensocs.com ([193.104.36.180]:58555) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtU1-0006ZZ-I1; Fri, 29 Jun 2018 09:30:42 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 3786B4434A7; Fri, 29 Jun 2018 15:30:33 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id oFSvgwONmDhZ; Fri, 29 Jun 2018 15:30:31 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 67BE34434AB; Fri, 29 Jun 2018 15:30:31 +0200 (CEST) Received: from michell-laptop.hive.antfield.fr (LFbn-LYO-1-488-36.w2-7.abo.wanadoo.fr [2.7.77.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id F0D1B443495; Fri, 29 Jun 2018 15:30:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279033; bh=DY+akSE0S6bW+nQxKHwo+oVeWP4b7A8n/Dc0pjdIUwI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=rRsphGjlpP9jy44JXUspKp+3Swt5Dm+UwuvFWI+agZdcbPERbGnKZxrvz5UEYPX6w Jch7jfvPrqhoDAyfp3+X9mAUiMv+JQ6E+P7fpCbiyZ8Y/YXvRg24fCO/PfKUTY3A6Z ssn7Nm5yR6H+EPNEpXAex8K8KkBEGOnhlWFOWMn8= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=eu/rZFXn; dkim=pass (1024-bit key) header.d=greensocs.com header.b=eu/rZFXn DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279031; bh=DY+akSE0S6bW+nQxKHwo+oVeWP4b7A8n/Dc0pjdIUwI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=eu/rZFXn/BDVKrn2wGSviAjGHA8T8wYjix7vsWrZ1oE4t0B4JWqCM3/9am74EIaJ5 sTm1L9HVgsBYxtcwQRkw/zRdnlJPeIrYMyN/xa2NekWCN0BuKTFcD/MxX+uO2hTv+g kmvaxSSArNUpHWAfdEISKZqXPOhkyFx2Or0UrjtE= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279031; bh=DY+akSE0S6bW+nQxKHwo+oVeWP4b7A8n/Dc0pjdIUwI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=eu/rZFXn/BDVKrn2wGSviAjGHA8T8wYjix7vsWrZ1oE4t0B4JWqCM3/9am74EIaJ5 sTm1L9HVgsBYxtcwQRkw/zRdnlJPeIrYMyN/xa2NekWCN0BuKTFcD/MxX+uO2hTv+g kmvaxSSArNUpHWAfdEISKZqXPOhkyFx2Or0UrjtE= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:36 +0200 Message-Id: <20180629132954.24269-3-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 02/20] intc/arm_gic: Refactor operations on the distributor X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In preparation for the virtualization extensions implementation, refactor the name of the functions and macros that act on the GIC distributor to make that fact explicit. It will be useful to differentiate them from the ones that will act on the virtual interfaces. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Sai Pavan Boddu Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 163 +++++++++++++++++++++------------------ hw/intc/arm_gic_common.c | 6 +- hw/intc/arm_gic_kvm.c | 23 +++--- hw/intc/gic_internal.h | 51 ++++++------ 4 files changed, 127 insertions(+), 116 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 5755a4fb2c..3b299e37cc 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -92,11 +92,12 @@ void gic_update(GICState *s) best_prio =3D 0x100; best_irq =3D 1023; for (irq =3D 0; irq < s->num_irq; irq++) { - if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) = && - (!GIC_TEST_ACTIVE(irq, cm)) && - (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { - if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { - best_prio =3D GIC_GET_PRIORITY(irq, cpu); + if (GIC_DIST_TEST_ENABLED(irq, cm) && + gic_test_pending(s, irq, cm) && + (!GIC_DIST_TEST_ACTIVE(irq, cm)) && + (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) { + if (GIC_DIST_GET_PRIORITY(irq, cpu) < best_prio) { + best_prio =3D GIC_DIST_GET_PRIORITY(irq, cpu); best_irq =3D irq; } } @@ -112,7 +113,7 @@ void gic_update(GICState *s) if (best_prio < s->priority_mask[cpu]) { s->current_pending[cpu] =3D best_irq; if (best_prio < s->running_priority[cpu]) { - int group =3D GIC_TEST_GROUP(best_irq, cm); + int group =3D GIC_DIST_TEST_GROUP(best_irq, cm); =20 if (extract32(s->ctlr, group, 1) && extract32(s->cpu_ctlr[cpu], group, 1)) { @@ -145,7 +146,7 @@ void gic_set_pending_private(GICState *s, int cpu, int = irq) } =20 DPRINTF("Set %d pending cpu %d\n", irq, cpu); - GIC_SET_PENDING(irq, cm); + GIC_DIST_SET_PENDING(irq, cm); gic_update(s); } =20 @@ -153,13 +154,13 @@ static void gic_set_irq_11mpcore(GICState *s, int irq= , int level, int cm, int target) { if (level) { - GIC_SET_LEVEL(irq, cm); - if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { + GIC_DIST_SET_LEVEL(irq, cm); + if (GIC_DIST_TEST_EDGE_TRIGGER(irq) || GIC_DIST_TEST_ENABLED(irq, = cm)) { DPRINTF("Set %d pending mask %x\n", irq, target); - GIC_SET_PENDING(irq, target); + GIC_DIST_SET_PENDING(irq, target); } } else { - GIC_CLEAR_LEVEL(irq, cm); + GIC_DIST_CLEAR_LEVEL(irq, cm); } } =20 @@ -167,13 +168,13 @@ static void gic_set_irq_generic(GICState *s, int irq,= int level, int cm, int target) { if (level) { - GIC_SET_LEVEL(irq, cm); + GIC_DIST_SET_LEVEL(irq, cm); DPRINTF("Set %d pending mask %x\n", irq, target); - if (GIC_TEST_EDGE_TRIGGER(irq)) { - GIC_SET_PENDING(irq, target); + if (GIC_DIST_TEST_EDGE_TRIGGER(irq)) { + GIC_DIST_SET_PENDING(irq, target); } } else { - GIC_CLEAR_LEVEL(irq, cm); + GIC_DIST_CLEAR_LEVEL(irq, cm); } } =20 @@ -192,7 +193,7 @@ static void gic_set_irq(void *opaque, int irq, int leve= l) /* The first external input line is internal interrupt 32. */ cm =3D ALL_CPU_MASK; irq +=3D GIC_INTERNAL; - target =3D GIC_TARGET(irq); + target =3D GIC_DIST_TARGET(irq); } else { int cpu; irq -=3D (s->num_irq - GIC_INTERNAL); @@ -204,7 +205,7 @@ static void gic_set_irq(void *opaque, int irq, int leve= l) =20 assert(irq >=3D GIC_NR_SGIS); =20 - if (level =3D=3D GIC_TEST_LEVEL(irq, cm)) { + if (level =3D=3D GIC_DIST_TEST_LEVEL(irq, cm)) { return; } =20 @@ -224,7 +225,7 @@ static uint16_t gic_get_current_pending_irq(GICState *s= , int cpu, uint16_t pending_irq =3D s->current_pending[cpu]; =20 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { - int group =3D GIC_TEST_GROUP(pending_irq, (1 << cpu)); + int group =3D GIC_DIST_TEST_GROUP(pending_irq, (1 << cpu)); /* On a GIC without the security extensions, reading this register * behaves in the same way as a secure access to a GIC with them. */ @@ -255,7 +256,7 @@ static int gic_get_group_priority(GICState *s, int cpu,= int irq) =20 if (gic_has_groups(s) && !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && - GIC_TEST_GROUP(irq, (1 << cpu))) { + GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { bpr =3D s->abpr[cpu] - 1; assert(bpr >=3D 0); } else { @@ -268,7 +269,7 @@ static int gic_get_group_priority(GICState *s, int cpu,= int irq) */ mask =3D ~0U << ((bpr & 7) + 1); =20 - return GIC_GET_PRIORITY(irq, cpu) & mask; + return GIC_DIST_GET_PRIORITY(irq, cpu) & mask; } =20 static void gic_activate_irq(GICState *s, int cpu, int irq) @@ -281,14 +282,14 @@ static void gic_activate_irq(GICState *s, int cpu, in= t irq) int regno =3D preemption_level / 32; int bitno =3D preemption_level % 32; =20 - if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) { + if (gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { s->nsapr[regno][cpu] |=3D (1 << bitno); } else { s->apr[regno][cpu] |=3D (1 << bitno); } =20 s->running_priority[cpu] =3D prio; - GIC_SET_ACTIVE(irq, 1 << cpu); + GIC_DIST_SET_ACTIVE(irq, 1 << cpu); } =20 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) @@ -357,7 +358,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemT= xAttrs attrs) return irq; } =20 - if (GIC_GET_PRIORITY(irq, cpu) >=3D s->running_priority[cpu]) { + if (GIC_DIST_GET_PRIORITY(irq, cpu) >=3D s->running_priority[cpu]) { DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n",= irq); return 1023; } @@ -366,7 +367,8 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemT= xAttrs attrs) /* Clear pending flags for both level and edge triggered interrupt= s. * Level triggered IRQs will be reasserted once they become inacti= ve. */ - GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); + GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK + : cm); ret =3D irq; } else { if (irq < GIC_NR_SGIS) { @@ -378,7 +380,9 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemT= xAttrs attrs) src =3D ctz32(s->sgi_pending[irq][cpu]); s->sgi_pending[irq][cpu] &=3D ~(1 << src); if (s->sgi_pending[irq][cpu] =3D=3D 0) { - GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK = : cm); + GIC_DIST_CLEAR_PENDING(irq, + GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_= MASK + : cm); } ret =3D irq | ((src & 0x7) << 10); } else { @@ -386,7 +390,8 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemT= xAttrs attrs) * interrupts. (level triggered interrupts with an active line * remain pending, see gic_test_pending) */ - GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm= ); + GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU= _MASK + : cm); ret =3D irq; } } @@ -397,11 +402,11 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, Me= mTxAttrs attrs) return ret; } =20 -void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, +void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, MemTxAttrs attrs) { if (s->security_extn && !attrs.secure) { - if (!GIC_TEST_GROUP(irq, (1 << cpu))) { + if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { return; /* Ignore Non-secure access of Group0 IRQ */ } val =3D 0x80 | (val >> 1); /* Non-secure view */ @@ -414,13 +419,13 @@ void gic_set_priority(GICState *s, int cpu, int irq, = uint8_t val, } } =20 -static uint32_t gic_get_priority(GICState *s, int cpu, int irq, +static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq, MemTxAttrs attrs) { - uint32_t prio =3D GIC_GET_PRIORITY(irq, cpu); + uint32_t prio =3D GIC_DIST_GET_PRIORITY(irq, cpu); =20 if (s->security_extn && !attrs.secure) { - if (!GIC_TEST_GROUP(irq, (1 << cpu))) { + if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { return 0; /* Non-secure access cannot read priority of Group0 = IRQ */ } prio =3D (prio << 1) & 0xff; /* Non-secure view */ @@ -543,7 +548,7 @@ static bool gic_eoi_split(GICState *s, int cpu, MemTxAt= trs attrs) static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs a= ttrs) { int cm =3D 1 << cpu; - int group =3D gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); + int group =3D gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm); =20 if (!gic_eoi_split(s, cpu, attrs)) { /* This is UNPREDICTABLE; we choose to ignore it */ @@ -557,7 +562,7 @@ static void gic_deactivate_irq(GICState *s, int cpu, in= t irq, MemTxAttrs attrs) return; } =20 - GIC_CLEAR_ACTIVE(irq, cm); + GIC_DIST_CLEAR_ACTIVE(irq, cm); } =20 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) @@ -584,14 +589,15 @@ void gic_complete_irq(GICState *s, int cpu, int irq, = MemTxAttrs attrs) if (s->revision =3D=3D REV_11MPCORE) { /* Mark level triggered interrupts as pending if they are still raised. */ - if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) - && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) !=3D 0) { + if (!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_ENABLED(irq,= cm) + && GIC_DIST_TEST_LEVEL(irq, cm) + && (GIC_DIST_TARGET(irq) & cm) !=3D 0) { DPRINTF("Set %d pending mask %x\n", irq, cm); - GIC_SET_PENDING(irq, cm); + GIC_DIST_SET_PENDING(irq, cm); } } =20 - group =3D gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); + group =3D gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm); =20 if (s->security_extn && !attrs.secure && !group) { DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); @@ -607,7 +613,7 @@ void gic_complete_irq(GICState *s, int cpu, int irq, Me= mTxAttrs attrs) =20 /* In GICv2 the guest can choose to split priority-drop and deactivate= */ if (!gic_eoi_split(s, cpu, attrs)) { - GIC_CLEAR_ACTIVE(irq, cm); + GIC_DIST_CLEAR_ACTIVE(irq, cm); } gic_update(s); } @@ -655,7 +661,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr off= set, MemTxAttrs attrs) goto bad_reg; } for (i =3D 0; i < 8; i++) { - if (GIC_TEST_GROUP(irq + i, cm)) { + if (GIC_DIST_TEST_GROUP(irq + i, cm)) { res |=3D (1 << i); } } @@ -675,11 +681,11 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr o= ffset, MemTxAttrs attrs) res =3D 0; for (i =3D 0; i < 8; i++) { if (s->security_extn && !attrs.secure && - !GIC_TEST_GROUP(irq + i, 1 << cpu)) { + !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { continue; /* Ignore Non-secure access of Group0 IRQ */ } =20 - if (GIC_TEST_ENABLED(irq + i, cm)) { + if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { res |=3D (1 << i); } } @@ -696,7 +702,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr off= set, MemTxAttrs attrs) mask =3D (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; for (i =3D 0; i < 8; i++) { if (s->security_extn && !attrs.secure && - !GIC_TEST_GROUP(irq + i, 1 << cpu)) { + !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { continue; /* Ignore Non-secure access of Group0 IRQ */ } =20 @@ -713,11 +719,11 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr o= ffset, MemTxAttrs attrs) mask =3D (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; for (i =3D 0; i < 8; i++) { if (s->security_extn && !attrs.secure && - !GIC_TEST_GROUP(irq + i, 1 << cpu)) { + !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { continue; /* Ignore Non-secure access of Group0 IRQ */ } =20 - if (GIC_TEST_ACTIVE(irq + i, mask)) { + if (GIC_DIST_TEST_ACTIVE(irq + i, mask)) { res |=3D (1 << i); } } @@ -726,7 +732,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr off= set, MemTxAttrs attrs) irq =3D (offset - 0x400) + GIC_BASE_IRQ; if (irq >=3D s->num_irq) goto bad_reg; - res =3D gic_get_priority(s, cpu, irq, attrs); + res =3D gic_dist_get_priority(s, cpu, irq, attrs); } else if (offset < 0xc00) { /* Interrupt CPU Target. */ if (s->num_cpu =3D=3D 1 && s->revision !=3D REV_11MPCORE) { @@ -740,7 +746,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr off= set, MemTxAttrs attrs) if (irq >=3D 29 && irq <=3D 31) { res =3D cm; } else { - res =3D GIC_TARGET(irq); + res =3D GIC_DIST_TARGET(irq); } } } else if (offset < 0xf00) { @@ -751,14 +757,16 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr o= ffset, MemTxAttrs attrs) res =3D 0; for (i =3D 0; i < 4; i++) { if (s->security_extn && !attrs.secure && - !GIC_TEST_GROUP(irq + i, 1 << cpu)) { + !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { continue; /* Ignore Non-secure access of Group0 IRQ */ } =20 - if (GIC_TEST_MODEL(irq + i)) + if (GIC_DIST_TEST_MODEL(irq + i)) { res |=3D (1 << (i * 2)); - if (GIC_TEST_EDGE_TRIGGER(irq + i)) + } + if (GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { res |=3D (2 << (i * 2)); + } } } else if (offset < 0xf10) { goto bad_reg; @@ -776,7 +784,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr off= set, MemTxAttrs attrs) } =20 if (s->security_extn && !attrs.secure && - !GIC_TEST_GROUP(irq, 1 << cpu)) { + !GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { res =3D 0; /* Ignore Non-secure access of Group0 IRQ */ } else { res =3D s->sgi_pending[irq][cpu]; @@ -872,10 +880,10 @@ static void gic_dist_writeb(void *opaque, hwaddr offs= et, int cm =3D (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU= _MASK; if (value & (1 << i)) { /* Group1 (Non-secure) */ - GIC_SET_GROUP(irq + i, cm); + GIC_DIST_SET_GROUP(irq + i, cm); } else { /* Group0 (Secure) */ - GIC_CLEAR_GROUP(irq + i, cm); + GIC_DIST_CLEAR_GROUP(irq + i, cm); } } } @@ -894,25 +902,26 @@ static void gic_dist_writeb(void *opaque, hwaddr offs= et, for (i =3D 0; i < 8; i++) { if (value & (1 << i)) { int mask =3D - (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i= ); + (irq < GIC_INTERNAL) ? (1 << cpu) + : GIC_DIST_TARGET(irq + i); int cm =3D (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MAS= K; =20 if (s->security_extn && !attrs.secure && - !GIC_TEST_GROUP(irq + i, 1 << cpu)) { + !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { continue; /* Ignore Non-secure access of Group0 IRQ */ } =20 - if (!GIC_TEST_ENABLED(irq + i, cm)) { + if (!GIC_DIST_TEST_ENABLED(irq + i, cm)) { DPRINTF("Enabled IRQ %d\n", irq + i); trace_gic_enable_irq(irq + i); } - GIC_SET_ENABLED(irq + i, cm); + GIC_DIST_SET_ENABLED(irq + i, cm); /* If a raised level triggered IRQ enabled then mark is as pending. */ - if (GIC_TEST_LEVEL(irq + i, mask) - && !GIC_TEST_EDGE_TRIGGER(irq + i)) { + if (GIC_DIST_TEST_LEVEL(irq + i, mask) + && !GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { DPRINTF("Set %d pending mask %x\n", irq + i, mask); - GIC_SET_PENDING(irq + i, mask); + GIC_DIST_SET_PENDING(irq + i, mask); } } } @@ -930,15 +939,15 @@ static void gic_dist_writeb(void *opaque, hwaddr offs= et, int cm =3D (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MAS= K; =20 if (s->security_extn && !attrs.secure && - !GIC_TEST_GROUP(irq + i, 1 << cpu)) { + !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { continue; /* Ignore Non-secure access of Group0 IRQ */ } =20 - if (GIC_TEST_ENABLED(irq + i, cm)) { + if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { DPRINTF("Disabled IRQ %d\n", irq + i); trace_gic_disable_irq(irq + i); } - GIC_CLEAR_ENABLED(irq + i, cm); + GIC_DIST_CLEAR_ENABLED(irq + i, cm); } } } else if (offset < 0x280) { @@ -953,11 +962,11 @@ static void gic_dist_writeb(void *opaque, hwaddr offs= et, for (i =3D 0; i < 8; i++) { if (value & (1 << i)) { if (s->security_extn && !attrs.secure && - !GIC_TEST_GROUP(irq + i, 1 << cpu)) { + !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { continue; /* Ignore Non-secure access of Group0 IRQ */ } =20 - GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); + GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i)); } } } else if (offset < 0x300) { @@ -971,7 +980,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, =20 for (i =3D 0; i < 8; i++) { if (s->security_extn && !attrs.secure && - !GIC_TEST_GROUP(irq + i, 1 << cpu)) { + !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { continue; /* Ignore Non-secure access of Group0 IRQ */ } =20 @@ -979,7 +988,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, for per-CPU interrupts. It's unclear whether this is the corect behavior. */ if (value & (1 << i)) { - GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); + GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK); } } } else if (offset < 0x380) { @@ -1027,7 +1036,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offs= et, irq =3D (offset - 0x400) + GIC_BASE_IRQ; if (irq >=3D s->num_irq) goto bad_reg; - gic_set_priority(s, cpu, irq, value, attrs); + gic_dist_set_priority(s, cpu, irq, value, attrs); } else if (offset < 0xc00) { /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the * annoying exception of the 11MPCore's GIC. @@ -1053,21 +1062,21 @@ static void gic_dist_writeb(void *opaque, hwaddr of= fset, value |=3D 0xaa; for (i =3D 0; i < 4; i++) { if (s->security_extn && !attrs.secure && - !GIC_TEST_GROUP(irq + i, 1 << cpu)) { + !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { continue; /* Ignore Non-secure access of Group0 IRQ */ } =20 if (s->revision =3D=3D REV_11MPCORE) { if (value & (1 << (i * 2))) { - GIC_SET_MODEL(irq + i); + GIC_DIST_SET_MODEL(irq + i); } else { - GIC_CLEAR_MODEL(irq + i); + GIC_DIST_CLEAR_MODEL(irq + i); } } if (value & (2 << (i * 2))) { - GIC_SET_EDGE_TRIGGER(irq + i); + GIC_DIST_SET_EDGE_TRIGGER(irq + i); } else { - GIC_CLEAR_EDGE_TRIGGER(irq + i); + GIC_DIST_CLEAR_EDGE_TRIGGER(irq + i); } } } else if (offset < 0xf10) { @@ -1081,10 +1090,10 @@ static void gic_dist_writeb(void *opaque, hwaddr of= fset, irq =3D (offset - 0xf10); =20 if (!s->security_extn || attrs.secure || - GIC_TEST_GROUP(irq, 1 << cpu)) { + GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { s->sgi_pending[irq][cpu] &=3D ~value; if (s->sgi_pending[irq][cpu] =3D=3D 0) { - GIC_CLEAR_PENDING(irq, 1 << cpu); + GIC_DIST_CLEAR_PENDING(irq, 1 << cpu); } } } else if (offset < 0xf30) { @@ -1095,8 +1104,8 @@ static void gic_dist_writeb(void *opaque, hwaddr offs= et, irq =3D (offset - 0xf20); =20 if (!s->security_extn || attrs.secure || - GIC_TEST_GROUP(irq, 1 << cpu)) { - GIC_SET_PENDING(irq, 1 << cpu); + GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { + GIC_DIST_SET_PENDING(irq, 1 << cpu); s->sgi_pending[irq][cpu] |=3D value; } } else { @@ -1143,7 +1152,7 @@ static void gic_dist_writel(void *opaque, hwaddr offs= et, mask =3D ALL_CPU_MASK; break; } - GIC_SET_PENDING(irq, mask); + GIC_DIST_SET_PENDING(irq, mask); target_cpu =3D ctz32(mask); while (target_cpu < GIC_NCPU) { s->sgi_pending[irq][target_cpu] |=3D (1 << cpu); diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index aee50a20e0..295ee9cc5e 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -204,8 +204,8 @@ static void arm_gic_common_reset(DeviceState *dev) } } for (i =3D 0; i < GIC_NR_SGIS; i++) { - GIC_SET_ENABLED(i, ALL_CPU_MASK); - GIC_SET_EDGE_TRIGGER(i); + GIC_DIST_SET_ENABLED(i, ALL_CPU_MASK); + GIC_DIST_SET_EDGE_TRIGGER(i); } =20 for (i =3D 0; i < ARRAY_SIZE(s->priority2); i++) { @@ -222,7 +222,7 @@ static void arm_gic_common_reset(DeviceState *dev) } if (s->security_extn && s->irq_reset_nonsecure) { for (i =3D 0; i < GIC_MAXIRQ; i++) { - GIC_SET_GROUP(i, ALL_CPU_MASK); + GIC_DIST_SET_GROUP(i, ALL_CPU_MASK); } } =20 diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 86665080bd..4b611c8d6d 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -140,10 +140,10 @@ static void translate_group(GICState *s, int irq, int= cpu, int cm =3D (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; =20 if (to_kernel) { - *field =3D GIC_TEST_GROUP(irq, cm); + *field =3D GIC_DIST_TEST_GROUP(irq, cm); } else { if (*field & 1) { - GIC_SET_GROUP(irq, cm); + GIC_DIST_SET_GROUP(irq, cm); } } } @@ -154,10 +154,10 @@ static void translate_enabled(GICState *s, int irq, i= nt cpu, int cm =3D (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; =20 if (to_kernel) { - *field =3D GIC_TEST_ENABLED(irq, cm); + *field =3D GIC_DIST_TEST_ENABLED(irq, cm); } else { if (*field & 1) { - GIC_SET_ENABLED(irq, cm); + GIC_DIST_SET_ENABLED(irq, cm); } } } @@ -171,7 +171,7 @@ static void translate_pending(GICState *s, int irq, int= cpu, *field =3D gic_test_pending(s, irq, cm); } else { if (*field & 1) { - GIC_SET_PENDING(irq, cm); + GIC_DIST_SET_PENDING(irq, cm); /* TODO: Capture is level-line is held high in the kernel */ } } @@ -183,10 +183,10 @@ static void translate_active(GICState *s, int irq, in= t cpu, int cm =3D (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; =20 if (to_kernel) { - *field =3D GIC_TEST_ACTIVE(irq, cm); + *field =3D GIC_DIST_TEST_ACTIVE(irq, cm); } else { if (*field & 1) { - GIC_SET_ACTIVE(irq, cm); + GIC_DIST_SET_ACTIVE(irq, cm); } } } @@ -195,10 +195,10 @@ static void translate_trigger(GICState *s, int irq, i= nt cpu, uint32_t *field, bool to_kernel) { if (to_kernel) { - *field =3D (GIC_TEST_EDGE_TRIGGER(irq)) ? 0x2 : 0x0; + *field =3D (GIC_DIST_TEST_EDGE_TRIGGER(irq)) ? 0x2 : 0x0; } else { if (*field & 0x2) { - GIC_SET_EDGE_TRIGGER(irq); + GIC_DIST_SET_EDGE_TRIGGER(irq); } } } @@ -207,9 +207,10 @@ static void translate_priority(GICState *s, int irq, i= nt cpu, uint32_t *field, bool to_kernel) { if (to_kernel) { - *field =3D GIC_GET_PRIORITY(irq, cpu) & 0xff; + *field =3D GIC_DIST_GET_PRIORITY(irq, cpu) & 0xff; } else { - gic_set_priority(s, cpu, irq, *field & 0xff, MEMTXATTRS_UNSPECIFIE= D); + gic_dist_set_priority(s, cpu, irq, + *field & 0xff, MEMTXATTRS_UNSPECIFIED); } } =20 diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 7fe87b13de..6f8d242904 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -27,30 +27,31 @@ =20 #define GIC_BASE_IRQ 0 =20 -#define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |=3D (cm) -#define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &=3D ~(cm) -#define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) !=3D= 0) -#define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |=3D (cm) -#define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &=3D ~(cm) -#define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |=3D (cm) -#define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &=3D ~(cm) -#define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) !=3D 0) -#define GIC_SET_MODEL(irq) s->irq_state[irq].model =3D true -#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model =3D false -#define GIC_TEST_MODEL(irq) s->irq_state[irq].model -#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level |=3D (cm) -#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &=3D ~(cm) -#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) !=3D 0) -#define GIC_SET_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger =3D true -#define GIC_CLEAR_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger =3D fal= se -#define GIC_TEST_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger) -#define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \ +#define GIC_DIST_SET_ENABLED(irq, cm) (s->irq_state[irq].enabled |=3D (cm)) +#define GIC_DIST_CLEAR_ENABLED(irq, cm) (s->irq_state[irq].enabled &=3D ~(= cm)) +#define GIC_DIST_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm))= !=3D 0) +#define GIC_DIST_SET_PENDING(irq, cm) (s->irq_state[irq].pending |=3D (cm)) +#define GIC_DIST_CLEAR_PENDING(irq, cm) (s->irq_state[irq].pending &=3D ~(= cm)) +#define GIC_DIST_SET_ACTIVE(irq, cm) (s->irq_state[irq].active |=3D (cm)) +#define GIC_DIST_CLEAR_ACTIVE(irq, cm) (s->irq_state[irq].active &=3D ~(cm= )) +#define GIC_DIST_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != =3D 0) +#define GIC_DIST_SET_MODEL(irq) (s->irq_state[irq].model =3D true) +#define GIC_DIST_CLEAR_MODEL(irq) (s->irq_state[irq].model =3D false) +#define GIC_DIST_TEST_MODEL(irq) (s->irq_state[irq].model) +#define GIC_DIST_SET_LEVEL(irq, cm) (s->irq_state[irq].level |=3D (cm)) +#define GIC_DIST_CLEAR_LEVEL(irq, cm) (s->irq_state[irq].level &=3D ~(cm)) +#define GIC_DIST_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != =3D 0) +#define GIC_DIST_SET_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger =3D= true) +#define GIC_DIST_CLEAR_EDGE_TRIGGER(irq) \ + (s->irq_state[irq].edge_trigger =3D false) +#define GIC_DIST_TEST_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger) +#define GIC_DIST_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? = \ s->priority1[irq][cpu] : \ s->priority2[(irq) - GIC_INTERNAL]) -#define GIC_TARGET(irq) s->irq_target[irq] -#define GIC_CLEAR_GROUP(irq, cm) (s->irq_state[irq].group &=3D ~(cm)) -#define GIC_SET_GROUP(irq, cm) (s->irq_state[irq].group |=3D (cm)) -#define GIC_TEST_GROUP(irq, cm) ((s->irq_state[irq].group & (cm)) !=3D 0) +#define GIC_DIST_TARGET(irq) (s->irq_target[irq]) +#define GIC_DIST_CLEAR_GROUP(irq, cm) (s->irq_state[irq].group &=3D ~(cm)) +#define GIC_DIST_SET_GROUP(irq, cm) (s->irq_state[irq].group |=3D (cm)) +#define GIC_DIST_TEST_GROUP(irq, cm) ((s->irq_state[irq].group & (cm)) != =3D 0) =20 #define GICD_CTLR_EN_GRP0 (1U << 0) #define GICD_CTLR_EN_GRP1 (1U << 1) @@ -79,8 +80,8 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxA= ttrs attrs); void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs); void gic_update(GICState *s); void gic_init_irqs_and_distributor(GICState *s); -void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, - MemTxAttrs attrs); +void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, + MemTxAttrs attrs); =20 static inline bool gic_test_pending(GICState *s, int irq, int cm) { @@ -93,7 +94,7 @@ static inline bool gic_test_pending(GICState *s, int irq,= int cm) * GICD_ISPENDR to set the state pending. */ return (s->irq_state[irq].pending & cm) || - (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_LEVEL(irq, cm)); + (!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_LEVEL(irq, = cm)); } } =20 --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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b=3ZVRxGjHCw68Ao3L73+mmGE/w1TIx92kBREqQCoE5rGF1Dd4UUKCDe8aCgrMbdMVr jSyLTVqfEscgfdPd+KsvjkqgARJYmi6ZDmyuADzlMp0hjBJ48/qHwfMe7KKIuoScOL kcdj4rug0nMRMUb6CqgTPn1ckJB+o1tq51zCZrMw= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=NIDCPo9b; dkim=pass (1024-bit key) header.d=greensocs.com header.b=NIDCPo9b DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279031; bh=TdGBrby7ZaADHouw741lqsKN651TGqhh73IC/wV93IQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=NIDCPo9bHh3mwDjjOMvPb8ycMCOynRdutHljj6YTkFj6JdhuGzCrJnb1Pya+GcKjZ +aWj2NQ+8JSFgsh4QsOQ996A79m4Pb1wic3fPTDe0nAmEjuEgU/Ap7e8bihlu+mkMN yAVuzMDwZ8xugPjsSi/H7p9dRBYBNCw5fcS55d6Y= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279031; bh=TdGBrby7ZaADHouw741lqsKN651TGqhh73IC/wV93IQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=NIDCPo9bHh3mwDjjOMvPb8ycMCOynRdutHljj6YTkFj6JdhuGzCrJnb1Pya+GcKjZ +aWj2NQ+8JSFgsh4QsOQ996A79m4Pb1wic3fPTDe0nAmEjuEgU/Ap7e8bihlu+mkMN yAVuzMDwZ8xugPjsSi/H7p9dRBYBNCw5fcS55d6Y= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:37 +0200 Message-Id: <20180629132954.24269-4-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 03/20] intc/arm_gic: Remove some dead code and put some functions static X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Some functions are now only used in arm_gic.c, put them static. Some of them where only used by the NVIC implementation and are not used anymore, so remove them. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 23 ++--------------------- hw/intc/gic_internal.h | 4 ---- 2 files changed, 2 insertions(+), 25 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 3b299e37cc..6bed3d3e0b 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -71,7 +71,7 @@ static inline bool gic_has_groups(GICState *s) =20 /* TODO: Many places that call this routine could be optimized. */ /* Update interrupt status after enabled or pending bits have been changed= . */ -void gic_update(GICState *s) +static void gic_update(GICState *s) { int best_irq; int best_prio; @@ -137,19 +137,6 @@ void gic_update(GICState *s) } } =20 -void gic_set_pending_private(GICState *s, int cpu, int irq) -{ - int cm =3D 1 << cpu; - - if (gic_test_pending(s, irq, cm)) { - return; - } - - DPRINTF("Set %d pending cpu %d\n", irq, cpu); - GIC_DIST_SET_PENDING(irq, cm); - gic_update(s); -} - static void gic_set_irq_11mpcore(GICState *s, int irq, int level, int cm, int target) { @@ -565,7 +552,7 @@ static void gic_deactivate_irq(GICState *s, int cpu, in= t irq, MemTxAttrs attrs) GIC_DIST_CLEAR_ACTIVE(irq, cm); } =20 -void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) +static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs att= rs) { int cm =3D 1 << cpu; int group; @@ -1456,12 +1443,6 @@ static const MemoryRegionOps gic_cpu_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -/* This function is used by nvic model */ -void gic_init_irqs_and_distributor(GICState *s) -{ - gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); -} - static void arm_gic_realize(DeviceState *dev, Error **errp) { /* Device instance realize function for the GIC sysbus device */ diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 6f8d242904..a2075a94db 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -75,11 +75,7 @@ /* The special cases for the revision property: */ #define REV_11MPCORE 0 =20 -void gic_set_pending_private(GICState *s, int cpu, int irq); uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs); -void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs); -void gic_update(GICState *s); -void gic_init_irqs_and_distributor(GICState *s); void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, MemTxAttrs attrs); =20 --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530279808656483.92780815027663; Fri, 29 Jun 2018 06:43:28 -0700 (PDT) Received: from localhost ([::1]:42224 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtgL-0001V5-Tv for importer@patchew.org; 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a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279032; bh=hy2xioeOgpWDvjVWNTqy9JfacgGmvViw5GG6aQwA0B0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=7SF37hjKAF7IXVvDtHUL+CAct+moPM+LSWquIAE/GM2sAfwAYvZdnGiKFOylb2mKH zjJ9elEdPMpTKIlqQ21MKumD+Joa46ted4X6tsVWn6WpZiWfU6UVIq8DMmIfdjsDue eUObLbdtngNUfR8MM2B/r5jaec33VtG66iuissX4= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:38 +0200 Message-Id: <20180629132954.24269-5-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 04/20] vmstate.h: Provide VMSTATE_UINT16_SUB_ARRAY X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Provide a VMSTATE_UINT16_SUB_ARRAY macro to save a uint16_t sub-array in a VMState. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- include/migration/vmstate.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index 42b946ce90..2b501d0466 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -923,6 +923,9 @@ extern const VMStateInfo vmstate_info_qtailq; #define VMSTATE_UINT16_ARRAY(_f, _s, _n) \ VMSTATE_UINT16_ARRAY_V(_f, _s, _n, 0) =20 +#define VMSTATE_UINT16_SUB_ARRAY(_f, _s, _start, _num) \ + VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_uint16, uint16= _t) + #define VMSTATE_UINT16_2DARRAY(_f, _s, _n1, _n2) \ VMSTATE_UINT16_2DARRAY_V(_f, _s, _n1, _n2, 0) =20 --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Fri, 29 Jun 2018 09:30:42 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id CED264434B2; Fri, 29 Jun 2018 15:30:34 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HbcaejfxgBQh; Fri, 29 Jun 2018 15:30:33 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 4BA684434B1; Fri, 29 Jun 2018 15:30:33 +0200 (CEST) Received: from michell-laptop.hive.antfield.fr (LFbn-LYO-1-488-36.w2-7.abo.wanadoo.fr [2.7.77.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 925DE4434A8; Fri, 29 Jun 2018 15:30:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279034; bh=B6zK56OBGB4g91rZGkZo0kAVasfVo6Uky406CxylDOE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=EWEnCt95vFqSMnVe+qpy4TEtMiqbcNnmn27OlGdqlbOgda+vfx6AIJvzNfWan9Vct rUlN4AjKEuK9Zuy88Y4cCJxE4LaF1V5qN7XJQ6qbBU5qyxZnQC/l4csfdfMqs+03+v OJvrprdCCGgEXdPiCWBBs8zTnLm2FPk1mZXd28uA= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=Dv+cZVXd; dkim=pass (1024-bit key) header.d=greensocs.com header.b=7CZ+UJF7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279033; bh=B6zK56OBGB4g91rZGkZo0kAVasfVo6Uky406CxylDOE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Dv+cZVXdmcT3Rg1JLI4fVGn+dRcwGZSwKdLxKLTGjM9MuoUHEyyMnAI+xvSPnwzyf xuG9R70klNHmx86HmrKv20aiqCAZScWWoaGgDisFiKpba+WeuAzp9q8fgosNCP7g7U 8Ba+UCTBYIPlKfMjuN4jWs7P7bdtAj+epiIlImkA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279032; bh=B6zK56OBGB4g91rZGkZo0kAVasfVo6Uky406CxylDOE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=7CZ+UJF796wt17uQc8W9C8mm8yZHGT4blWqlCPYnyLXWmCpQSCAv/76o0DOZ14DGj y1ZSdJu6vw51+UsO6Lj8g+EQcc1T2cveHJQLIjKjAAkMLiFkRb4owat04OMRV9re2k WUc+LTzmm8/2QfnQVUCcl0QHsP9yj1xDCPHqplbY= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:39 +0200 Message-Id: <20180629132954.24269-6-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 05/20] intc/arm_gic: Add the virtualization extensions to the GIC state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 3 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the necessary parts of the virtualization extensions state to the GIC state. We choose to increase the size of the CPU interfaces state to add space for the vCPU interfaces (the GIC_NCPU_VCPU macro). This way, we'll be able to reuse most of the CPU interface code for the vCPUs. The only exception is the APR value, which is stored in h_apr in the virtual interface state for vCPUs. This is due to some complications with the GIC VMState, for which we don't want to break backward compatibility. APRs being stored in 2D arrays, increasing the second dimension would lead to some ugly VMState description. To avoid that, we keep it in h_apr for vCPUs. The vCPUs are numbered from GIC_NCPU to (GIC_NCPU * 2) - 1. The `gic_is_vcpu` function help to determine if a given CPU id correspond to a physical CPU or a virtual one. For the in-kernel KVM VGIC, since the exposed VGIC does not implement the virtualization extensions, we report an error if the corresponding property is set to true. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 2 +- hw/intc/arm_gic_common.c | 148 ++++++++++++++++++++++++++----- hw/intc/arm_gic_kvm.c | 8 +- hw/intc/gic_internal.h | 5 ++ include/hw/intc/arm_gic_common.h | 43 +++++++-- 5 files changed, 173 insertions(+), 33 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 6bed3d3e0b..b2dd379bd2 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1465,7 +1465,7 @@ static void arm_gic_realize(DeviceState *dev, Error *= *errp) } =20 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ - gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); + gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, NULL); =20 /* Extra core-specific regions for the CPU interfaces. This is * necessary for "franken-GIC" implementations, for example on diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 295ee9cc5e..75352d439e 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -46,6 +46,13 @@ static int gic_post_load(void *opaque, int version_id) return 0; } =20 +static bool gic_virt_state_needed(void *opaque) +{ + GICState *s =3D (GICState *)opaque; + + return s->virt_extn; +} + static const VMStateDescription vmstate_gic_irq_state =3D { .name =3D "arm_gic_irq_state", .version_id =3D 1, @@ -62,6 +69,30 @@ static const VMStateDescription vmstate_gic_irq_state = =3D { } }; =20 +static const VMStateDescription vmstate_gic_virt_state =3D { + .name =3D "arm_gic_virt_state", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D gic_virt_state_needed, + .fields =3D (VMStateField[]) { + /* Virtual interface */ + VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU), + VMSTATE_UINT32_ARRAY(h_misr, GICState, GIC_NCPU), + VMSTATE_UINT32_2DARRAY(h_lr, GICState, GIC_MAX_LR, GIC_NCPU), + VMSTATE_UINT32_ARRAY(h_apr, GICState, GIC_NCPU), + + /* Virtual CPU interfaces */ + VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, GIC_NCPU, GIC_NCPU), + VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, GIC_NCPU, GIC_NC= PU), + VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, GIC_NCPU, GIC= _NCPU), + VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, GIC_NCPU, GIC_= NCPU), + VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, GIC_NCPU, GIC_NCPU), + VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, GIC_NCPU, GIC_NCPU), + + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_gic =3D { .name =3D "arm_gic", .version_id =3D 12, @@ -70,26 +101,31 @@ static const VMStateDescription vmstate_gic =3D { .post_load =3D gic_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINT32(ctlr, GICState), - VMSTATE_UINT32_ARRAY(cpu_ctlr, GICState, GIC_NCPU), + VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, 0, GIC_NCPU), VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1, vmstate_gic_irq_state, gic_irq_state), VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ), VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU), VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL= ), VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU= ), - VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU), - VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU), - VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU), - VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU), - VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU), + VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, 0, GIC_NCPU), + VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, 0, GIC_NCPU), + VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, 0, GIC_NCPU), + VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, 0, GIC_NCPU), + VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, 0, GIC_NCPU), VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU), VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * []) { + &vmstate_gic_virt_state, + NULL } }; =20 void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler, - const MemoryRegionOps *ops) + const MemoryRegionOps *ops, + const MemoryRegionOps *virt_ops) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(s); int i =3D s->num_irq - GIC_INTERNAL; @@ -116,6 +152,11 @@ void gic_init_irqs_and_mmio(GICState *s, qemu_irq_hand= ler handler, for (i =3D 0; i < s->num_cpu; i++) { sysbus_init_irq(sbd, &s->parent_vfiq[i]); } + if (s->virt_extn) { + for (i =3D 0; i < s->num_cpu; i++) { + sysbus_init_irq(sbd, &s->maintenance_irq[i]); + } + } =20 /* Distributor */ memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000= ); @@ -127,6 +168,17 @@ void gic_init_irqs_and_mmio(GICState *s, qemu_irq_hand= ler handler, memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL, s, "gic_cpu", s->revision =3D=3D 2 ? 0x2000 : 0x= 100); sysbus_init_mmio(sbd, &s->cpuiomem[0]); + + if (s->virt_extn) { + memory_region_init_io(&s->vifaceiomem, OBJECT(s), virt_ops, + s, "gic_viface", 0x1000); + sysbus_init_mmio(sbd, &s->vifaceiomem); + + memory_region_init_io(&s->vcpuiomem[0], OBJECT(s), + virt_ops ? &virt_ops[1] : NULL, + s, "gic_vcpu", 0x2000); + sysbus_init_mmio(sbd, &s->vcpuiomem[0]); + } } =20 static void arm_gic_common_realize(DeviceState *dev, Error **errp) @@ -163,6 +215,48 @@ static void arm_gic_common_realize(DeviceState *dev, E= rror **errp) "the security extensions"); return; } + + if (s->virt_extn) { + if (s->revision !=3D 2) { + error_setg(errp, "GIC virtualization extensions are only " + "supported by revision 2"); + return; + } + + /* For now, set the number of implemented LRs to 4, as found in mo= st + * real GICv2. This could be promoted as a QOM property if we need= to + * emulate a variant with another num_lrs. + */ + s->num_lrs =3D 4; + } +} + +static inline void arm_gic_common_reset_irq_state(GICState *s, int first_c= pu, + int resetprio) +{ + int i, j; + + for (i =3D first_cpu; i < first_cpu + s->num_cpu; i++) { + if (s->revision =3D=3D REV_11MPCORE) { + s->priority_mask[i] =3D 0xf0; + } else { + s->priority_mask[i] =3D resetprio; + } + s->current_pending[i] =3D 1023; + s->running_priority[i] =3D 0x100; + s->cpu_ctlr[i] =3D 0; + s->bpr[i] =3D gic_is_vcpu(i) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR; + s->abpr[i] =3D gic_is_vcpu(i) ? GIC_VIRT_MIN_ABPR : GIC_MIN_ABPR; + + if (!gic_is_vcpu(i)) { + for (j =3D 0; j < GIC_INTERNAL; j++) { + s->priority1[j][i] =3D resetprio; + } + for (j =3D 0; j < GIC_NR_SGIS; j++) { + s->sgi_pending[j][i] =3D 0; + } + } + } } =20 static void arm_gic_common_reset(DeviceState *dev) @@ -185,24 +279,15 @@ static void arm_gic_common_reset(DeviceState *dev) } =20 memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); - for (i =3D 0 ; i < s->num_cpu; i++) { - if (s->revision =3D=3D REV_11MPCORE) { - s->priority_mask[i] =3D 0xf0; - } else { - s->priority_mask[i] =3D resetprio; - } - s->current_pending[i] =3D 1023; - s->running_priority[i] =3D 0x100; - s->cpu_ctlr[i] =3D 0; - s->bpr[i] =3D GIC_MIN_BPR; - s->abpr[i] =3D GIC_MIN_ABPR; - for (j =3D 0; j < GIC_INTERNAL; j++) { - s->priority1[j][i] =3D resetprio; - } - for (j =3D 0; j < GIC_NR_SGIS; j++) { - s->sgi_pending[j][i] =3D 0; - } + arm_gic_common_reset_irq_state(s, 0, resetprio); + + if (s->virt_extn) { + /* vCPU states are stored at indexes GIC_NCPU .. GIC_NCPU+num_cpu. + * The exposed vCPU interface does not have security extensions. + */ + arm_gic_common_reset_irq_state(s, GIC_NCPU, 0); } + for (i =3D 0; i < GIC_NR_SGIS; i++) { GIC_DIST_SET_ENABLED(i, ALL_CPU_MASK); GIC_DIST_SET_EDGE_TRIGGER(i); @@ -226,6 +311,19 @@ static void arm_gic_common_reset(DeviceState *dev) } } =20 + if (s->virt_extn) { + for (i =3D 0; i < s->num_lrs; i++) { + for (j =3D 0; j < s->num_cpu; j++) { + s->h_lr[i][j] =3D 0; + } + } + + for (i =3D 0; i < s->num_cpu; i++) { + s->h_hcr[i] =3D 0; + s->h_misr[i] =3D 0; + } + } + s->ctlr =3D 0; } =20 @@ -255,6 +353,8 @@ static Property arm_gic_common_properties[] =3D { DEFINE_PROP_UINT32("revision", GICState, revision, 1), /* True if the GIC should implement the security extensions */ DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0= ), + /* True if the GIC should implement the virtualization extensions */ + DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn,= 0), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 4b611c8d6d..a611e8ee12 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -511,6 +511,12 @@ static void kvm_arm_gic_realize(DeviceState *dev, Erro= r **errp) return; } =20 + if (s->virt_extn) { + error_setg(errp, "the in-kernel VGIC does not implement the " + "virtualization extensions"); + return; + } + if (!kvm_arm_gic_can_save_restore(s)) { error_setg(&s->migration_blocker, "This operating system kernel do= es " "not support vGICv2 migration"); @@ -522,7 +528,7 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error= **errp) } } =20 - gic_init_irqs_and_mmio(s, kvm_arm_gicv2_set_irq, NULL); + gic_init_irqs_and_mmio(s, kvm_arm_gicv2_set_irq, NULL, NULL); =20 for (i =3D 0; i < s->num_irq - GIC_INTERNAL; i++) { qemu_irq irq =3D qdev_get_gpio_in(dev, i); diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index a2075a94db..c85427c8e3 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -94,4 +94,9 @@ static inline bool gic_test_pending(GICState *s, int irq,= int cm) } } =20 +static inline bool gic_is_vcpu(int cpu) +{ + return cpu >=3D GIC_NCPU; +} + #endif /* QEMU_ARM_GIC_INTERNAL_H */ diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_com= mon.h index af3ca18e2f..9aa1aa5188 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -30,6 +30,8 @@ #define GIC_NR_SGIS 16 /* Maximum number of possible CPU interfaces, determined by GIC architectu= re */ #define GIC_NCPU 8 +/* Maximum number of possible CPU interfaces with their respective vCPU */ +#define GIC_NCPU_VCPU (GIC_NCPU * 2) =20 #define MAX_NR_GROUP_PRIO 128 #define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32) @@ -37,6 +39,17 @@ #define GIC_MIN_BPR 0 #define GIC_MIN_ABPR (GIC_MIN_BPR + 1) =20 +/* Architectural maximum number of list registers in the virtual interface= */ +#define GIC_MAX_LR 64 + +/* Only 32 priority levels and 32 preemption levels in the vCPU interfaces= */ +#define GIC_VIRT_MAX_GROUP_PRIO_BITS 5 +#define GIC_VIRT_MAX_NR_GROUP_PRIO (1 << GIC_VIRT_MAX_GROUP_PRIO_BITS) +#define GIC_VIRT_NR_APRS (GIC_VIRT_MAX_NR_GROUP_PRIO / 32) + +#define GIC_VIRT_MIN_BPR 2 +#define GIC_VIRT_MIN_ABPR (GIC_VIRT_MIN_BPR + 1) + typedef struct gic_irq_state { /* The enable bits are only banked for per-cpu interrupts. */ uint8_t enabled; @@ -57,6 +70,8 @@ typedef struct GICState { qemu_irq parent_fiq[GIC_NCPU]; qemu_irq parent_virq[GIC_NCPU]; qemu_irq parent_vfiq[GIC_NCPU]; + qemu_irq maintenance_irq[GIC_NCPU]; + /* GICD_CTLR; for a GIC with the security extensions the NS banked ver= sion * of this register is just an alias of bit 1 of the S banked version. */ @@ -64,7 +79,7 @@ typedef struct GICState { /* GICC_CTLR; again, the NS banked version is just aliases of bits of * the S banked register, so our state only needs to store the S versi= on. */ - uint32_t cpu_ctlr[GIC_NCPU]; + uint32_t cpu_ctlr[GIC_NCPU_VCPU]; =20 gic_irq_state irq_state[GIC_MAXIRQ]; uint8_t irq_target[GIC_MAXIRQ]; @@ -78,9 +93,9 @@ typedef struct GICState { */ uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU]; =20 - uint16_t priority_mask[GIC_NCPU]; - uint16_t running_priority[GIC_NCPU]; - uint16_t current_pending[GIC_NCPU]; + uint16_t priority_mask[GIC_NCPU_VCPU]; + uint16_t running_priority[GIC_NCPU_VCPU]; + uint16_t current_pending[GIC_NCPU_VCPU]; =20 /* If we present the GICv2 without security extensions to a guest, * the guest can configure the GICC_CTLR to configure group 1 binary p= oint @@ -88,8 +103,8 @@ typedef struct GICState { * For a GIC with Security Extensions we use use bpr for the * secure copy and abpr as storage for the non-secure copy of the regi= ster. */ - uint8_t bpr[GIC_NCPU]; - uint8_t abpr[GIC_NCPU]; + uint8_t bpr[GIC_NCPU_VCPU]; + uint8_t abpr[GIC_NCPU_VCPU]; =20 /* The APR is implementation defined, so we choose a layout identical = to * the KVM ABI layout for QEMU's implementation of the gic: @@ -100,6 +115,15 @@ typedef struct GICState { uint32_t apr[GIC_NR_APRS][GIC_NCPU]; uint32_t nsapr[GIC_NR_APRS][GIC_NCPU]; =20 + /* Virtual interface control registers */ + uint32_t h_hcr[GIC_NCPU]; + uint32_t h_misr[GIC_NCPU]; + uint32_t h_lr[GIC_MAX_LR][GIC_NCPU]; + uint32_t h_apr[GIC_NCPU]; + + /* Number of LRs implemented in this GIC instance */ + uint32_t num_lrs; + uint32_t num_cpu; =20 MemoryRegion iomem; /* Distributor */ @@ -108,9 +132,13 @@ typedef struct GICState { */ struct GICState *backref[GIC_NCPU]; MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ + MemoryRegion vifaceiomem; /* Virtual interface */ + MemoryRegion vcpuiomem[GIC_NCPU + 1]; /* vCPU interface */ + uint32_t num_irq; uint32_t revision; bool security_extn; + bool virt_extn; bool irq_reset_nonsecure; /* configure IRQs as group 1 (NS) on reset? = */ int dev_fd; /* kvm device fd if backed by kvm vgic support */ Error *migration_blocker; @@ -134,6 +162,7 @@ typedef struct ARMGICCommonClass { } ARMGICCommonClass; =20 void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler, - const MemoryRegionOps *ops); + const MemoryRegionOps *ops, + const MemoryRegionOps *virt_ops); =20 #endif --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530279498846385.85707635300093; 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charset="utf-8" Add the register definitions for the virtual interface of the GICv2. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/gic_internal.h | 65 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index c85427c8e3..1aa888a576 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -21,6 +21,7 @@ #ifndef QEMU_ARM_GIC_INTERNAL_H #define QEMU_ARM_GIC_INTERNAL_H =20 +#include "hw/registerfields.h" #include "hw/intc/arm_gic.h" =20 #define ALL_CPU_MASK ((unsigned)(((1 << GIC_NCPU) - 1))) @@ -64,6 +65,70 @@ #define GICC_CTLR_EOIMODE (1U << 9) #define GICC_CTLR_EOIMODE_NS (1U << 10) =20 +REG32(GICH_HCR, 0x0) + FIELD(GICH_HCR, EN, 0, 1) + FIELD(GICH_HCR, UIE, 1, 1) + FIELD(GICH_HCR, LRENPIE, 2, 1) + FIELD(GICH_HCR, NPIE, 3, 1) + FIELD(GICH_HCR, VGRP0EIE, 4, 1) + FIELD(GICH_HCR, VGRP0DIE, 5, 1) + FIELD(GICH_HCR, VGRP1EIE, 6, 1) + FIELD(GICH_HCR, VGRP1DIE, 7, 1) + FIELD(GICH_HCR, EOICount, 27, 5) + +#define GICH_HCR_MASK \ + (R_GICH_HCR_EN_MASK | R_GICH_HCR_UIE_MASK | \ + R_GICH_HCR_LRENPIE_MASK | R_GICH_HCR_NPIE_MASK | \ + R_GICH_HCR_VGRP0EIE_MASK | R_GICH_HCR_VGRP0DIE_MASK | \ + R_GICH_HCR_VGRP1EIE_MASK | R_GICH_HCR_VGRP1DIE_MASK | \ + R_GICH_HCR_EOICount_MASK) + +REG32(GICH_VTR, 0x4) + FIELD(GICH_VTR, ListRegs, 0, 6) + FIELD(GICH_VTR, PREbits, 26, 3) + FIELD(GICH_VTR, PRIbits, 29, 3) + +REG32(GICH_VMCR, 0x8) + FIELD(GICH_VMCR, VMCCtlr, 0, 10) + FIELD(GICH_VMCR, VMABP, 18, 3) + FIELD(GICH_VMCR, VMBP, 21, 3) + FIELD(GICH_VMCR, VMPriMask, 27, 5) + +REG32(GICH_MISR, 0x10) + FIELD(GICH_MISR, EOI, 0, 1) + FIELD(GICH_MISR, U, 1, 1) + FIELD(GICH_MISR, LRENP, 2, 1) + FIELD(GICH_MISR, NP, 3, 1) + FIELD(GICH_MISR, VGrp0E, 4, 1) + FIELD(GICH_MISR, VGrp0D, 5, 1) + FIELD(GICH_MISR, VGrp1E, 6, 1) + FIELD(GICH_MISR, VGrp1D, 7, 1) + +REG32(GICH_EISR0, 0x20) +REG32(GICH_EISR1, 0x24) +REG32(GICH_ELRSR0, 0x30) +REG32(GICH_ELRSR1, 0x34) +REG32(GICH_APR, 0xf0) + +REG32(GICH_LR0, 0x100) + FIELD(GICH_LR0, VirtualID, 0, 10) + FIELD(GICH_LR0, PhysicalID, 10, 10) + FIELD(GICH_LR0, CPUID, 10, 3) + FIELD(GICH_LR0, EOI, 19, 1) + FIELD(GICH_LR0, Priority, 23, 5) + FIELD(GICH_LR0, State, 28, 2) + FIELD(GICH_LR0, Grp1, 30, 1) + FIELD(GICH_LR0, HW, 31, 1) + +/* Last LR register */ +REG32(GICH_LR63, 0x1fc) + +#define GICH_LR_MASK \ + (R_GICH_LR0_VirtualID_MASK | R_GICH_LR0_PhysicalID_MASK | \ + R_GICH_LR0_CPUID_MASK | R_GICH_LR0_EOI_MASK | \ + R_GICH_LR0_Priority_MASK | R_GICH_LR0_State_MASK | \ + R_GICH_LR0_Grp1_MASK | R_GICH_LR0_HW_MASK) + /* Valid bits for GICC_CTLR for GICv1, v1 with security extensions, * GICv2 and GICv2 with security extensions: */ --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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b=lf5D6AoiPIfE1FmHFqPvPVgM3xIfzwS3HzAIhC09yl1ya1CF0m2VqMUzFpRbK09oh U06o4NH6zpf55LTBxTQ4ipuSD6oDJqFXYVtvts47+AL7zgebXDRVOrpNCI+sbPqcxV Ftts4ROJPk+3XRDPlIgouu3tG6uZqOKcvinCjc9o= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=IvFNyGOR; dkim=pass (1024-bit key) header.d=greensocs.com header.b=XXoreDuC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279035; bh=HwYjVSWnlKOVRNfYFf6N6iHysaScDzknQYqvQobDsn4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=IvFNyGOR0XrXasd40CSBDnVSnkEvrvDROZdbe0IJdiSNtvekSa9iG7PnGmkPnNmGp NiUr37d4fjoBuR+Lry7D/AXw+gw66rIlg2OM+AIFnd7Pg9XG2bmrmkbuLp1aZtsIrr 4bwC3NvZa83DxDIdRREGp64lVYTfaS9WOT52osAs= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279034; bh=HwYjVSWnlKOVRNfYFf6N6iHysaScDzknQYqvQobDsn4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=XXoreDuChSOLCR65B85JIQA1/0iuf37INmj2e6KIPL5e3K63iA3oMfpseZxT/Rapm cCjHW10zXsKQFKaM2wS/Rztkit0V8v+UJLQrnzJ6wlgCgnSu47czt7P8uKVuLJ51x7 BFX6JWP3/aIPZPXV/7sQH0vEkrL+0hl5Pp2uCk8U= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:41 +0200 Message-Id: <20180629132954.24269-8-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 07/20] intc/arm_gic: Add virtualization extensions helper macros and functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 3 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add some helper macros and functions related to the virtualization extensions to gic_internal.h. The GICH_LR_* macros help extracting specific fields of a list register value. The only tricky one is the priority field as only the MSB are stored. The value must be shifted accordingly to obtain the correct priority value. gic_is_vcpu() and gic_get_vcpu_real_id() help with (v)CPU id manipulation to abstract the fact that vCPU id are in the range [ GIC_NCPU; (GIC_NCPU + num_cpu) [. gic_lr_* and gic_virq_is_valid() help with the list registers. gic_get_lr_entry() tries to find the LR entry for a given (vCPU, irq) pair. gic_get_lr_entry_nofail() is meant to be used in contexts where we know for sure that the entry exists, so we can avoid the NULL check on the returned pointer. Signed-off-by: Luc Michel --- hw/intc/arm_gic.c | 5 ++++ hw/intc/gic_internal.h | 65 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index b2dd379bd2..f25d1b1270 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -61,6 +61,11 @@ static inline int gic_get_current_cpu(GICState *s) return 0; } =20 +static inline int gic_get_current_vcpu(GICState *s) +{ + return gic_get_current_cpu(s) + GIC_NCPU; +} + /* Return true if this GIC config has interrupt groups, which is * true if we're a GICv2, or a GICv1 with the security extensions. */ diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 1aa888a576..4242a16bd4 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -129,6 +129,20 @@ REG32(GICH_LR63, 0x1fc) R_GICH_LR0_Priority_MASK | R_GICH_LR0_State_MASK | \ R_GICH_LR0_Grp1_MASK | R_GICH_LR0_HW_MASK) =20 +#define GICH_LR_STATE_INVALID 0 +#define GICH_LR_STATE_PENDING 1 +#define GICH_LR_STATE_ACTIVE 2 +#define GICH_LR_STATE_ACTIVE_PENDING 3 + +#define GICH_LR_VIRT_ID(entry) (FIELD_EX32(entry, GICH_LR0, VirtualID)) +#define GICH_LR_PHYS_ID(entry) (FIELD_EX32(entry, GICH_LR0, PhysicalID)) +#define GICH_LR_CPUID(entry) (FIELD_EX32(entry, GICH_LR0, CPUID)) +#define GICH_LR_EOI(entry) (FIELD_EX32(entry, GICH_LR0, EOI)) +#define GICH_LR_PRIORITY(entry) (FIELD_EX32(entry, GICH_LR0, Priority) << = 3) +#define GICH_LR_STATE(entry) (FIELD_EX32(entry, GICH_LR0, State)) +#define GICH_LR_GROUP(entry) (FIELD_EX32(entry, GICH_LR0, Grp1)) +#define GICH_LR_HW(entry) (FIELD_EX32(entry, GICH_LR0, HW)) + /* Valid bits for GICC_CTLR for GICv1, v1 with security extensions, * GICv2 and GICv2 with security extensions: */ @@ -164,4 +178,55 @@ static inline bool gic_is_vcpu(int cpu) return cpu >=3D GIC_NCPU; } =20 +static inline int gic_get_vcpu_real_id(int cpu) +{ + return (cpu >=3D GIC_NCPU) ? (cpu - GIC_NCPU) : cpu; +} + +static inline bool gic_lr_entry_is_free(uint32_t entry) +{ + return (GICH_LR_STATE(entry) =3D=3D GICH_LR_STATE_INVALID) + && (GICH_LR_HW(entry) || !GICH_LR_EOI(entry)); +} + +static inline bool gic_lr_entry_is_eoi(uint32_t entry) +{ + return (GICH_LR_STATE(entry) =3D=3D GICH_LR_STATE_INVALID) + && !GICH_LR_HW(entry) && GICH_LR_EOI(entry); +} + +/* Return a pointer on the LR entry for a given (irq,vcpu) pair. + * Having multiple LRs with the same VirtualID leads to UNPREDICTABLE + * behaviour in the GIC. We choose to return the first one that matches. + */ +static inline uint32_t *gic_get_lr_entry(GICState *s, int irq, int vcpu) +{ + int cpu =3D gic_get_vcpu_real_id(vcpu); + int lr_idx; + + for (lr_idx =3D 0; lr_idx < s->num_lrs; lr_idx++) { + uint32_t *entry =3D &s->h_lr[lr_idx][cpu]; + + if ((GICH_LR_VIRT_ID(*entry) =3D=3D irq) && + (!gic_lr_entry_is_free(*entry))) { + return entry; + } + } + + return NULL; +} + +static inline bool gic_virq_is_valid(GICState *s, int irq, int vcpu) +{ + return gic_get_lr_entry(s, irq, vcpu) !=3D NULL; +} + +static inline uint32_t *gic_get_lr_entry_nofail(GICState *s, int irq, int = vcpu) +{ + uint32_t *entry =3D gic_get_lr_entry(s, irq, vcpu); + assert(entry); + + return entry; +} + #endif /* QEMU_ARM_GIC_INTERNAL_H */ --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 29 Jun 2018 09:30:42 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 2EDB54434AF; Fri, 29 Jun 2018 15:30:37 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MHdXg_DQIdLy; Fri, 29 Jun 2018 15:30:35 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id DC8114434B1; Fri, 29 Jun 2018 15:30:35 +0200 (CEST) Received: from michell-laptop.hive.antfield.fr (LFbn-LYO-1-488-36.w2-7.abo.wanadoo.fr [2.7.77.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 12F074434B3; Fri, 29 Jun 2018 15:30:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279037; bh=+LWsPsIqavWrJSscmGjxw0qJwL1sojvQVzV7xzhVY40=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ga4N4GCDoW2gnS/0CIjhf8N2FdqtAQhrfx/mXugHkW/THjeg2TVi//xwI/iq/OTQc bzkNQJy+YTuRmbiXkbfRHVNRJmFr3w9lG5//njpDfrbdkJ4KhQgVWn4W2fUepkmDPq ntbQCbS6CruxDDAiutjbnSKjxwgvUxVIugr9WpOE= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=tjYQrVLa; dkim=pass (1024-bit key) header.d=greensocs.com header.b=tjYQrVLa DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279035; bh=+LWsPsIqavWrJSscmGjxw0qJwL1sojvQVzV7xzhVY40=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=tjYQrVLaaIi7OpYrCJCqyP4E9Il3IjIphoCLZ5TsThD36E2hNEGQ7kRpj0T8DCwhr J3A0gSWZoYD4ZlKLtHV5LstqdFfbv9EUCZU51V/DiUEkBGmhpgloAhnj89K1jysDhb D4JchLyIIw/y3XRB58BlMzQSS6LEMw4hjLxs9omM= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279035; bh=+LWsPsIqavWrJSscmGjxw0qJwL1sojvQVzV7xzhVY40=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=tjYQrVLaaIi7OpYrCJCqyP4E9Il3IjIphoCLZ5TsThD36E2hNEGQ7kRpj0T8DCwhr J3A0gSWZoYD4ZlKLtHV5LstqdFfbv9EUCZU51V/DiUEkBGmhpgloAhnj89K1jysDhb D4JchLyIIw/y3XRB58BlMzQSS6LEMw4hjLxs9omM= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:42 +0200 Message-Id: <20180629132954.24269-9-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 08/20] intc/arm_gic: Refactor secure/ns access check in the CPU interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" An access to the CPU interface is non-secure if the current GIC instance implements the security extensions, and the memory access is actually non-secure. Until then, it was checked with tests such as if (s->security_extn && !attrs.secure) { ... } in various places of the CPU interface code. With the implementation of the virtualization extensions, those tests must be updated to take into account whether we are in a vCPU interface or not. This is because the exposed vCPU interface does not implement security extensions. This commits replaces all those tests with a call to the gic_cpu_ns_access() function to check if the current access to the CPU interface is non-secure. This function takes into account whether the current CPU is a vCPU or not. Note that this function is used only in the (v)CPU interface code path. The distributor code path is leaved unchanged, as the distributor is not exposed to vCPUs at all. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 39 ++++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index f25d1b1270..8ab3025901 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -74,6 +74,11 @@ static inline bool gic_has_groups(GICState *s) return s->revision =3D=3D 2 || s->security_extn; } =20 +static inline bool gic_cpu_ns_access(GICState *s, int cpu, MemTxAttrs attr= s) +{ + return !gic_is_vcpu(cpu) && s->security_extn && !attrs.secure; +} + /* TODO: Many places that call this routine could be optimized. */ /* Update interrupt status after enabled or pending bits have been changed= . */ static void gic_update(GICState *s) @@ -221,7 +226,7 @@ static uint16_t gic_get_current_pending_irq(GICState *s= , int cpu, /* On a GIC without the security extensions, reading this register * behaves in the same way as a secure access to a GIC with them. */ - bool secure =3D !s->security_extn || attrs.secure; + bool secure =3D !gic_cpu_ns_access(s, cpu, attrs); =20 if (group =3D=3D 0 && !secure) { /* Group0 interrupts hidden from Non-secure access */ @@ -428,7 +433,7 @@ static uint32_t gic_dist_get_priority(GICState *s, int = cpu, int irq, static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, MemTxAttrs attrs) { - if (s->security_extn && !attrs.secure) { + if (gic_cpu_ns_access(s, cpu, attrs)) { if (s->priority_mask[cpu] & 0x80) { /* Priority Mask in upper half */ pmask =3D 0x80 | (pmask >> 1); @@ -444,7 +449,7 @@ static uint32_t gic_get_priority_mask(GICState *s, int = cpu, MemTxAttrs attrs) { uint32_t pmask =3D s->priority_mask[cpu]; =20 - if (s->security_extn && !attrs.secure) { + if (gic_cpu_ns_access(s, cpu, attrs)) { if (pmask & 0x80) { /* Priority Mask in upper half, return Non-secure view */ pmask =3D (pmask << 1) & 0xff; @@ -460,7 +465,7 @@ static uint32_t gic_get_cpu_control(GICState *s, int cp= u, MemTxAttrs attrs) { uint32_t ret =3D s->cpu_ctlr[cpu]; =20 - if (s->security_extn && !attrs.secure) { + if (gic_cpu_ns_access(s, cpu, attrs)) { /* Construct the NS banked view of GICC_CTLR from the correct * bits of the S banked view. We don't need to move the bypass * control bits because we don't implement that (IMPDEF) part @@ -476,7 +481,7 @@ static void gic_set_cpu_control(GICState *s, int cpu, u= int32_t value, { uint32_t mask; =20 - if (s->security_extn && !attrs.secure) { + if (gic_cpu_ns_access(s, cpu, attrs)) { /* The NS view can only write certain bits in the register; * the rest are unchanged */ @@ -507,7 +512,7 @@ static uint8_t gic_get_running_priority(GICState *s, in= t cpu, MemTxAttrs attrs) return 0xff; } =20 - if (s->security_extn && !attrs.secure) { + if (gic_cpu_ns_access(s, cpu, attrs)) { if (s->running_priority[cpu] & 0x80) { /* Running priority in upper half of range: return the Non-sec= ure * view of the priority. @@ -531,7 +536,7 @@ static bool gic_eoi_split(GICState *s, int cpu, MemTxAt= trs attrs) /* Before GICv2 prio-drop and deactivate are not separable */ return false; } - if (s->security_extn && !attrs.secure) { + if (gic_cpu_ns_access(s, cpu, attrs)) { return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; } return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; @@ -549,7 +554,7 @@ static void gic_deactivate_irq(GICState *s, int cpu, in= t irq, MemTxAttrs attrs) return; } =20 - if (s->security_extn && !attrs.secure && !group) { + if (gic_cpu_ns_access(s, cpu, attrs) && !group) { DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); return; } @@ -591,7 +596,7 @@ static void gic_complete_irq(GICState *s, int cpu, int = irq, MemTxAttrs attrs) =20 group =3D gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm); =20 - if (s->security_extn && !attrs.secure && !group) { + if (gic_cpu_ns_access(s, cpu, attrs) && !group) { DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); return; } @@ -1249,7 +1254,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu,= int offset, *data =3D gic_get_priority_mask(s, cpu, attrs); break; case 0x08: /* Binary Point */ - if (s->security_extn && !attrs.secure) { + if (gic_cpu_ns_access(s, cpu, attrs)) { if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { /* NS view of BPR when CBPR is 1 */ *data =3D MIN(s->bpr[cpu] + 1, 7); @@ -1276,7 +1281,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu,= int offset, * With security extensions, secure access: ABPR (alias of NS BPR) * With security extensions, nonsecure access: RAZ/WI */ - if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { + if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { *data =3D 0; } else { *data =3D s->abpr[cpu]; @@ -1288,7 +1293,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu,= int offset, =20 if (regno >=3D GIC_NR_APRS || s->revision !=3D 2) { *data =3D 0; - } else if (s->security_extn && !attrs.secure) { + } else if (gic_cpu_ns_access(s, cpu, attrs)) { /* NS view of GICC_APR is the top half of GIC_NSAPR */ *data =3D gic_apr_ns_view(s, regno, cpu); } else { @@ -1301,7 +1306,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu,= int offset, int regno =3D (offset - 0xe0) / 4; =20 if (regno >=3D GIC_NR_APRS || s->revision !=3D 2 || !gic_has_group= s(s) || - (s->security_extn && !attrs.secure)) { + gic_cpu_ns_access(s, cpu, attrs)) { *data =3D 0; } else { *data =3D s->nsapr[regno][cpu]; @@ -1328,7 +1333,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu= , int offset, gic_set_priority_mask(s, cpu, value, attrs); break; case 0x08: /* Binary Point */ - if (s->security_extn && !attrs.secure) { + if (gic_cpu_ns_access(s, cpu, attrs)) { if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { /* WI when CBPR is 1 */ return MEMTX_OK; @@ -1343,7 +1348,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu= , int offset, gic_complete_irq(s, cpu, value & 0x3ff, attrs); return MEMTX_OK; case 0x1c: /* Aliased Binary Point */ - if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { + if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { /* unimplemented, or NS access: RAZ/WI */ return MEMTX_OK; } else { @@ -1357,7 +1362,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu= , int offset, if (regno >=3D GIC_NR_APRS || s->revision !=3D 2) { return MEMTX_OK; } - if (s->security_extn && !attrs.secure) { + if (gic_cpu_ns_access(s, cpu, attrs)) { /* NS view of GICC_APR is the top half of GIC_NSAPR */ gic_apr_write_ns_view(s, regno, cpu, value); } else { @@ -1372,7 +1377,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu= , int offset, if (regno >=3D GIC_NR_APRS || s->revision !=3D 2) { return MEMTX_OK; } - if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { + if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { return MEMTX_OK; } s->nsapr[regno][cpu] =3D value; --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530280052624154.46828139985644; Fri, 29 Jun 2018 06:47:32 -0700 (PDT) Received: from localhost ([::1]:42256 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtkG-0004s6-6Z for importer@patchew.org; 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Fri, 29 Jun 2018 15:30:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279037; bh=Bil+frXao78+kycLwohEdCE57evq9N47sfNCjZ6KNLo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=i8Ma9jX5LL0mO4aR8BJJRCeD4R/k22KktKb9UNXeVh3Ovtbr0VYR3KG/Jym74vhjW POrGLwdS8YzlvF7cuZwx7y1O+6CG4POVmujggndhf6jSnc3h/llFbkS9DtAOi89IIX xGWLqfpq9/BKpMmeZ8Pky3fhN3O9FHMMOh9jWZ6Y= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=l9V/TH0a; dkim=pass (1024-bit key) header.d=greensocs.com header.b=l9V/TH0a DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279036; bh=Bil+frXao78+kycLwohEdCE57evq9N47sfNCjZ6KNLo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=l9V/TH0arxkD+WTCr/+Sr8LB4kwXc12QX4MIp8V5JU4aMOlHVvHoinZx6jRWS21V7 0It+N8vj4dMiUXpAA5uUL8YXOeK0OHU6O19Uuc3nbRCoiDL77LFB+HSsNlvBQSw9+t OhGfjjQiUCP/7mE/6s+rb6UelEiFbFRglIVMwGyg= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279036; bh=Bil+frXao78+kycLwohEdCE57evq9N47sfNCjZ6KNLo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=l9V/TH0arxkD+WTCr/+Sr8LB4kwXc12QX4MIp8V5JU4aMOlHVvHoinZx6jRWS21V7 0It+N8vj4dMiUXpAA5uUL8YXOeK0OHU6O19Uuc3nbRCoiDL77LFB+HSsNlvBQSw9+t OhGfjjQiUCP/7mE/6s+rb6UelEiFbFRglIVMwGyg= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:43 +0200 Message-Id: <20180629132954.24269-10-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 09/20] intc/arm_gic: Add virtualization enabled IRQ helper functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add some helper functions to gic_internal.h to get or change the state of an IRQ. When the current CPU is not a vCPU, the call is forwarded to the GIC distributor. Otherwise, it acts on the list register matching the IRQ in the current CPU virtual interface. gic_clear_active can have a side effect on the distributor, even in the vCPU case, when the correponding LR has the HW field set. Use those functions in the CPU interface code path to prepare for the vCPU interface implementation. Signed-off-by: Luc Michel --- hw/intc/arm_gic.c | 32 ++++++++--------- hw/intc/gic_internal.h | 78 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+), 18 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 8ab3025901..d55a88bb33 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -222,7 +222,8 @@ static uint16_t gic_get_current_pending_irq(GICState *s= , int cpu, uint16_t pending_irq =3D s->current_pending[cpu]; =20 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { - int group =3D GIC_DIST_TEST_GROUP(pending_irq, (1 << cpu)); + int group =3D gic_test_group(s, pending_irq, cpu); + /* On a GIC without the security extensions, reading this register * behaves in the same way as a secure access to a GIC with them. */ @@ -253,7 +254,7 @@ static int gic_get_group_priority(GICState *s, int cpu,= int irq) =20 if (gic_has_groups(s) && !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && - GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { + gic_test_group(s, irq, cpu)) { bpr =3D s->abpr[cpu] - 1; assert(bpr >=3D 0); } else { @@ -266,7 +267,7 @@ static int gic_get_group_priority(GICState *s, int cpu,= int irq) */ mask =3D ~0U << ((bpr & 7) + 1); =20 - return GIC_DIST_GET_PRIORITY(irq, cpu) & mask; + return gic_get_priority(s, irq, cpu) & mask; } =20 static void gic_activate_irq(GICState *s, int cpu, int irq) @@ -279,14 +280,14 @@ static void gic_activate_irq(GICState *s, int cpu, in= t irq) int regno =3D preemption_level / 32; int bitno =3D preemption_level % 32; =20 - if (gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { + if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) { s->nsapr[regno][cpu] |=3D (1 << bitno); } else { s->apr[regno][cpu] |=3D (1 << bitno); } =20 s->running_priority[cpu] =3D prio; - GIC_DIST_SET_ACTIVE(irq, 1 << cpu); + gic_set_active(s, irq, cpu); } =20 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) @@ -355,7 +356,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemT= xAttrs attrs) return irq; } =20 - if (GIC_DIST_GET_PRIORITY(irq, cpu) >=3D s->running_priority[cpu]) { + if (gic_get_priority(s, irq, cpu) >=3D s->running_priority[cpu]) { DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n",= irq); return 1023; } @@ -364,8 +365,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemT= xAttrs attrs) /* Clear pending flags for both level and edge triggered interrupt= s. * Level triggered IRQs will be reasserted once they become inacti= ve. */ - GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK - : cm); + gic_clear_pending(s, irq, cpu); ret =3D irq; } else { if (irq < GIC_NR_SGIS) { @@ -377,9 +377,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemT= xAttrs attrs) src =3D ctz32(s->sgi_pending[irq][cpu]); s->sgi_pending[irq][cpu] &=3D ~(1 << src); if (s->sgi_pending[irq][cpu] =3D=3D 0) { - GIC_DIST_CLEAR_PENDING(irq, - GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_= MASK - : cm); + gic_clear_pending(s, irq, cpu); } ret =3D irq | ((src & 0x7) << 10); } else { @@ -387,8 +385,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemT= xAttrs attrs) * interrupts. (level triggered interrupts with an active line * remain pending, see gic_test_pending) */ - GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU= _MASK - : cm); + gic_clear_pending(s, irq, cpu); ret =3D irq; } } @@ -544,8 +541,7 @@ static bool gic_eoi_split(GICState *s, int cpu, MemTxAt= trs attrs) =20 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs a= ttrs) { - int cm =3D 1 << cpu; - int group =3D gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm); + int group =3D gic_has_groups(s) && gic_test_group(s, irq, cpu); =20 if (!gic_eoi_split(s, cpu, attrs)) { /* This is UNPREDICTABLE; we choose to ignore it */ @@ -559,7 +555,7 @@ static void gic_deactivate_irq(GICState *s, int cpu, in= t irq, MemTxAttrs attrs) return; } =20 - GIC_DIST_CLEAR_ACTIVE(irq, cm); + gic_clear_active(s, irq, cpu); } =20 static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs att= rs) @@ -594,7 +590,7 @@ static void gic_complete_irq(GICState *s, int cpu, int = irq, MemTxAttrs attrs) } } =20 - group =3D gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm); + group =3D gic_has_groups(s) && gic_test_group(s, irq, cpu); =20 if (gic_cpu_ns_access(s, cpu, attrs) && !group) { DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); @@ -610,7 +606,7 @@ static void gic_complete_irq(GICState *s, int cpu, int = irq, MemTxAttrs attrs) =20 /* In GICv2 the guest can choose to split priority-drop and deactivate= */ if (!gic_eoi_split(s, cpu, attrs)) { - GIC_DIST_CLEAR_ACTIVE(irq, cm); + gic_clear_active(s, irq, cpu); } gic_update(s); } diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 4242a16bd4..4cacd34264 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -143,6 +143,13 @@ REG32(GICH_LR63, 0x1fc) #define GICH_LR_GROUP(entry) (FIELD_EX32(entry, GICH_LR0, Grp1)) #define GICH_LR_HW(entry) (FIELD_EX32(entry, GICH_LR0, HW)) =20 +#define GICH_LR_CLEAR_PENDING(entry) \ + ((entry) &=3D ~(GICH_LR_STATE_PENDING << R_GICH_LR0_State_SHIFT)) +#define GICH_LR_SET_ACTIVE(entry) \ + ((entry) |=3D (GICH_LR_STATE_ACTIVE << R_GICH_LR0_State_SHIFT)) +#define GICH_LR_CLEAR_ACTIVE(entry) \ + ((entry) &=3D ~(GICH_LR_STATE_ACTIVE << R_GICH_LR0_State_SHIFT)) + /* Valid bits for GICC_CTLR for GICv1, v1 with security extensions, * GICv2 and GICv2 with security extensions: */ @@ -229,4 +236,75 @@ static inline uint32_t *gic_get_lr_entry_nofail(GICSta= te *s, int irq, int vcpu) return entry; } =20 +static inline bool gic_test_group(GICState *s, int irq, int cpu) +{ + if (gic_is_vcpu(cpu)) { + uint32_t *entry =3D gic_get_lr_entry_nofail(s, irq, cpu); + return GICH_LR_GROUP(*entry); + } else { + return GIC_DIST_TEST_GROUP(irq, 1 << cpu); + } +} + +static inline void gic_clear_pending(GICState *s, int irq, int cpu) +{ + if (gic_is_vcpu(cpu)) { + uint32_t *entry =3D gic_get_lr_entry_nofail(s, irq, cpu); + GICH_LR_CLEAR_PENDING(*entry); + } else { + /* Clear pending state for both level and edge triggered + * interrupts. (level triggered interrupts with an active line + * remain pending, see gic_test_pending) + */ + GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK + : (1 << cpu)); + } +} + +static inline void gic_set_active(GICState *s, int irq, int cpu) +{ + if (gic_is_vcpu(cpu)) { + uint32_t *entry =3D gic_get_lr_entry_nofail(s, irq, cpu); + GICH_LR_SET_ACTIVE(*entry); + } else { + GIC_DIST_SET_ACTIVE(irq, 1 << cpu); + } +} + +static inline void gic_clear_active(GICState *s, int irq, int cpu) +{ + if (gic_is_vcpu(cpu)) { + uint32_t *entry =3D gic_get_lr_entry_nofail(s, irq, cpu); + GICH_LR_CLEAR_ACTIVE(*entry); + + if (GICH_LR_HW(*entry)) { + /* Hardware interrupt. We must forward the deactivation reques= t to + * the distributor. + */ + int phys_irq =3D GICH_LR_PHYS_ID(*entry); + int rcpu =3D gic_get_vcpu_real_id(cpu); + + /* This is equivalent to a NS write to DIR on the physical CPU + * interface. Hence group0 interrupt deactivation is ignored if + * the GIC is secure. + */ + if (!s->security_extn || GIC_DIST_TEST_GROUP(phys_irq, 1 << rc= pu)) { + GIC_DIST_CLEAR_ACTIVE(phys_irq, 1 << rcpu); + } + } + } else { + GIC_DIST_CLEAR_ACTIVE(irq, 1 << cpu); + } +} + +static inline int gic_get_priority(GICState *s, int irq, int cpu) +{ + if (gic_is_vcpu(cpu)) { + uint32_t *entry =3D gic_get_lr_entry_nofail(s, irq, cpu); + return GICH_LR_PRIORITY(*entry); + } else { + return GIC_DIST_GET_PRIORITY(irq, cpu); + } +} + #endif /* QEMU_ARM_GIC_INTERNAL_H */ --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530279853326372.8526676768673; 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dkim=pass (1024-bit key) header.d=greensocs.com header.b=vO1QPaZR DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279037; bh=MIz3Xya7Bfs70SeBav01e9oe2TZ/yq+G0OAvywSvOto=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=dQDCi1cKCo4pZ10+VbS9/xberr0FCBO4HtmgNAyGJNI8P7EKU8zJoDVY8c8a6lIeG Am7UK6SvbBfipbNkpwfupz8/IjEaye//WOMsnDx4OqKKaQy3S0yY0UBfV4/gLIzYbM wyCIINALKij6Jshse197hhF9t56HanjzAHS0rlWE= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279036; bh=MIz3Xya7Bfs70SeBav01e9oe2TZ/yq+G0OAvywSvOto=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=vO1QPaZRpwoihA7xC09UPu5FvEhEBk9LzD4kwxH7TthFaFG7Osn4okoPiZ9Ik7nTw qi/btPUYz/nWwDgclzyT5J5szVu0IiJszrL3wXLg189ZWJ/H2vbhjy2pei0eKaO74D 4gwbUc63bR8pbc5sBPFqewLWFbFMqSx/RWbptaxo= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:44 +0200 Message-Id: <20180629132954.24269-11-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 10/20] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_prio) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 3 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement virtualization extensions in gic_activate_irq() and gic_drop_prio() and in gic_get_prio_from_apr_bits() called by gic_drop_prio(). When the current CPU is a vCPU: - Use GIC_VIRT_MIN_BPR and GIC_VIRT_NR_APRS instead of their non-virt counterparts, - the vCPU APR is stored in the virtual interface, in h_apr. Signed-off-by: Luc Michel --- hw/intc/arm_gic.c | 45 ++++++++++++++++++++++++++++++++++++--------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index d55a88bb33..d61c2dd557 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -276,16 +276,23 @@ static void gic_activate_irq(GICState *s, int cpu, in= t irq) * and update the running priority. */ int prio =3D gic_get_group_priority(s, cpu, irq); - int preemption_level =3D prio >> (GIC_MIN_BPR + 1); + int min_bpr =3D gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR; + int preemption_level =3D prio >> (min_bpr + 1); int regno =3D preemption_level / 32; int bitno =3D preemption_level % 32; + uint32_t *papr =3D NULL; =20 - if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) { - s->nsapr[regno][cpu] |=3D (1 << bitno); + if (gic_is_vcpu(cpu)) { + assert(regno =3D=3D 0); + papr =3D &s->h_apr[gic_get_vcpu_real_id(cpu)]; + } else if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) { + papr =3D &s->nsapr[regno][cpu]; } else { - s->apr[regno][cpu] |=3D (1 << bitno); + papr =3D &s->apr[regno][cpu]; } =20 + *papr |=3D (1 << bitno); + s->running_priority[cpu] =3D prio; gic_set_active(s, irq, cpu); } @@ -296,12 +303,22 @@ static int gic_get_prio_from_apr_bits(GICState *s, in= t cpu) * on the set bits in the Active Priority Registers. */ int i; - for (i =3D 0; i < GIC_NR_APRS; i++) { - uint32_t apr =3D s->apr[i][cpu] | s->nsapr[i][cpu]; + int min_bpr =3D gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR; + int nr_aprs =3D gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; + + for (i =3D 0; i < nr_aprs; i++) { + uint32_t apr; + + if (gic_is_vcpu(cpu)) { + apr =3D s->h_apr[gic_get_vcpu_real_id(cpu)]; + } else { + apr =3D s->apr[i][cpu] | s->nsapr[i][cpu]; + } + if (!apr) { continue; } - return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); + return (i * 32 + ctz32(apr)) << (min_bpr + 1); } return 0x100; } @@ -325,9 +342,19 @@ static void gic_drop_prio(GICState *s, int cpu, int gr= oup) * might not do so, and interrupts that should not preempt might do so. */ int i; + int nr_aprs =3D gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; + + for (i =3D 0; i < nr_aprs; i++) { + uint32_t *papr =3D NULL; + + if (gic_is_vcpu(cpu)) { + papr =3D &s->h_apr[gic_get_vcpu_real_id(cpu)]; + } else if (group) { + papr =3D &s->nsapr[i][cpu]; + } else { + papr =3D &s->apr[i][cpu]; + } =20 - for (i =3D 0; i < GIC_NR_APRS; i++) { - uint32_t *papr =3D group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; if (!*papr) { continue; } --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530279665276423.96338741755847; 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Fri, 29 Jun 2018 15:30:37 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 9F5354434B1; Fri, 29 Jun 2018 15:30:37 +0200 (CEST) Received: from michell-laptop.hive.antfield.fr (LFbn-LYO-1-488-36.w2-7.abo.wanadoo.fr [2.7.77.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 314144434B5; Fri, 29 Jun 2018 15:30:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279038; bh=QszQPZXYcFkSBsQQnLZxtmc59qcfJEbtosKMiFwaW9Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=koWroJbm3H2MhVCGPRohwFDUdV09eB/V4+YQUF/azbk87yEEMXL5Z0lm8ZLUeWETD uT6t/ilESrfWQnUuhqQn+sdT5lx17iRFSeXGBZjEaOjOxBkjP6rPd/V2JRdNlPi66O 4m4IY4tob3qzFld78qEiwOksBhl20YHVimiuJ9hQ= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=llcfmHSa; dkim=pass (1024-bit key) header.d=greensocs.com header.b=llcfmHSa DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279037; bh=QszQPZXYcFkSBsQQnLZxtmc59qcfJEbtosKMiFwaW9Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=llcfmHSayx1GclAFdkF/XUQBPsVWGfMs8rmH9480QJwCQ6wgRKcSUH6ehg2bUVOmF sn9K7c/2TbEerKNgecNckBmZ2W6DlK716Rf9ACfnZDIN9urvewiRspVH7MgCNTz7RN c1+ZlYK8w0X0IGMl/55ve9Gyl77LB9Aqgggrhm5U= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279037; bh=QszQPZXYcFkSBsQQnLZxtmc59qcfJEbtosKMiFwaW9Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=llcfmHSayx1GclAFdkF/XUQBPsVWGfMs8rmH9480QJwCQ6wgRKcSUH6ehg2bUVOmF sn9K7c/2TbEerKNgecNckBmZ2W6DlK716Rf9ACfnZDIN9urvewiRspVH7MgCNTz7RN c1+ZlYK8w0X0IGMl/55ve9Gyl77LB9Aqgggrhm5U= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:45 +0200 Message-Id: <20180629132954.24269-12-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 11/20] intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irq X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement virtualization extensions in the gic_acknowledge_irq() function. This function changes the state of the highest priority IRQ from pending to active. When the current CPU is a vCPU, modifying the state of an IRQ modifies the corresponding LR entry. However if we clear the pending flag before setting the active one, we lose track of the LR entry as it becomes invalid. The next call to gic_get_lr_entry() will fail. To overcome this issue, we call gic_activate_irq() before gic_clear_pending(). This does not change the general behaviour of gic_acknowledge_irq. We also move the SGI case in gic_clear_pending_sgi() to enhance code readability as the virtualization extensions support adds a if-else level. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 52 ++++++++++++++++++++++++++++++----------------- 1 file changed, 33 insertions(+), 19 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index d61c2dd557..a7577ac073 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -366,17 +366,44 @@ static void gic_drop_prio(GICState *s, int cpu, int g= roup) s->running_priority[cpu] =3D gic_get_prio_from_apr_bits(s, cpu); } =20 +static inline uint32_t gic_clear_pending_sgi(GICState *s, int irq, int cpu) +{ + int src; + uint32_t ret; + + if (!gic_is_vcpu(cpu)) { + /* Lookup the source CPU for the SGI and clear this in the + * sgi_pending map. Return the src and clear the overall pending + * state on this CPU if the SGI is not pending from any CPUs. + */ + assert(s->sgi_pending[irq][cpu] !=3D 0); + src =3D ctz32(s->sgi_pending[irq][cpu]); + s->sgi_pending[irq][cpu] &=3D ~(1 << src); + if (s->sgi_pending[irq][cpu] =3D=3D 0) { + gic_clear_pending(s, irq, cpu); + } + ret =3D irq | ((src & 0x7) << 10); + } else { + uint32_t *lr_entry =3D gic_get_lr_entry(s, irq, cpu); + src =3D GICH_LR_CPUID(*lr_entry); + + gic_clear_pending(s, irq, cpu); + ret =3D irq | (src << 10); + } + + return ret; +} + uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) { - int ret, irq, src; - int cm =3D 1 << cpu; + int ret, irq; =20 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately * for the case where this GIC supports grouping and the pending inter= rupt * is in the wrong group. */ irq =3D gic_get_current_pending_irq(s, cpu, attrs); - trace_gic_acknowledge_irq(cpu, irq); + trace_gic_acknowledge_irq(gic_get_vcpu_real_id(cpu), irq); =20 if (irq >=3D GIC_MAXIRQ) { DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); @@ -388,6 +415,8 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemT= xAttrs attrs) return 1023; } =20 + gic_activate_irq(s, cpu, irq); + if (s->revision =3D=3D REV_11MPCORE) { /* Clear pending flags for both level and edge triggered interrupt= s. * Level triggered IRQs will be reasserted once they become inacti= ve. @@ -396,28 +425,13 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, Me= mTxAttrs attrs) ret =3D irq; } else { if (irq < GIC_NR_SGIS) { - /* Lookup the source CPU for the SGI and clear this in the - * sgi_pending map. Return the src and clear the overall pend= ing - * state on this CPU if the SGI is not pending from any CPUs. - */ - assert(s->sgi_pending[irq][cpu] !=3D 0); - src =3D ctz32(s->sgi_pending[irq][cpu]); - s->sgi_pending[irq][cpu] &=3D ~(1 << src); - if (s->sgi_pending[irq][cpu] =3D=3D 0) { - gic_clear_pending(s, irq, cpu); - } - ret =3D irq | ((src & 0x7) << 10); + ret =3D gic_clear_pending_sgi(s, irq, cpu); } else { - /* Clear pending state for both level and edge triggered - * interrupts. (level triggered interrupts with an active line - * remain pending, see gic_test_pending) - */ gic_clear_pending(s, irq, cpu); ret =3D irq; } } =20 - gic_activate_irq(s, cpu, irq); gic_update(s); DPRINTF("ACK %d\n", irq); return ret; --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530279274375348.9128740181143; Fri, 29 Jun 2018 06:34:34 -0700 (PDT) Received: from localhost ([::1]:42171 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtXi-0001PI-Kn for importer@patchew.org; Fri, 29 Jun 2018 09:34:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38108) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtUH-0007hZ-Bf for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:30:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYtUC-0007H2-6E for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:30:57 -0400 Received: from greensocs.com ([193.104.36.180]:58619) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtU2-0006mY-Ar; Fri, 29 Jun 2018 09:30:42 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 29D8B4434B1; Fri, 29 Jun 2018 15:30:39 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LXasRcEDes06; Fri, 29 Jun 2018 15:30:38 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 4DF1A4434B7; Fri, 29 Jun 2018 15:30:38 +0200 (CEST) Received: from michell-laptop.hive.antfield.fr (LFbn-LYO-1-488-36.w2-7.abo.wanadoo.fr [2.7.77.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id B1CF94434B5; Fri, 29 Jun 2018 15:30:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279039; bh=IZnUnSWK2zcIP/cCVEwvOa9/RpI3I0kZxu9SuWElsBg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=jIFblKF/w7O6RIcU8bvupawQdby4wXeYSo+zEbpwtXPG0r/crbeH5DhZ07ffaW8kD yO0TOJzIIaHWPKiGeVY4bQ7m9a3XpN/1OLlusI+yNReMnsCN6rMRHGFJnIU83yJLkB yEVNY4O4U/rnKqgkgASPOp57kTIuaHcH2n2NevBc= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=etdF7Tgs; dkim=pass (1024-bit key) header.d=greensocs.com header.b=Qgk/5YD6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279038; bh=IZnUnSWK2zcIP/cCVEwvOa9/RpI3I0kZxu9SuWElsBg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=etdF7Tgs+aKEJ3GVnCSIc3xgtWzGyJex38CPD22aQu0JeDMmGV+1R4vp1tTESqFtl MDDfy5Qfmz0BziNUPewZyKKDlOn2w1zcbEg2lcX/UtcAY1lKRe5qxjoSxzcUjTiyEu +DUXtz1/YuXtCjF6446t2G24RqJ4b6HVEtkFgm3w= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279037; bh=IZnUnSWK2zcIP/cCVEwvOa9/RpI3I0kZxu9SuWElsBg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Qgk/5YD6aU+Z8wIovQ/EMbuF0lr81O1cErL08OyYjGNZh6nFFwFOUfYk9U+n5UB5E fw/GFDUB/m2eP1QadlusO3FwX4on2t3/uOlS4YNsZ/K9AEV7DNt5tCTuduZZek8WfI uJWpcxLf1Uzs8HwuaVAE+CbuB7S26YteG/F1rnZk= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:46 +0200 Message-Id: <20180629132954.24269-13-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 12/20] intc/arm_gic: Implement virtualization extensions in gic_complete_irq X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 3 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement virtualization extensions in the gic_complete_irq() function. When a guest tries to end an IRQ that does not exist in the LRs, the EOICount field of the virtual interface HCR register is incremented by one, and the request is ignored. Signed-off-by: Luc Michel --- hw/intc/arm_gic.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index a7577ac073..434dc9c7b2 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -605,6 +605,15 @@ static void gic_complete_irq(GICState *s, int cpu, int= irq, MemTxAttrs attrs) int group; =20 DPRINTF("EOI %d\n", irq); + if (gic_is_vcpu(cpu) && !gic_virq_is_valid(s, irq, cpu)) { + /* This vIRQ does not have a valid LR entry. Increment EOICount and + * ignore the write. + */ + int rcpu =3D gic_get_vcpu_real_id(cpu); + s->h_hcr[rcpu] +=3D 1 << R_GICH_HCR_EOICount_SHIFT; + return; + } + if (irq >=3D s->num_irq) { /* This handles two cases: * 1. If software writes the ID of a spurious interrupt [ie 1023] --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530279317302728.3463300887441; Fri, 29 Jun 2018 06:35:17 -0700 (PDT) Received: from localhost ([::1]:42173 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtYS-0002B5-Ht for importer@patchew.org; Fri, 29 Jun 2018 09:35:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38102) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtUH-0007hU-9N for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:30:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYtUC-0007Hq-Ea for qemu-devel@nongnu.org; Fri, 29 Jun 2018 09:30:57 -0400 Received: from greensocs.com ([193.104.36.180]:58623) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtU2-0006nX-Hs; Fri, 29 Jun 2018 09:30:43 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id BA7344434B7; Fri, 29 Jun 2018 15:30:39 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JcMrYS5yfi6j; Fri, 29 Jun 2018 15:30:38 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id CF6BF4434B9; Fri, 29 Jun 2018 15:30:38 +0200 (CEST) Received: from michell-laptop.hive.antfield.fr (LFbn-LYO-1-488-36.w2-7.abo.wanadoo.fr [2.7.77.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 517294434B5; Fri, 29 Jun 2018 15:30:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279039; bh=RnCM0QeyK4Th8xyUB80B9wnawptYOn6aaOfHMd/1gNk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=4xl5Y+se5/78pu6uPvJDDGp76O718pu5ZiOntE/a58zBI6zrZOfY2ehUFqzFqGEp4 NMmpKMfCqOzd0buNfrEreBhQuIG19zeNgx8erEAJ7UlV38BB3+aM+/KhxSQ2/CXyN9 zeDpKXybO8dv2W3eIo9ntp00dqLy9dmVTUNFiUBE= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=YERw6Skh; dkim=pass (1024-bit key) header.d=greensocs.com header.b=YERw6Skh DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279038; bh=RnCM0QeyK4Th8xyUB80B9wnawptYOn6aaOfHMd/1gNk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=YERw6SkhewKOg/dS//cpnes60/pJiZ6xK0MZdu31BRQNCA/Fsn4QPZxdHpnfwCp83 /mCICKOZqJckWQY7NzKw/4fy+GRnVo1tOCEg0PMSf3CfymXsj4WHmh96/mhAoMIIz9 kLXSimQ1vdlssSVdRiq7FQLgOsYTYoJqzMlpbm18= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279038; bh=RnCM0QeyK4Th8xyUB80B9wnawptYOn6aaOfHMd/1gNk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=YERw6SkhewKOg/dS//cpnes60/pJiZ6xK0MZdu31BRQNCA/Fsn4QPZxdHpnfwCp83 /mCICKOZqJckWQY7NzKw/4fy+GRnVo1tOCEg0PMSf3CfymXsj4WHmh96/mhAoMIIz9 kLXSimQ1vdlssSVdRiq7FQLgOsYTYoJqzMlpbm18= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:47 +0200 Message-Id: <20180629132954.24269-14-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 13/20] intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement virtualization extensions in the gic_cpu_read() and gic_cpu_write() functions. Those are the last bits missing to fully support virtualization extensions in the CPU interface path. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 434dc9c7b2..2b1fa280eb 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1336,9 +1336,12 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu= , int offset, case 0xd0: case 0xd4: case 0xd8: case 0xdc: { int regno =3D (offset - 0xd0) / 4; + int nr_aprs =3D gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; =20 - if (regno >=3D GIC_NR_APRS || s->revision !=3D 2) { + if (regno >=3D nr_aprs || s->revision !=3D 2) { *data =3D 0; + } else if (gic_is_vcpu(cpu)) { + *data =3D s->h_apr[gic_get_vcpu_real_id(cpu)]; } else if (gic_cpu_ns_access(s, cpu, attrs)) { /* NS view of GICC_APR is the top half of GIC_NSAPR */ *data =3D gic_apr_ns_view(s, regno, cpu); @@ -1352,7 +1355,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu,= int offset, int regno =3D (offset - 0xe0) / 4; =20 if (regno >=3D GIC_NR_APRS || s->revision !=3D 2 || !gic_has_group= s(s) || - gic_cpu_ns_access(s, cpu, attrs)) { + gic_cpu_ns_access(s, cpu, attrs) || gic_is_vcpu(cpu)) { *data =3D 0; } else { *data =3D s->nsapr[regno][cpu]; @@ -1387,7 +1390,8 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu= , int offset, s->abpr[cpu] =3D MAX(value & 0x7, GIC_MIN_ABPR); } } else { - s->bpr[cpu] =3D MAX(value & 0x7, GIC_MIN_BPR); + int min_bpr =3D gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_= BPR; + s->bpr[cpu] =3D MAX(value & 0x7, min_bpr); } break; case 0x10: /* End Of Interrupt */ @@ -1404,11 +1408,14 @@ static MemTxResult gic_cpu_write(GICState *s, int c= pu, int offset, case 0xd0: case 0xd4: case 0xd8: case 0xdc: { int regno =3D (offset - 0xd0) / 4; + int nr_aprs =3D gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; =20 - if (regno >=3D GIC_NR_APRS || s->revision !=3D 2) { + if (regno >=3D nr_aprs || s->revision !=3D 2) { return MEMTX_OK; } - if (gic_cpu_ns_access(s, cpu, attrs)) { + if (gic_is_vcpu(cpu)) { + s->h_apr[gic_get_vcpu_real_id(cpu)] =3D value; + } else if (gic_cpu_ns_access(s, cpu, attrs)) { /* NS view of GICC_APR is the top half of GIC_NSAPR */ gic_apr_write_ns_view(s, regno, cpu, value); } else { @@ -1423,6 +1430,9 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu= , int offset, if (regno >=3D GIC_NR_APRS || s->revision !=3D 2) { return MEMTX_OK; } + if (gic_is_vcpu(cpu)) { + return MEMTX_OK; + } if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { return MEMTX_OK; } --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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b=YBFeVsEYmdoAp75dxdQRN6tv1MbHuF0SovfzQLxAkosNhMR9oFmKqYQptl+micFXY pg9+tAdbCalNiYnm6hd2ejhlwuMj7tkz/Ent0OS7XTGKsUqcdzCbIdqOBUlsost9o8 QNlJkgOCSi6+ujLuKdFQgg0x8l5y2BqP0kj4Fv4E= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=KcgyqTr4; dkim=pass (1024-bit key) header.d=greensocs.com header.b=KcgyqTr4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279039; bh=PIhnC8PVzlvZ+ddBfg9Qq1hRX0bI4MURM++5ytkZF98=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=KcgyqTr44Gymd6XuT+qQ3tEpFb6ZgGDe4OeTQpOJLTTksDD63ThvFV8S0VvYlDrVl +YtgR7jEq8YhXz1p3WvVlK6g27ySqKiY71rqPfvOYXRtitMi0d7okepMcMOXTeu6ca 4HkLwnJYYQEUM8YygTQye25fAnzJpLJjdN9aqbkU= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279039; bh=PIhnC8PVzlvZ+ddBfg9Qq1hRX0bI4MURM++5ytkZF98=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=KcgyqTr44Gymd6XuT+qQ3tEpFb6ZgGDe4OeTQpOJLTTksDD63ThvFV8S0VvYlDrVl +YtgR7jEq8YhXz1p3WvVlK6g27ySqKiY71rqPfvOYXRtitMi0d7okepMcMOXTeu6ca 4HkLwnJYYQEUM8YygTQye25fAnzJpLJjdN9aqbkU= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:48 +0200 Message-Id: <20180629132954.24269-15-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 14/20] intc/arm_gic: Wire the vCPU interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the read/write functions to handle accesses to the vCPU interface. Those accesses are forwarded to the real CPU interface, with the CPU id being converted to the corresponding vCPU id (vCPU id =3D CPU id + GIC_NCPU). As for the CPU interface, we create a base region for the vCPU interface that fetches the current vCPU id using the current_cpu global variable, and one mirror region per vCPU which maps to that specific vCPU id. This is required by the GIC architecture specification. Signed-off-by: Luc Michel --- hw/intc/arm_gic.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 2b1fa280eb..9bbd544a5c 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1488,6 +1488,46 @@ static MemTxResult gic_do_cpu_write(void *opaque, hw= addr addr, GICState *s =3D *backref; int id =3D (backref - s->backref); return gic_cpu_write(s, id, addr, value, attrs); + +} + +static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *= data, + unsigned size, MemTxAttrs attrs) +{ + GICState *s =3D (GICState *)opaque; + + return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs); +} + +static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + GICState *s =3D (GICState *)opaque; + + return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs); +} + +static MemTxResult gic_do_vcpu_read(void *opaque, hwaddr addr, uint64_t *d= ata, + unsigned size, MemTxAttrs attrs) +{ + GICState **backref =3D (GICState **)opaque; + GICState *s =3D *backref; + int id =3D (backref - s->backref); + + return gic_cpu_read(s, id + GIC_NCPU, addr, data, attrs); +} + +static MemTxResult gic_do_vcpu_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + GICState **backref =3D (GICState **)opaque; + GICState *s =3D *backref; + int id =3D (backref - s->backref); + + return gic_cpu_write(s, id + GIC_NCPU, addr, value, attrs); + } =20 static const MemoryRegionOps gic_ops[2] =3D { @@ -1509,6 +1549,25 @@ static const MemoryRegionOps gic_cpu_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +static const MemoryRegionOps gic_virt_ops[2] =3D { + { + .read_with_attrs =3D NULL, + .write_with_attrs =3D NULL, + .endianness =3D DEVICE_NATIVE_ENDIAN, + }, + { + .read_with_attrs =3D gic_thisvcpu_read, + .write_with_attrs =3D gic_thisvcpu_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + } +}; + +static const MemoryRegionOps gic_vcpu_ops =3D { + .read_with_attrs =3D gic_do_vcpu_read, + .write_with_attrs =3D gic_do_vcpu_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + static void arm_gic_realize(DeviceState *dev, Error **errp) { /* Device instance realize function for the GIC sysbus device */ @@ -1531,7 +1590,7 @@ static void arm_gic_realize(DeviceState *dev, Error *= *errp) } =20 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ - gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, NULL); + gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, gic_virt_ops); =20 /* Extra core-specific regions for the CPU interfaces. This is * necessary for "franken-GIC" implementations, for example on @@ -1547,6 +1606,16 @@ static void arm_gic_realize(DeviceState *dev, Error = **errp) &s->backref[i], "gic_cpu", 0x100); sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); } + + if (s->virt_extn) { + for (i =3D 0; i < s->num_cpu; i++) { + memory_region_init_io(&s->vcpuiomem[i + 1], OBJECT(s), + &gic_vcpu_ops, &s->backref[i], + "gic_vcpu", 0x2000); + sysbus_init_mmio(sbd, &s->vcpuiomem[i + 1]); + } + } + } =20 static void arm_gic_class_init(ObjectClass *klass, void *data) --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530280219655100.82954740067669; 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dkim=pass (1024-bit key) header.d=greensocs.com header.b=3ucvNkp0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279039; bh=2fqRjrhfWPHXK4V2w3JDrR9pnrx5hmv8Gk3+ejSLdqM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=3ucvNkp0Za+iCc673B9NBTbvg39SFMs5dueGSUmmlXdh0EAj94aZrKJvqJWmWy66D ZgSnlPrOL5F04ylLZG5zN10pdRlHWGeGXoN10grDhrGnYjjXBzXbVa1B8XxgQFnPvF VSXjL3WuMiDnClew1PpJWK8zkOOT2CRR9bHPM9cI= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279039; bh=2fqRjrhfWPHXK4V2w3JDrR9pnrx5hmv8Gk3+ejSLdqM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=3ucvNkp0Za+iCc673B9NBTbvg39SFMs5dueGSUmmlXdh0EAj94aZrKJvqJWmWy66D ZgSnlPrOL5F04ylLZG5zN10pdRlHWGeGXoN10grDhrGnYjjXBzXbVa1B8XxgQFnPvF VSXjL3WuMiDnClew1PpJWK8zkOOT2CRR9bHPM9cI= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:49 +0200 Message-Id: <20180629132954.24269-16-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 15/20] intc/arm_gic: Implement the virtual interface registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement the read and write functions for the virtual interface of the virtualization extensions in the GICv2. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 161 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 159 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 9bbd544a5c..a29042f291 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1530,6 +1530,163 @@ static MemTxResult gic_do_vcpu_write(void *opaque, = hwaddr addr, =20 } =20 +static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start) +{ + int lr_idx; + uint32_t ret =3D 0; + + for (lr_idx =3D lr_start; lr_idx < s->num_lrs; lr_idx++) { + uint32_t *entry =3D &s->h_lr[lr_idx][cpu]; + ret =3D deposit32(ret, lr_idx - lr_start, 1, + gic_lr_entry_is_eoi(*entry)); + } + + return ret; +} + +static uint32_t gic_compute_elrsr(GICState *s, int cpu, int lr_start) +{ + int lr_idx; + uint32_t ret =3D 0; + + for (lr_idx =3D lr_start; lr_idx < s->num_lrs; lr_idx++) { + uint32_t *entry =3D &s->h_lr[lr_idx][cpu]; + ret =3D deposit32(ret, lr_idx - lr_start, 1, + gic_lr_entry_is_free(*entry)); + } + + return ret; +} + +static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs) +{ + int vcpu =3D gic_get_current_vcpu(s); + uint32_t ctlr; + uint32_t abpr; + uint32_t bpr; + uint32_t prio_mask; + + ctlr =3D FIELD_EX32(value, GICH_VMCR, VMCCtlr); + abpr =3D FIELD_EX32(value, GICH_VMCR, VMABP); + bpr =3D FIELD_EX32(value, GICH_VMCR, VMBP); + prio_mask =3D FIELD_EX32(value, GICH_VMCR, VMPriMask) << 3; + + gic_set_cpu_control(s, vcpu, ctlr, attrs); + s->abpr[vcpu] =3D MAX(abpr, GIC_VIRT_MIN_ABPR); + s->bpr[vcpu] =3D MAX(bpr, GIC_VIRT_MIN_BPR); + gic_set_priority_mask(s, vcpu, prio_mask, attrs); +} + +static MemTxResult gic_hyp_read(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) +{ + GICState *s =3D ARM_GIC(opaque); + int cpu =3D gic_get_current_cpu(s); + int vcpu =3D gic_get_current_vcpu(s); + + switch (addr) { + case A_GICH_HCR: /* Hypervisor Control */ + *data =3D s->h_hcr[cpu]; + break; + + case A_GICH_VTR: /* VGIC Type */ + *data =3D FIELD_DP32(0, GICH_VTR, ListRegs, s->num_lrs - 1); + *data =3D FIELD_DP32(*data, GICH_VTR, PREbits, + GIC_VIRT_MAX_GROUP_PRIO_BITS - 1); + *data =3D FIELD_DP32(*data, GICH_VTR, PRIbits, + (7 - GIC_VIRT_MIN_BPR) - 1); + break; + + case A_GICH_VMCR: /* Virtual Machine Control */ + *data =3D FIELD_DP32(0, GICH_VMCR, VMCCtlr, + extract32(s->cpu_ctlr[vcpu], 0, 10)); + *data =3D FIELD_DP32(*data, GICH_VMCR, VMABP, s->abpr[vcpu]); + *data =3D FIELD_DP32(*data, GICH_VMCR, VMBP, s->bpr[vcpu]); + *data =3D FIELD_DP32(*data, GICH_VMCR, VMPriMask, + extract32(s->priority_mask[vcpu], 3, 5)); + break; + + case A_GICH_MISR: /* Maintenance Interrupt Status */ + *data =3D s->h_misr[cpu]; + break; + + case A_GICH_EISR0: /* End of Interrupt Status 0 and 1 */ + case A_GICH_EISR1: + *data =3D gic_compute_eisr(s, cpu, (addr - A_GICH_EISR0) * 8); + break; + + case A_GICH_ELRSR0: /* Empty List Status 0 and 1 */ + case A_GICH_ELRSR1: + *data =3D gic_compute_elrsr(s, cpu, (addr - A_GICH_ELRSR0) * 8); + break; + + case A_GICH_APR: /* Active Priorities */ + *data =3D s->h_apr[cpu]; + break; + + case A_GICH_LR0 ... A_GICH_LR63: /* List Registers */ + { + int lr_idx =3D (addr - A_GICH_LR0) / 4; + + if (lr_idx > s->num_lrs) { + *data =3D 0; + } else { + *data =3D s->h_lr[lr_idx][cpu]; + } + break; + } + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "gic_hyp_read: Bad offset %" HWADDR_PRIx "\n", addr); + return MEMTX_OK; + } + + return MEMTX_OK; +} + +static MemTxResult gic_hyp_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size, MemTxAttrs attrs) +{ + GICState *s =3D ARM_GIC(opaque); + int cpu =3D gic_get_current_cpu(s); + int vcpu =3D gic_get_current_vcpu(s); + + switch (addr) { + case A_GICH_HCR: /* Hypervisor Control */ + s->h_hcr[cpu] =3D value & GICH_HCR_MASK; + break; + + case A_GICH_VMCR: /* Virtual Machine Control */ + gic_vmcr_write(s, value, attrs); + break; + + case A_GICH_APR: /* Active Priorities */ + s->h_apr[cpu] =3D value; + s->running_priority[vcpu] =3D gic_get_prio_from_apr_bits(s, vcpu); + break; + + case A_GICH_LR0 ... A_GICH_LR63: /* List Registers */ + { + int lr_idx =3D (addr - A_GICH_LR0) / 4; + + if (lr_idx > s->num_lrs) { + return MEMTX_OK; + } + + s->h_lr[lr_idx][cpu] =3D value & GICH_LR_MASK; + break; + } + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "gic_hyp_write: Bad offset %" HWADDR_PRIx "\n", addr= ); + return MEMTX_OK; + } + + return MEMTX_OK; +} + static const MemoryRegionOps gic_ops[2] =3D { { .read_with_attrs =3D gic_dist_read, @@ -1551,8 +1708,8 @@ static const MemoryRegionOps gic_cpu_ops =3D { =20 static const MemoryRegionOps gic_virt_ops[2] =3D { { - .read_with_attrs =3D NULL, - .write_with_attrs =3D NULL, + .read_with_attrs =3D gic_hyp_read, + .write_with_attrs =3D gic_hyp_write, .endianness =3D DEVICE_NATIVE_ENDIAN, }, { --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Add the gic_update_virt() function to update the vCPU interface states and raise vIRQ and vFIQ as needed. This commit renames gic_update() to gic_update_internal() and generalizes it to handle both cases, with a `virt' parameter to track whether we are updating the CPU or vCPU interfaces. The main difference between CPU and vCPU is the way we select the best IRQ. This part has been split into the gic_get_best_(v)irq functions. For the virt case, the LRs are iterated to find the best candidate. Signed-off-by: Luc Michel --- hw/intc/arm_gic.c | 170 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 130 insertions(+), 40 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index a29042f291..a3ff4b89d1 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -79,74 +79,143 @@ static inline bool gic_cpu_ns_access(GICState *s, int = cpu, MemTxAttrs attrs) return !gic_is_vcpu(cpu) && s->security_extn && !attrs.secure; } =20 +static inline void gic_get_best_irq(GICState *s, int cpu, + int *best_irq, int *best_prio, int *gr= oup) +{ + int irq; + int cm =3D 1 << cpu; + + *best_irq =3D 1023; + *best_prio =3D 0x100; + + for (irq =3D 0; irq < s->num_irq; irq++) { + if (GIC_DIST_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm)= && + (!GIC_DIST_TEST_ACTIVE(irq, cm)) && + (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) { + if (GIC_DIST_GET_PRIORITY(irq, cpu) < *best_prio) { + *best_prio =3D GIC_DIST_GET_PRIORITY(irq, cpu); + *best_irq =3D irq; + } + } + } + + if (*best_irq < 1023) { + *group =3D GIC_DIST_TEST_GROUP(*best_irq, cm); + } +} + +static inline void gic_get_best_virq(GICState *s, int cpu, + int *best_irq, int *best_prio, int *g= roup) +{ + int lr_idx =3D 0; + + *best_irq =3D 1023; + *best_prio =3D 0x100; + + for (lr_idx =3D 0; lr_idx < s->num_lrs; lr_idx++) { + uint32_t lr_entry =3D s->h_lr[lr_idx][cpu]; + int state =3D GICH_LR_STATE(lr_entry); + + if (state =3D=3D GICH_LR_STATE_PENDING) { + int prio =3D GICH_LR_PRIORITY(lr_entry); + + if (prio < *best_prio) { + *best_prio =3D prio; + *best_irq =3D GICH_LR_VIRT_ID(lr_entry); + *group =3D GICH_LR_GROUP(lr_entry); + } + } + } +} + +/* Return true if IRQ signaling is enabled: + * - !virt -> from the distributor to the CPU interfaces, + * for the given group mask, + * - virt -> from the given virtual interface to the CPU virtual interf= ace. + */ +static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool vi= rt, + int group_mask) +{ + return (virt && (s->h_hcr[cpu] & R_GICH_HCR_EN_MASK)) + || (!virt && (s->ctlr & group_mask)); +} + /* TODO: Many places that call this routine could be optimized. */ /* Update interrupt status after enabled or pending bits have been changed= . */ -static void gic_update(GICState *s) +static inline void gic_update_internal(GICState *s, bool virt) { int best_irq; int best_prio; - int irq; int irq_level, fiq_level; - int cpu; - int cm; + int cpu, cpu_iface; + int group =3D 0; + qemu_irq *irq_lines =3D virt ? s->parent_virq : s->parent_irq; + qemu_irq *fiq_lines =3D virt ? s->parent_vfiq : s->parent_fiq; =20 for (cpu =3D 0; cpu < s->num_cpu; cpu++) { - cm =3D 1 << cpu; - s->current_pending[cpu] =3D 1023; - if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) - || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1= ))) { - qemu_irq_lower(s->parent_irq[cpu]); - qemu_irq_lower(s->parent_fiq[cpu]); + cpu_iface =3D virt ? (cpu + GIC_NCPU) : cpu; + + s->current_pending[cpu_iface] =3D 1023; + if (!gic_irq_signaling_enabled(s, cpu, virt, + GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GR= P1) + || !(s->cpu_ctlr[cpu_iface] & + (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { + qemu_irq_lower(irq_lines[cpu]); + qemu_irq_lower(fiq_lines[cpu]); continue; } - best_prio =3D 0x100; - best_irq =3D 1023; - for (irq =3D 0; irq < s->num_irq; irq++) { - if (GIC_DIST_TEST_ENABLED(irq, cm) && - gic_test_pending(s, irq, cm) && - (!GIC_DIST_TEST_ACTIVE(irq, cm)) && - (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) { - if (GIC_DIST_GET_PRIORITY(irq, cpu) < best_prio) { - best_prio =3D GIC_DIST_GET_PRIORITY(irq, cpu); - best_irq =3D irq; - } - } + + if (virt) { + gic_get_best_virq(s, cpu, &best_irq, &best_prio, &group); + } else { + gic_get_best_irq(s, cpu, &best_irq, &best_prio, &group); } =20 if (best_irq !=3D 1023) { trace_gic_update_bestirq(cpu, best_irq, best_prio, - s->priority_mask[cpu], s->running_priority[cpu]); + s->priority_mask[cpu_iface], s->running_priority[cpu_iface= ]); } =20 irq_level =3D fiq_level =3D 0; =20 - if (best_prio < s->priority_mask[cpu]) { - s->current_pending[cpu] =3D best_irq; - if (best_prio < s->running_priority[cpu]) { - int group =3D GIC_DIST_TEST_GROUP(best_irq, cm); - - if (extract32(s->ctlr, group, 1) && - extract32(s->cpu_ctlr[cpu], group, 1)) { - if (group =3D=3D 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ= _EN) { + if (best_prio < s->priority_mask[cpu_iface]) { + s->current_pending[cpu_iface] =3D best_irq; + if (best_prio < s->running_priority[cpu_iface]) { + if (gic_irq_signaling_enabled(s, cpu, virt, 1 << group) && + extract32(s->cpu_ctlr[cpu_iface], group, 1)) { + if (group =3D=3D 0 && + s->cpu_ctlr[cpu_iface] & GICC_CTLR_FIQ_EN) { DPRINTF("Raised pending FIQ %d (cpu %d)\n", - best_irq, cpu); + best_irq, cpu_iface); fiq_level =3D 1; - trace_gic_update_set_irq(cpu, "fiq", fiq_level); + trace_gic_update_set_irq(cpu, virt ? "vfiq" : "fiq= ", + fiq_level); } else { DPRINTF("Raised pending IRQ %d (cpu %d)\n", - best_irq, cpu); + best_irq, cpu_iface); irq_level =3D 1; - trace_gic_update_set_irq(cpu, "irq", irq_level); + trace_gic_update_set_irq(cpu, virt ? "virq" : "irq= ", + irq_level); } } } } =20 - qemu_set_irq(s->parent_irq[cpu], irq_level); - qemu_set_irq(s->parent_fiq[cpu], fiq_level); + qemu_set_irq(irq_lines[cpu], irq_level); + qemu_set_irq(fiq_lines[cpu], fiq_level); } } =20 +static void gic_update(GICState *s) +{ + gic_update_internal(s, false); +} + +static void gic_update_virt(GICState *s) +{ + gic_update_internal(s, true); +} + static void gic_set_irq_11mpcore(GICState *s, int irq, int level, int cm, int target) { @@ -432,7 +501,11 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, Mem= TxAttrs attrs) } } =20 - gic_update(s); + if (gic_is_vcpu(cpu)) { + gic_update_virt(s); + } else { + gic_update(s); + } DPRINTF("ACK %d\n", irq); return ret; } @@ -611,6 +684,11 @@ static void gic_complete_irq(GICState *s, int cpu, int= irq, MemTxAttrs attrs) */ int rcpu =3D gic_get_vcpu_real_id(cpu); s->h_hcr[rcpu] +=3D 1 << R_GICH_HCR_EOICount_SHIFT; + + /* Update the virtual interface in case a maintenance interrupt sh= ould + * be raised. + */ + gic_update_virt(s); return; } =20 @@ -658,7 +736,12 @@ static void gic_complete_irq(GICState *s, int cpu, int= irq, MemTxAttrs attrs) if (!gic_eoi_split(s, cpu, attrs)) { gic_clear_active(s, irq, cpu); } - gic_update(s); + + if (gic_is_vcpu(cpu)) { + gic_update_virt(s); + } else { + gic_update(s); + } } =20 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs att= rs) @@ -1448,7 +1531,13 @@ static MemTxResult gic_cpu_write(GICState *s, int cp= u, int offset, "gic_cpu_write: Bad offset %x\n", (int)offset); return MEMTX_OK; } - gic_update(s); + + if (gic_is_vcpu(cpu)) { + gic_update_virt(s); + } else { + gic_update(s); + } + return MEMTX_OK; } =20 @@ -1684,6 +1773,7 @@ static MemTxResult gic_hyp_write(void *opaque, hwaddr= addr, uint64_t value, return MEMTX_OK; } =20 + gic_update_virt(s); return MEMTX_OK; } =20 --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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b=RjTMQhog3E7EN8vBhke1r2HSa3kU57ldblI3vhdwCUj7XpFIwrNHTQ76WYhORA+ty x0X0kq3j+2HMInVHIceE7P8xCLWSWcU/nj3izBAFkYpRMiTk3XcVMYn81sN7ud2MPH OkXEIKtbuWrXZvqxMjbG3M9xEd0JKyS0LnCFpSgg= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=4EDH6Ht3; dkim=pass (1024-bit key) header.d=greensocs.com header.b=4EDH6Ht3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279041; bh=Tcn8vA+NQ6UjfzqAXfFdIrJgo/nDdngNZUAvIGiaw7s=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=4EDH6Ht3BsXdO8vC2TiVt+BN6XLtFjec0gsJt6fJvZV4m2DJYNkqYRwy784cEU8Ci SDikZYr6my5GAdEdeTTz+VcoonmTkzsINiVnleF8DvwUv1bcaeCIKf8EnnAewVWQUA X0CEfrPW7VhmManBLtmiYGpD7K6XfagZqsW7MbQs= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279041; bh=Tcn8vA+NQ6UjfzqAXfFdIrJgo/nDdngNZUAvIGiaw7s=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=4EDH6Ht3BsXdO8vC2TiVt+BN6XLtFjec0gsJt6fJvZV4m2DJYNkqYRwy784cEU8Ci SDikZYr6my5GAdEdeTTz+VcoonmTkzsINiVnleF8DvwUv1bcaeCIKf8EnnAewVWQUA X0CEfrPW7VhmManBLtmiYGpD7K6XfagZqsW7MbQs= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:51 +0200 Message-Id: <20180629132954.24269-18-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 17/20] intc/arm_gic: Implement maintenance interrupt generation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement the maintenance interrupt generation that is part of the GICv2 virtualization extensions. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index a3ff4b89d1..10300e9b4c 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -206,6 +206,94 @@ static inline void gic_update_internal(GICState *s, bo= ol virt) } } =20 +static inline void gic_extract_lr_info(GICState *s, int cpu, + int *num_eoi, int *num_valid, int *num_pen= ding) +{ + int lr_idx; + + *num_eoi =3D 0; + *num_valid =3D 0; + *num_pending =3D 0; + + for (lr_idx =3D 0; lr_idx < s->num_lrs; lr_idx++) { + uint32_t *entry =3D &s->h_lr[lr_idx][cpu]; + + if (gic_lr_entry_is_eoi(*entry)) { + (*num_eoi)++; + } + + if (GICH_LR_STATE(*entry) !=3D GICH_LR_STATE_INVALID) { + (*num_valid)++; + } + + if (GICH_LR_STATE(*entry) =3D=3D GICH_LR_STATE_PENDING) { + (*num_pending)++; + } + } +} + +static void gic_compute_misr(GICState *s, int cpu) +{ + int val; + int vcpu =3D cpu + GIC_NCPU; + + int num_eoi, num_valid, num_pending; + + gic_extract_lr_info(s, cpu, &num_eoi, &num_valid, &num_pending); + + /* EOI */ + val =3D (num_eoi !=3D 0); + s->h_misr[cpu] =3D FIELD_DP32(0, GICH_MISR, EOI, val); + + /* U: true if only 0 or 1 LR entry is valid */ + val =3D s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK && + (num_valid < 2); + s->h_misr[cpu] =3D FIELD_DP32(s->h_misr[cpu], GICH_MISR, U, val); + + /* LRENP: EOICount is not 0 */ + val =3D s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK && + ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) !=3D 0); + s->h_misr[cpu] =3D FIELD_DP32(s->h_misr[cpu], GICH_MISR, LRENP, val); + + /* NP: no pending interrupts */ + val =3D s->h_hcr[cpu] & R_GICH_HCR_NPIE_MASK && + (num_pending =3D=3D 0); + s->h_misr[cpu] =3D FIELD_DP32(s->h_misr[cpu], GICH_MISR, NP, val); + + /* VGrp0E: group0 virq signaling enabled */ + val =3D s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK && + (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0); + s->h_misr[cpu] =3D FIELD_DP32(s->h_misr[cpu], GICH_MISR, VGrp0E, val); + + /* VGrp0D: group0 virq signaling disabled */ + val =3D s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK && + !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0); + s->h_misr[cpu] =3D FIELD_DP32(s->h_misr[cpu], GICH_MISR, VGrp0D, val); + + /* VGrp1E: group1 virq signaling enabled */ + val =3D s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK && + (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1); + s->h_misr[cpu] =3D FIELD_DP32(s->h_misr[cpu], GICH_MISR, VGrp1E, val); + + /* VGrp1D: group1 virq signaling disabled */ + val =3D s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK && + !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1); + s->h_misr[cpu] =3D FIELD_DP32(s->h_misr[cpu], GICH_MISR, VGrp1D, val); +} + +static void gic_update_maintenance(GICState *s) +{ + int cpu =3D 0; + int maint_level; + + for (cpu =3D 0; cpu < s->num_cpu; cpu++) { + gic_compute_misr(s, cpu); + maint_level =3D (s->h_hcr[cpu] & R_GICH_HCR_EN_MASK) && s->h_misr[= cpu]; + + qemu_set_irq(s->maintenance_irq[cpu], maint_level); + } +} + static void gic_update(GICState *s) { gic_update_internal(s, false); @@ -214,6 +302,7 @@ static void gic_update(GICState *s) static void gic_update_virt(GICState *s) { gic_update_internal(s, true); + gic_update_maintenance(s); } =20 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530279505054357.85726082294116; Fri, 29 Jun 2018 06:38:25 -0700 (PDT) Received: from localhost ([::1]:42192 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYtbU-0005Ik-98 for importer@patchew.org; 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a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279041; bh=JXnfvnQvRli+fPXG5DPmVsRnNaeRyhVEbA5DGp3+TWo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=zF8hNKUMVarzSQ30Am/o4h0DucBAzby8CFYSAO1XAjvCbajGWQmrvYUUeG6aMBLVp 2PTH6+3lMceouK2RljBwQNECpMC78cHFi0A8+uv/v0ywa6+HtxqYdvEXZqc6/KjT+Q Vos3DvzbO0MDEqxFHdtLyejTjldIG0ppVDEeBnyk= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:52 +0200 Message-Id: <20180629132954.24269-19-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 18/20] intc/arm_gic: Improve traces X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 3 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add some traces to the ARM GIC to catch register accesses (distributor, (v)cpu interface and virtual interface), and to take into account virtualization extensions (print `vcpu` instead of `cpu` when needed). Also add some virtualization extensions specific traces: LR updating and maintenance IRQ generation. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 31 +++++++++++++++++++++++++------ hw/intc/trace-events | 12 ++++++++++-- 2 files changed, 35 insertions(+), 8 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 10300e9b4c..7d24348d96 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -172,8 +172,10 @@ static inline void gic_update_internal(GICState *s, bo= ol virt) } =20 if (best_irq !=3D 1023) { - trace_gic_update_bestirq(cpu, best_irq, best_prio, - s->priority_mask[cpu_iface], s->running_priority[cpu_iface= ]); + trace_gic_update_bestirq(virt ? "vcpu" : "cpu", cpu, + best_irq, best_prio, + s->priority_mask[cpu_iface], + s->running_priority[cpu_iface]); } =20 irq_level =3D fiq_level =3D 0; @@ -290,6 +292,7 @@ static void gic_update_maintenance(GICState *s) gic_compute_misr(s, cpu); maint_level =3D (s->h_hcr[cpu] & R_GICH_HCR_EN_MASK) && s->h_misr[= cpu]; =20 + trace_gic_update_maintenance_irq(cpu, maint_level); qemu_set_irq(s->maintenance_irq[cpu], maint_level); } } @@ -561,7 +564,8 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemT= xAttrs attrs) * is in the wrong group. */ irq =3D gic_get_current_pending_irq(s, cpu, attrs); - trace_gic_acknowledge_irq(gic_get_vcpu_real_id(cpu), irq); + trace_gic_acknowledge_irq(gic_is_vcpu(cpu) ? "vcpu" : "cpu", + gic_get_vcpu_real_id(cpu), irq); =20 if (irq >=3D GIC_MAXIRQ) { DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); @@ -1040,20 +1044,23 @@ static MemTxResult gic_dist_read(void *opaque, hwad= dr offset, uint64_t *data, switch (size) { case 1: *data =3D gic_dist_readb(opaque, offset, attrs); - return MEMTX_OK; + break; case 2: *data =3D gic_dist_readb(opaque, offset, attrs); *data |=3D gic_dist_readb(opaque, offset + 1, attrs) << 8; - return MEMTX_OK; + break; case 4: *data =3D gic_dist_readb(opaque, offset, attrs); *data |=3D gic_dist_readb(opaque, offset + 1, attrs) << 8; *data |=3D gic_dist_readb(opaque, offset + 2, attrs) << 16; *data |=3D gic_dist_readb(opaque, offset + 3, attrs) << 24; - return MEMTX_OK; + break; default: return MEMTX_ERROR; } + + trace_gic_dist_read(offset, size, *data); + return MEMTX_OK; } =20 static void gic_dist_writeb(void *opaque, hwaddr offset, @@ -1384,6 +1391,8 @@ static void gic_dist_writel(void *opaque, hwaddr offs= et, static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t da= ta, unsigned size, MemTxAttrs attrs) { + trace_gic_dist_write(offset, size, data); + switch (size) { case 1: gic_dist_writeb(opaque, offset, data, attrs); @@ -1540,12 +1549,18 @@ static MemTxResult gic_cpu_read(GICState *s, int cp= u, int offset, *data =3D 0; break; } + + trace_gic_cpu_read(gic_is_vcpu(cpu) ? "vcpu" : "cpu", + gic_get_vcpu_real_id(cpu), offset, *data); return MEMTX_OK; } =20 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value, MemTxAttrs attrs) { + trace_gic_cpu_write(gic_is_vcpu(cpu) ? "vcpu" : "cpu", + gic_get_vcpu_real_id(cpu), offset, value); + switch (offset) { case 0x00: /* Control */ gic_set_cpu_control(s, cpu, value, attrs); @@ -1820,6 +1835,7 @@ static MemTxResult gic_hyp_read(void *opaque, hwaddr = addr, uint64_t *data, return MEMTX_OK; } =20 + trace_gic_hyp_read(addr, *data); return MEMTX_OK; } =20 @@ -1830,6 +1846,8 @@ static MemTxResult gic_hyp_write(void *opaque, hwaddr= addr, uint64_t value, int cpu =3D gic_get_current_cpu(s); int vcpu =3D gic_get_current_vcpu(s); =20 + trace_gic_hyp_write(addr, value); + switch (addr) { case A_GICH_HCR: /* Hypervisor Control */ s->h_hcr[cpu] =3D value & GICH_HCR_MASK; @@ -1853,6 +1871,7 @@ static MemTxResult gic_hyp_write(void *opaque, hwaddr= addr, uint64_t value, } =20 s->h_lr[lr_idx][cpu] =3D value & GICH_LR_MASK; + trace_gic_lr_entry(cpu, lr_idx, s->h_lr[lr_idx][cpu]); break; } =20 diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 55e8c2570c..47fa4ad5c1 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -92,9 +92,17 @@ aspeed_vic_write(uint64_t offset, unsigned size, uint32_= t data) "To 0x%" PRIx64 gic_enable_irq(int irq) "irq %d enabled" gic_disable_irq(int irq) "irq %d disabled" gic_set_irq(int irq, int level, int cpumask, int target) "irq %d level %d = cpumask 0x%x target 0x%x" -gic_update_bestirq(int cpu, int irq, int prio, int priority_mask, int runn= ing_priority) "cpu %d irq %d priority %d cpu priority mask %d cpu running p= riority %d" +gic_update_bestirq(const char *s, int cpu, int irq, int prio, int priority= _mask, int running_priority) "%s %d irq %d priority %d cpu priority mask %d= cpu running priority %d" gic_update_set_irq(int cpu, const char *name, int level) "cpu[%d]: %s =3D = %d" -gic_acknowledge_irq(int cpu, int irq) "cpu %d acknowledged irq %d" +gic_acknowledge_irq(const char *s, int cpu, int irq) "%s %d acknowledged i= rq %d" +gic_cpu_write(const char *s, int cpu, int addr, uint32_t val) "%s %d iface= write at 0x%08x 0x%08" PRIx32 +gic_cpu_read(const char *s, int cpu, int addr, uint32_t val) "%s %d iface = read at 0x%08x: 0x%08" PRIx32 +gic_hyp_read(int addr, uint32_t val) "hyp read at 0x%08x: 0x%08" PRIx32 +gic_hyp_write(int addr, uint32_t val) "hyp write at 0x%08x: 0x%08" PRIx32 +gic_dist_read(int addr, unsigned int size, uint32_t val) "dist read at 0x%= 08x size %u: 0x%08" PRIx32 +gic_dist_write(int addr, unsigned int size, uint32_t val) "dist write at 0= x%08x size %u: 0x%08" PRIx32 +gic_lr_entry(int cpu, int entry, uint32_t val) "cpu %d: new lr entry %d: 0= x%08" PRIx32 +gic_update_maintenance_irq(int cpu, int val) "cpu %d: maintenance =3D %d" =20 # hw/intc/arm_gicv3_cpuif.c gicv3_icc_pmr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_PMR read cpu 0x%= x value 0x%" PRIx64 --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Fri, 29 Jun 2018 09:30:44 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 92644443495; Fri, 29 Jun 2018 15:30:43 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uj8U1cokJOmv; Fri, 29 Jun 2018 15:30:42 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 80CCC4434BB; Fri, 29 Jun 2018 15:30:42 +0200 (CEST) Received: from michell-laptop.hive.antfield.fr (LFbn-LYO-1-488-36.w2-7.abo.wanadoo.fr [2.7.77.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 011C3443496; Fri, 29 Jun 2018 15:30:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279043; bh=pZYy7vYLlg51p8GPJgcPlN1LsdJ1D5PyMqlvVOLED84=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=hw+sZ/Pk+LzRRB4Fo8TyzTpXX4XC9SzZpG05YmJ9xE2YgWWgHsAha1gFEJQubI0UN w0i8g1ReAvBnYbTKwCErxoRzauDoaaHjBvY9cVy21OZ5YxW/VhOryTbWe7AUvhEx5o X+vpSSly68C+k3tdqrccDRRyg0JytAQVzQmCbQO4= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=iJRuw5dN; dkim=pass (1024-bit key) header.d=greensocs.com header.b=iJRuw5dN DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279042; bh=pZYy7vYLlg51p8GPJgcPlN1LsdJ1D5PyMqlvVOLED84=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=iJRuw5dNNGUR+lGvSW1xU0gTCOp6dvks0bvvusQaRRQQW8tCugEiS1rqf/9u7UMTm kehQRYY6JBEEJi9sYC0rVNKPHtSVqJ9u3DXOiEPY3EfFIyi8HX/zNJUcJ9jb1XWTGZ pkNF3xk0KGBw3gQV+4aVJJ+6CsZUb33+LLPputEM= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279042; bh=pZYy7vYLlg51p8GPJgcPlN1LsdJ1D5PyMqlvVOLED84=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=iJRuw5dNNGUR+lGvSW1xU0gTCOp6dvks0bvvusQaRRQQW8tCugEiS1rqf/9u7UMTm kehQRYY6JBEEJi9sYC0rVNKPHtSVqJ9u3DXOiEPY3EfFIyi8HX/zNJUcJ9jb1XWTGZ pkNF3xk0KGBw3gQV+4aVJJ+6CsZUb33+LLPputEM= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:53 +0200 Message-Id: <20180629132954.24269-20-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 19/20] xlnx-zynqmp: Improve GIC wiring and MMIO mapping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This commit improve the way the GIC is realized and connected in the ZynqMP SoC. The security extensions are enabled only if requested in the machine state. The same goes for the virtualization extensions. All the GIC to APU CPU(s) IRQ lines are now connected, including FIQ, vIRQ and vFIQ. The missing CPU to GIC timers IRQ connections are also added (HYP and SEC timers). The GIC maintenance IRQs are back-wired to the correct GIC PPIs. Finally, the MMIO mappings are reworked to take into account the ZynqMP specificities. the GIC (v)CPU interface is aliased 16 times: * for the firsts 0x1000 bytes from 0xf9010000 to 0xf901f000 * for the seconds 0x1000 bytes from 0xf9020000 to 0xf902f000 Mappings of the virtual interface and virtual CPU interface are mapped only when virtualization extensions are requested. The XlnxZynqMPGICRegion struct has been enhanced to be able to catch all this information. Signed-off-by: Luc Michel --- hw/arm/xlnx-zynqmp.c | 92 ++++++++++++++++++++++++++++++++---- include/hw/arm/xlnx-zynqmp.h | 4 +- 2 files changed, 86 insertions(+), 10 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 29df35fb75..42c29b8d06 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -29,12 +29,17 @@ =20 #define ARM_PHYS_TIMER_PPI 30 #define ARM_VIRT_TIMER_PPI 27 +#define ARM_HYP_TIMER_PPI 26 +#define ARM_SEC_TIMER_PPI 29 +#define GIC_MAINTENANCE_PPI 25 =20 #define GEM_REVISION 0x40070106 =20 #define GIC_BASE_ADDR 0xf9000000 #define GIC_DIST_ADDR 0xf9010000 #define GIC_CPU_ADDR 0xf9020000 +#define GIC_VIFACE_ADDR 0xf9040000 +#define GIC_VCPU_ADDR 0xf9060000 =20 #define SATA_INTR 133 #define SATA_ADDR 0xFD0C0000 @@ -111,11 +116,54 @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH= ] =3D { typedef struct XlnxZynqMPGICRegion { int region_index; uint32_t address; + uint32_t offset; + bool virt; } XlnxZynqMPGICRegion; =20 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] =3D { - { .region_index =3D 0, .address =3D GIC_DIST_ADDR, }, - { .region_index =3D 1, .address =3D GIC_CPU_ADDR, }, + /* Distributor */ + { + .region_index =3D 0, + .address =3D GIC_DIST_ADDR, + .offset =3D 0, + .virt =3D false + }, + + /* CPU interface */ + { + .region_index =3D 1, + .address =3D GIC_CPU_ADDR, + .offset =3D 0, + .virt =3D false + }, + { + .region_index =3D 1, + .address =3D GIC_CPU_ADDR + 0x10000, + .offset =3D 0x1000, + .virt =3D false + }, + + /* Virtual interface */ + { + .region_index =3D 2, + .address =3D GIC_VIFACE_ADDR, + .offset =3D 0, + .virt =3D true + }, + + /* Virtual CPU interface */ + { + .region_index =3D 3, + .address =3D GIC_VCPU_ADDR, + .offset =3D 0, + .virt =3D true + }, + { + .region_index =3D 3, + .address =3D GIC_VCPU_ADDR + 0x10000, + .offset =3D 0x1000, + .virt =3D true + }, }; =20 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) @@ -286,6 +334,9 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error= **errp) qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32= ); qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); + qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secur= e); + qdev_prop_set_bit(DEVICE(&s->gic), + "has-virtualization-extensions", s->virt); =20 /* Realize APUs before realizing the GIC. KVM requires this. */ for (i =3D 0; i < num_apus; i++) { @@ -330,19 +381,23 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Err= or **errp) for (i =3D 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { SysBusDevice *gic =3D SYS_BUS_DEVICE(&s->gic); const XlnxZynqMPGICRegion *r =3D &xlnx_zynqmp_gic_regions[i]; - MemoryRegion *mr =3D sysbus_mmio_get_region(gic, r->region_index); + MemoryRegion *mr; uint32_t addr =3D r->address; int j; =20 - sysbus_mmio_map(gic, r->region_index, addr); + if (r->virt && !s->virt) { + continue; + } =20 + mr =3D sysbus_mmio_get_region(gic, r->region_index); for (j =3D 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { MemoryRegion *alias =3D &s->gic_mr[i][j]; =20 - addr +=3D XLNX_ZYNQMP_GIC_REGION_SIZE; memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias",= mr, - 0, XLNX_ZYNQMP_GIC_REGION_SIZE); + r->offset, XLNX_ZYNQMP_GIC_REGION_SIZ= E); memory_region_add_subregion(system_memory, addr, alias); + + addr +=3D XLNX_ZYNQMP_GIC_REGION_SIZE; } } =20 @@ -352,12 +407,33 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Err= or **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), ARM_CPU_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, + qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), + ARM_CPU_FIQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, + qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), + ARM_CPU_VIRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, + qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), + ARM_CPU_VFIQ)); irq =3D qdev_get_gpio_in(DEVICE(&s->gic), arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); - qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq); + qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); irq =3D qdev_get_gpio_in(DEVICE(&s->gic), arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); - qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); + qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); + irq =3D qdev_get_gpio_in(DEVICE(&s->gic), + arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); + qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); + irq =3D qdev_get_gpio_in(DEVICE(&s->gic), + arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); + qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); + + if (s->virt) { + irq =3D qdev_get_gpio_in(DEVICE(&s->gic), + arm_gic_ppi_index(i, GIC_MAINTENANCE_PP= I)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, = irq); + } } =20 if (s->has_rpu) { diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 82b6ec2486..98f925ab84 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -53,7 +53,7 @@ #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 =20 -#define XLNX_ZYNQMP_GIC_REGIONS 2 +#define XLNX_ZYNQMP_GIC_REGIONS 6 =20 /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k off= sets * and under-decodes the 64k region. This mirrors the 4k regions to every = 4k @@ -62,7 +62,7 @@ */ =20 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000 -#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE= - 1) +#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE) =20 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull =20 --=20 2.17.1 From nobody Mon Feb 9 19:10:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530279673168950.309368575948; Fri, 29 Jun 2018 06:41:13 -0700 (PDT) Received: from localhost ([::1]:42210 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYteA-00087s-SX for importer@patchew.org; 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a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1530279042; bh=Hcm6iL2d/lKqBaMAJY5X4I3zo8s+b1ZDK/eC0Gwqqm4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=sQ6J4OvioQ3L+ZtrgTtKhPx6/D8vDBwNv3l2u72F9wDrb0DjwFDmJnbQiUUoarFHM yEFYHJ5/BkjbbHhma84yXOa20naNQvmSPrCGMsDquIax6QitZf8Q8sTWpB1u4m7szp KlYqDXmAbq9E2Bq8T/qdgmthzUudpzbEdsa6ar34= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 15:29:54 +0200 Message-Id: <20180629132954.24269-21-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629132954.24269-1-luc.michel@greensocs.com> References: <20180629132954.24269-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 20/20] arm/virt: Add support for GICv2 virtualization extensions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for GICv2 virtualization extensions by mapping the necessary I/O regions and connecting the maintenance IRQ lines. Declare those additions in the device tree and in the ACPI tables. Signed-off-by: Luc Michel --- hw/arm/virt-acpi-build.c | 4 ++++ hw/arm/virt.c | 50 +++++++++++++++++++++++++++++++++------- include/hw/arm/virt.h | 3 +++ 3 files changed, 49 insertions(+), 8 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 6ea47e2588..3b74bf0372 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -659,6 +659,8 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) gicc->length =3D sizeof(*gicc); if (vms->gic_version =3D=3D 2) { gicc->base_address =3D cpu_to_le64(memmap[VIRT_GIC_CPU].base); + gicc->gich_base_address =3D cpu_to_le64(memmap[VIRT_GIC_HYP].b= ase); + gicc->gicv_base_address =3D cpu_to_le64(memmap[VIRT_GIC_VCPU].= base); } gicc->cpu_interface_number =3D cpu_to_le32(i); gicc->arm_mpidr =3D cpu_to_le64(armcpu->mp_affinity); @@ -670,6 +672,8 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } if (vms->virt && vms->gic_version =3D=3D 3) { gicc->vgic_interrupt =3D cpu_to_le32(PPI(ARCH_GICV3_MAINT_IRQ)= ); + } else if (vms->virt && vms->gic_version =3D=3D 2) { + gicc->vgic_interrupt =3D cpu_to_le32(PPI(ARCH_GICV2_MAINT_IRQ)= ); } } =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 742f68afca..e45b9de3be 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -131,6 +131,8 @@ static const MemMapEntry a15memmap[] =3D { [VIRT_GIC_DIST] =3D { 0x08000000, 0x00010000 }, [VIRT_GIC_CPU] =3D { 0x08010000, 0x00010000 }, [VIRT_GIC_V2M] =3D { 0x08020000, 0x00001000 }, + [VIRT_GIC_HYP] =3D { 0x08030000, 0x00001000 }, + [VIRT_GIC_VCPU] =3D { 0x08040000, 0x00001000 }, /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ [VIRT_GIC_ITS] =3D { 0x08080000, 0x00020000 }, /* This redistributor space allows up to 2*64kB*123 CPUs */ @@ -438,11 +440,26 @@ static void fdt_add_gic_node(VirtMachineState *vms) /* 'cortex-a15-gic' means 'GIC v2' */ qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", "arm,cortex-a15-gic"); - qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", - 2, vms->memmap[VIRT_GIC_DIST].base, - 2, vms->memmap[VIRT_GIC_DIST].size, - 2, vms->memmap[VIRT_GIC_CPU].base, - 2, vms->memmap[VIRT_GIC_CPU].size); + if (!vms->virt) { + qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", + 2, vms->memmap[VIRT_GIC_DIST].bas= e, + 2, vms->memmap[VIRT_GIC_DIST].siz= e, + 2, vms->memmap[VIRT_GIC_CPU].base, + 2, vms->memmap[VIRT_GIC_CPU].size= ); + } else { + qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", + 2, vms->memmap[VIRT_GIC_DIST].bas= e, + 2, vms->memmap[VIRT_GIC_DIST].siz= e, + 2, vms->memmap[VIRT_GIC_CPU].base, + 2, vms->memmap[VIRT_GIC_CPU].size, + 2, vms->memmap[VIRT_GIC_HYP].base, + 2, vms->memmap[VIRT_GIC_HYP].size, + 2, vms->memmap[VIRT_GIC_VCPU].bas= e, + 2, vms->memmap[VIRT_GIC_VCPU].siz= e); + qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts", + GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV2_MAINT_= IRQ, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + } } =20 qemu_fdt_setprop_cell(vms->fdt, "/intc", "phandle", vms->gic_phandle); @@ -563,6 +580,11 @@ static void create_gic(VirtMachineState *vms, qemu_irq= *pic) qdev_prop_set_uint32(gicdev, "redist-region-count[1]", MIN(smp_cpus - redist0_count, redist1_capacity)); } + } else { + if (!kvm_irqchip_in_kernel()) { + qdev_prop_set_bit(gicdev, "has-virtualization-extensions", + vms->virt); + } } qdev_init_nofail(gicdev); gicbusdev =3D SYS_BUS_DEVICE(gicdev); @@ -574,6 +596,10 @@ static void create_gic(VirtMachineState *vms, qemu_irq= *pic) } } else { sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); + if (vms->virt) { + sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); + sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); + } } =20 /* Wire the outputs from each CPU's generic timer and the GICv3 @@ -600,9 +626,17 @@ static void create_gic(VirtMachineState *vms, qemu_irq= *pic) ppibase + timer_irq[irq= ])); } =20 - qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",= 0, - qdev_get_gpio_in(gicdev, ppibase - + ARCH_GICV3_MAINT_IR= Q)); + if (type =3D=3D 3) { + qemu_irq irq =3D qdev_get_gpio_in(gicdev, + ppibase + ARCH_GICV3_MAINT_IRQ= ); + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", + 0, irq); + } else if (vms->virt) { + qemu_irq irq =3D qdev_get_gpio_in(gicdev, + ppibase + ARCH_GICV2_MAINT_IRQ= ); + sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); + } + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, qdev_get_gpio_in(gicdev, ppibase + VIRTUAL_PMU_IRQ)); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 9a870ccb6a..9e2f33f2d1 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -42,6 +42,7 @@ #define NUM_VIRTIO_TRANSPORTS 32 #define NUM_SMMU_IRQS 4 =20 +#define ARCH_GICV2_MAINT_IRQ 9 #define ARCH_GICV3_MAINT_IRQ 9 =20 #define ARCH_TIMER_VIRT_IRQ 11 @@ -60,6 +61,8 @@ enum { VIRT_GIC_DIST, VIRT_GIC_CPU, VIRT_GIC_V2M, + VIRT_GIC_HYP, + VIRT_GIC_VCPU, VIRT_GIC_ITS, VIRT_GIC_REDIST, VIRT_GIC_REDIST2, --=20 2.17.1