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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id j3-v6sm11687618pff.35.2018.06.28.17.15.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jun 2018 17:15:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bDxeI45M3+Sw5t2d9J5a8/XWQwI0hxpwq9USCSGZuao=; b=b1CydImQBA+kFalvu6xO1Q4AseOHN/eGxS4TyZ1Wcg8Z+Cxe+vAjJmxtUp03XERwu9 uWdgSVJBBbyn1xM6uU8RaWrE80PqzBrEFElMrv0+qVnLJ2X/HN7kZYWe4GK3UtIYbHJc P5v2QciPcb/BwKeVFptOKCDUVwf4zwRDpQ1Pc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bDxeI45M3+Sw5t2d9J5a8/XWQwI0hxpwq9USCSGZuao=; b=RlzTXmR7dXRQLOf/yaZrTw8izvIyUCljnKSiJjAvLCJF7F1uvFLSQOdBp9bqztwb/B L5eGyL654cEMR7MZPBbIjrv3dqvnk9cfW2+/RzdlxlB4NLAmgoQ9UeLxTRqfuoBYvVBA T7fu+WJqbtOwr7lmFevQZNyJt5xKz5ezU9m3aeMN3bAOdvSl0HEX6OlhjN5WqKwJGMO6 VfIcwyIjNqzXfp/sXNTutnIoeSIRJn8TVdkJMBqvsB4CO86yP/bI7wC8A5qHZ/Iq4s42 flxxyEwkKgS69+90jTA1ytcrgTojNvCaM7JECYrwkrjd3puymePYJQrxI1YEMeUbnfgu uZ7w== X-Gm-Message-State: APt69E28648/s+zfZZzJUl4/N+dlhztt81Ic6OfYGXI8HD8cLnapKuct vs6t2hOEGEzcrUt6LFgKw+GHt8r+q2w= X-Google-Smtp-Source: ADUXVKIHt9RtDYSKFFMzOX3QAD2rhaHwnYzlnyDhdwSZFNHXQXD9r3QgswymzlLIdxEUWMEBJgLf1Q== X-Received: by 2002:a17:902:8645:: with SMTP id y5-v6mr12460240plt.334.1530231343761; Thu, 28 Jun 2018 17:15:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 17:15:34 -0700 Message-Id: <20180629001538.11415-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629001538.11415-1-richard.henderson@linaro.org> References: <20180629001538.11415-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22b Subject: [Qemu-devel] [PATCH 2/6] target/arm: Fix SVE system register access checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Leave ARM_CP_SVE, removing ARM_CP_FPU; the sve_access_check produced by the flag already includes fp_access_check. If we also check ARM_CP_FPU the double fp_access_check asserts. Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson Reviewed-by: Laurent Desnogues Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 8 ++++---- target/arm/translate-a64.c | 5 ++--- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b19c7ace78..a855da045b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4393,7 +4393,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, static const ARMCPRegInfo zcr_el1_reginfo =3D { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, + .access =3D PL1_RW, .type =3D ARM_CP_SVE, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; @@ -4401,7 +4401,7 @@ static const ARMCPRegInfo zcr_el1_reginfo =3D { static const ARMCPRegInfo zcr_el2_reginfo =3D { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, + .access =3D PL2_RW, .type =3D ARM_CP_SVE, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; @@ -4409,14 +4409,14 @@ static const ARMCPRegInfo zcr_el2_reginfo =3D { static const ARMCPRegInfo zcr_no_el2_reginfo =3D { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, + .access =3D PL2_RW, .type =3D ARM_CP_SVE, .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }; =20 static const ARMCPRegInfo zcr_el3_reginfo =3D { .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, + .access =3D PL3_RW, .type =3D ARM_CP_SVE, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f986340832..45a6c2a3aa 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1633,11 +1633,10 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, default: break; } - if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { - return; - } if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { return; + } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { + return; } =20 if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO))= { --=20 2.17.1