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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id j3-v6sm11687618pff.35.2018.06.28.17.15.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jun 2018 17:15:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qCoeOPRxfqBzz9U1Vv3Tu63bMTIpVPlkzyb0DKca5aA=; b=NpFTEKNgXJFVxapcFnnRhZb8ww9RZZBAxkES07rf7QGi3ZXnJCBb+1k0l79ycQqzch w6eUL+kY7WMWtLY3+kwFXJ0WJDIaS1/QyrYpWwCoN6qCu/2BuMnUz78/q/wZTUnk63b3 6EVe9KE1S9Eva1vQ5taGd70hY/GdMxaYQeMAI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qCoeOPRxfqBzz9U1Vv3Tu63bMTIpVPlkzyb0DKca5aA=; b=k6mc539irYc4ABqoDzDpaDU1n5V30EaU/KcisV8eAyjt1ziwIlXPpCtZfJHfuA883k UWsoD1WKIciStJQqwlTid+HPTSc4N/sFpxdoraj05Bz+ZtDhdgyd1Of1IXU4jlBjM0zD 7gAS5k02q/TAwxNOQv77kHs3SRZ0Gviuw9DCsE+8lCGA6X0i45yvsfWs/BXnLK5IKPiF zPCPZjl4C6UUUHuVxzfdDHp/KM5rY6mnDQ/paAuBS6SOCvqwART7cpbUPG6XS2/6e73j rxrHohU+ce9BDvmAkgcYE9UGCQn9EPEScbYtWGxE3/byRXm6so0QU6ovJtzS//SZSR65 zc0Q== X-Gm-Message-State: APt69E0tgXcaFMidSGPmgVqy1dD9JRwxTghG6oc1AAiNSfVoXuQTsXoZ w+H7Ac85JzD0WKE59Hc4u4zdKFZPFPc= X-Google-Smtp-Source: ADUXVKLUFFAxeMywy0+4OcBK7sVhSSW9Mz8bt8FzNWI2YwwLMeRz8ZVpoQHDbOuy/A0s0+1IhpZS1g== X-Received: by 2002:a65:6699:: with SMTP id b25-v6mr10723196pgw.426.1530231342298; Thu, 28 Jun 2018 17:15:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 17:15:33 -0700 Message-Id: <20180629001538.11415-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629001538.11415-1-richard.henderson@linaro.org> References: <20180629001538.11415-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PATCH 1/6] target/arm: Fix SVE signed division vs x86 overflow exception X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We already check for the same condition within the normal integer sdiv and sdiv64 helpers. Use a slightly different formation that does not require deducing the expression type. Fixes: f97cfd596ed Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/sve_helper.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 790cbacd14..7d7fc90566 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -369,7 +369,13 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *= vg, uint32_t desc) \ #define DO_MIN(N, M) ((N) >=3D (M) ? (M) : (N)) #define DO_ABD(N, M) ((N) >=3D (M) ? (N) - (M) : (M) - (N)) #define DO_MUL(N, M) (N * M) -#define DO_DIV(N, M) (M ? N / M : 0) + +/* The zero divisor case is architectural; the -1 divisor case works + * around the x86 INT_MIN / -1 overflow exception without having to + * deduce the minimum integer for the type of the expression. + */ +#define DO_SDIV(N, M) (unlikely(M =3D=3D 0) ? 0 : unlikely(M =3D=3D -1) ? = -N : N / M) +#define DO_UDIV(N, M) (unlikely(M =3D=3D 0) ? 0 : N / M) =20 DO_ZPZZ(sve_and_zpzz_b, uint8_t, H1, DO_AND) DO_ZPZZ(sve_and_zpzz_h, uint16_t, H1_2, DO_AND) @@ -477,11 +483,11 @@ DO_ZPZZ(sve_umulh_zpzz_h, uint16_t, H1_2, do_mulh_h) DO_ZPZZ(sve_umulh_zpzz_s, uint32_t, H1_4, do_mulh_s) DO_ZPZZ_D(sve_umulh_zpzz_d, uint64_t, do_umulh_d) =20 -DO_ZPZZ(sve_sdiv_zpzz_s, int32_t, H1_4, DO_DIV) -DO_ZPZZ_D(sve_sdiv_zpzz_d, int64_t, DO_DIV) +DO_ZPZZ(sve_sdiv_zpzz_s, int32_t, H1_4, DO_SDIV) +DO_ZPZZ_D(sve_sdiv_zpzz_d, int64_t, DO_SDIV) =20 -DO_ZPZZ(sve_udiv_zpzz_s, uint32_t, H1_4, DO_DIV) -DO_ZPZZ_D(sve_udiv_zpzz_d, uint64_t, DO_DIV) +DO_ZPZZ(sve_udiv_zpzz_s, uint32_t, H1_4, DO_UDIV) +DO_ZPZZ_D(sve_udiv_zpzz_d, uint64_t, DO_UDIV) =20 /* Note that all bits of the shift are significant and not modulo the element size. */ --=20 2.17.1 From nobody Tue Feb 10 10:58:19 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530231492115467.4561342705108; Thu, 28 Jun 2018 17:18:12 -0700 (PDT) Received: from localhost ([::1]:39238 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYh6x-0005Jf-0i for importer@patchew.org; Thu, 28 Jun 2018 20:18:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41372) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYh4k-00041O-3W for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYh4j-0006fH-3U for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:46 -0400 Received: from mail-pl0-x22b.google.com ([2607:f8b0:400e:c01::22b]:45791) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYh4i-0006eW-UK for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:45 -0400 Received: by mail-pl0-x22b.google.com with SMTP id bi1-v6so3543378plb.12 for ; Thu, 28 Jun 2018 17:15:44 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id j3-v6sm11687618pff.35.2018.06.28.17.15.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jun 2018 17:15:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bDxeI45M3+Sw5t2d9J5a8/XWQwI0hxpwq9USCSGZuao=; b=b1CydImQBA+kFalvu6xO1Q4AseOHN/eGxS4TyZ1Wcg8Z+Cxe+vAjJmxtUp03XERwu9 uWdgSVJBBbyn1xM6uU8RaWrE80PqzBrEFElMrv0+qVnLJ2X/HN7kZYWe4GK3UtIYbHJc P5v2QciPcb/BwKeVFptOKCDUVwf4zwRDpQ1Pc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bDxeI45M3+Sw5t2d9J5a8/XWQwI0hxpwq9USCSGZuao=; b=RlzTXmR7dXRQLOf/yaZrTw8izvIyUCljnKSiJjAvLCJF7F1uvFLSQOdBp9bqztwb/B L5eGyL654cEMR7MZPBbIjrv3dqvnk9cfW2+/RzdlxlB4NLAmgoQ9UeLxTRqfuoBYvVBA T7fu+WJqbtOwr7lmFevQZNyJt5xKz5ezU9m3aeMN3bAOdvSl0HEX6OlhjN5WqKwJGMO6 VfIcwyIjNqzXfp/sXNTutnIoeSIRJn8TVdkJMBqvsB4CO86yP/bI7wC8A5qHZ/Iq4s42 flxxyEwkKgS69+90jTA1ytcrgTojNvCaM7JECYrwkrjd3puymePYJQrxI1YEMeUbnfgu uZ7w== X-Gm-Message-State: APt69E28648/s+zfZZzJUl4/N+dlhztt81Ic6OfYGXI8HD8cLnapKuct vs6t2hOEGEzcrUt6LFgKw+GHt8r+q2w= X-Google-Smtp-Source: ADUXVKIHt9RtDYSKFFMzOX3QAD2rhaHwnYzlnyDhdwSZFNHXQXD9r3QgswymzlLIdxEUWMEBJgLf1Q== X-Received: by 2002:a17:902:8645:: with SMTP id y5-v6mr12460240plt.334.1530231343761; Thu, 28 Jun 2018 17:15:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 17:15:34 -0700 Message-Id: <20180629001538.11415-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629001538.11415-1-richard.henderson@linaro.org> References: <20180629001538.11415-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22b Subject: [Qemu-devel] [PATCH 2/6] target/arm: Fix SVE system register access checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Leave ARM_CP_SVE, removing ARM_CP_FPU; the sve_access_check produced by the flag already includes fp_access_check. If we also check ARM_CP_FPU the double fp_access_check asserts. Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson Reviewed-by: Laurent Desnogues Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 8 ++++---- target/arm/translate-a64.c | 5 ++--- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b19c7ace78..a855da045b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4393,7 +4393,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, static const ARMCPRegInfo zcr_el1_reginfo =3D { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, + .access =3D PL1_RW, .type =3D ARM_CP_SVE, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; @@ -4401,7 +4401,7 @@ static const ARMCPRegInfo zcr_el1_reginfo =3D { static const ARMCPRegInfo zcr_el2_reginfo =3D { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, + .access =3D PL2_RW, .type =3D ARM_CP_SVE, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; @@ -4409,14 +4409,14 @@ static const ARMCPRegInfo zcr_el2_reginfo =3D { static const ARMCPRegInfo zcr_no_el2_reginfo =3D { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, + .access =3D PL2_RW, .type =3D ARM_CP_SVE, .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }; =20 static const ARMCPRegInfo zcr_el3_reginfo =3D { .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_SVE | ARM_CP_FPU, + .access =3D PL3_RW, .type =3D ARM_CP_SVE, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f986340832..45a6c2a3aa 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1633,11 +1633,10 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, default: break; } - if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { - return; - } if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { return; + } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { + return; } =20 if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO))= { --=20 2.17.1 From nobody Tue Feb 10 10:58:19 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530231492218649.0534772762722; Thu, 28 Jun 2018 17:18:12 -0700 (PDT) Received: from localhost ([::1]:39239 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYh6x-0005Kf-O7 for importer@patchew.org; Thu, 28 Jun 2018 20:18:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41391) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYh4l-00041X-2p for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYh4k-0006g2-82 for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:47 -0400 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:33539) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYh4k-0006fU-2y for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:46 -0400 Received: by mail-pl0-x242.google.com with SMTP id 6-v6so3556100plb.0 for ; Thu, 28 Jun 2018 17:15:46 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id j3-v6sm11687618pff.35.2018.06.28.17.15.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jun 2018 17:15:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aIqsOu2TjX3ToM1uKZUQ3z3HkuGStyywZKhiXfkMdBY=; b=JjAqTkjLmUdc/5NhpUJireUzNmEuW6SncLuNXFZkPOt8eXbbstkD4CLzC4arIHFcvs bnvYd3LZCVlqtMWzQ0nvs4Luvrn9Ib4IU/8fswA/raow+f4SBwB1iFdLW4nHI9qZoONG RL+4B6Pw+AcXKITCLT0V9HW3a0MGKaE+Qyb08= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aIqsOu2TjX3ToM1uKZUQ3z3HkuGStyywZKhiXfkMdBY=; b=eJUmXABDnPhz/4VJIE2wv4tIoSkglDXf7YLjSyjr8s87VSpAA5xyWW/vwSseepiCwQ LD8VIF3Jg1JnECWazQ5nO2NecKqbjbKbjJyILhK8TBxIk+/x00InwKGzbHSXXLeTE7wh PKoFpjnicI+jQhLErrSuD5RpmryAm5BFLcb/dnVBennBnzjbT/2Scj3KJMWEmrQa5qBy yrfH89BSAB4Z2nLGYShw/mnFCOWb1/yh82tcLS2Fe5zUmQPfx4aMhn8ypEb3uRQiDZ1z epKSko7KTnKu7kbolkxUIfGTZKu1Ui4pCvRMNJZ0zHz7Z3BpB60tKr2gjuma81MLHa8x BG7g== X-Gm-Message-State: APt69E0+NJmBt71pW+rs/Nlcqg9+e7YW1dLqtSf8smgFGWrcWsNjzrgH OAE5eJSdMd3cSwr4dj7Bazw6bEL489w= X-Google-Smtp-Source: ADUXVKKQN6XQ5JU0cpmzFrcy7f6mCgIhKIt3BzKxnuV34IOugeXUJXkh/EOAirGXPE1+hY9ALSv0IA== X-Received: by 2002:a17:902:2927:: with SMTP id g36-v6mr12350163plb.303.1530231344951; Thu, 28 Jun 2018 17:15:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 17:15:35 -0700 Message-Id: <20180629001538.11415-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629001538.11415-1-richard.henderson@linaro.org> References: <20180629001538.11415-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 3/6] target/arm: Prune a57 features from max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There is no need to re-set these 9 features already implied by the call to aarch64_a57_initfn. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu64.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3b4bc73ffa..8040493d5c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -235,19 +235,10 @@ static void aarch64_max_initfn(Object *obj) * whereas the architecture requires them to be present in both if * present in either. */ - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_V8_AES); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); set_feature(&cpu->env, ARM_FEATURE_V8_SM3); set_feature(&cpu->env, ARM_FEATURE_V8_SM4); - set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); - set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_V8_ATOMICS); set_feature(&cpu->env, ARM_FEATURE_V8_RDM); set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); --=20 2.17.1 From nobody Tue Feb 10 10:58:19 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530231695243141.1302563237913; Thu, 28 Jun 2018 17:21:35 -0700 (PDT) Received: from localhost ([::1]:39259 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYhAM-00084u-Ji for importer@patchew.org; Thu, 28 Jun 2018 20:21:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41404) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYh4m-000426-HT for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYh4l-0006gl-LO for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:48 -0400 Received: from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:39642) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYh4l-0006gO-El for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:47 -0400 Received: by mail-pf0-x22a.google.com with SMTP id s21-v6so3344370pfm.6 for ; Thu, 28 Jun 2018 17:15:47 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id j3-v6sm11687618pff.35.2018.06.28.17.15.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jun 2018 17:15:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mHBz3+eq9kbfyBEjgaxotqiA3EmZG97H4thceVsKJNg=; b=AauG+fHxNAtp03tYCnJEzXbi/WIcpu/hZJEylI26SIRcQjqTt+2zKZ1kvCH6Olq8Uq rGPYcpSOIj+w5F3u3DGkrxDQxNe5EUOWxS60BACx9DNqSttLDlHfvwztAPJUgYBOBpCn Ke+g6Wf3jh9JVMSsskcMR1H2VyqY0d3GswFeM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mHBz3+eq9kbfyBEjgaxotqiA3EmZG97H4thceVsKJNg=; b=aVxVzolDptYKn+r5b1dcp7WiMdA1mhZGf3yxg8GfZ+AXvOTjtPcl3s1oGHt8guVz+E Fg7kBefx0Cag5RdCOG2z7hpd/FpdFTunMTC61ySpzX6s6ECuDrerMro7T2YJTqxFnx5U wzBJgTTrqLHqKOq0avYcsOAXmOfsSo5dRt3YGfhuMismi5XiAVoCievj63PHqat//GKp EL6SWH1ttsfSDUoWRROAdu9cgNsBrRE3Rc9Ui+pPyzYemf8C2FSkKdN3D6iinNn0p4T/ Yy6Bo6OAQkSnePXz22WroWkQxfWo/DrO8Vgf+Is5gfFea7BsBA0IKZbyLCfkOAeAXzFW +BbQ== X-Gm-Message-State: APt69E1UB/T+utOZaR5reodOGm6/9YmRZlVDBPM+vthV2BVlU8h9a1b3 yzRpQJQAtOBxIvVsUs8iGNbhtZu9D98= X-Google-Smtp-Source: AAOMgpcn88E/S3cnPOFxFkhVUFXiIvsZZ+yFENMWXzX+wAwWHskGeWqP19Ra2xBHiPUxyapRUwF62A== X-Received: by 2002:a62:ed13:: with SMTP id u19-v6mr12128699pfh.125.1530231346317; Thu, 28 Jun 2018 17:15:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 17:15:36 -0700 Message-Id: <20180629001538.11415-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629001538.11415-1-richard.henderson@linaro.org> References: <20180629001538.11415-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PATCH 4/6] target/arm: Prune a15 features from max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There is no need to re-set these 3 features already implied by the call to aarch64_a15_initfn. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index aa62315cea..878cc6c7e8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1796,9 +1796,6 @@ static void arm_max_initfn(Object *obj) * since we don't correctly set the ID registers to advertise them, */ set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_V8_AES); set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); --=20 2.17.1 From nobody Tue Feb 10 10:58:19 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530231618433954.5108757495809; Thu, 28 Jun 2018 17:20:18 -0700 (PDT) Received: from localhost ([::1]:39249 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYh97-00076P-Oc for importer@patchew.org; Thu, 28 Jun 2018 20:20:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41420) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYh4o-00043l-85 for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYh4n-0006hb-42 for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:50 -0400 Received: from mail-pl0-x22c.google.com ([2607:f8b0:400e:c01::22c]:41159) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYh4m-0006h4-Mr for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:49 -0400 Received: by mail-pl0-x22c.google.com with SMTP id w8-v6so3553480ply.8 for ; Thu, 28 Jun 2018 17:15:48 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id j3-v6sm11687618pff.35.2018.06.28.17.15.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jun 2018 17:15:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zcgc074MhgPb88dn8j3LBz2LriQUpfV1TTmj3EVQ6yA=; b=IcyAqCX9xSyd/ARFsTXrSmSgRpwk0XQUx/fTRZXmAS8HWZkcPQCAVo48/Hf50jhI4f LsslSORfaZHMsOsxLdRcDd0XCuu+w3nYJDco4veb7NVOKcqVnrRWTgwhOauxAtgSnnpA YR+Q0fo6npppyN8I7B6GtpTWWZW16UvCcj70o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zcgc074MhgPb88dn8j3LBz2LriQUpfV1TTmj3EVQ6yA=; b=l3zh5tmh7NX5jmZQ4ugzxk/RaIv38vDX9X0M01nIAtbHEHggy/UK4wu2mtxhB95MkO 2OdzHvOtL//V6OqgS7sovuw4RyHZ0E0Hzl0ELTeanUYx/zDUv5LqN7eiyw5jMRcq6X/F aiNkhbjZvtVvjtttLvbo9D5St6QzRW6xp6VnYUtGEHAI3nstGtJekUcHVBb8MptU8Vn2 KWWp/g+/P9PX+v0dHE7BOHYk6ftvD5XAJS/SExuHSnlqtw/AL4qSPIti0lFVlp3mbtQQ kw6W4XcTLpis8HNNomY8kDjXaeHsPc0tEewDhx3/SSXr448jgfYt7qFsjHC/EWQ2oLSf 7LsQ== X-Gm-Message-State: APt69E0E3M3+89hjm8GAoQQCEw35dsC/QJKlup7WUI811Rk9EGeWv7hs HcGW6YrVbvXrTP6ykrc03v25BNuVPbk= X-Google-Smtp-Source: ADUXVKJdnUs5y0IRR+2txIXZoGBuJ0Mn4bDCinU9IX6Pgk5WtK//+wPoWBtgdvKOkm+3Fwcr/99H6w== X-Received: by 2002:a17:902:46e:: with SMTP id 101-v6mr12682203ple.39.1530231347585; Thu, 28 Jun 2018 17:15:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 17:15:37 -0700 Message-Id: <20180629001538.11415-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629001538.11415-1-richard.henderson@linaro.org> References: <20180629001538.11415-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22c Subject: [Qemu-devel] [PATCH 5/6] target/arm: Add ID_ISAR6 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This register was added to aa32 state by ARMv8.2. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/cpu.c | 4 ++++ target/arm/cpu64.c | 2 ++ target/arm/helper.c | 5 ++--- 4 files changed, 9 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6a8441c2dd..1505ac936e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -813,6 +813,7 @@ struct ARMCPU { uint32_t id_isar3; uint32_t id_isar4; uint32_t id_isar5; + uint32_t id_isar6; uint64_t id_aa64pfr0; uint64_t id_aa64pfr1; uint64_t id_aa64dfr0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 878cc6c7e8..de1a07a9f1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1262,6 +1262,7 @@ static void cortex_m3_initfn(Object *obj) cpu->id_isar3 =3D 0x01111110; cpu->id_isar4 =3D 0x01310102; cpu->id_isar5 =3D 0x00000000; + cpu->id_isar6 =3D 0x00000000; } =20 static void cortex_m4_initfn(Object *obj) @@ -1288,6 +1289,7 @@ static void cortex_m4_initfn(Object *obj) cpu->id_isar3 =3D 0x01111110; cpu->id_isar4 =3D 0x01310102; cpu->id_isar5 =3D 0x00000000; + cpu->id_isar6 =3D 0x00000000; } =20 static void cortex_m33_initfn(Object *obj) @@ -1316,6 +1318,7 @@ static void cortex_m33_initfn(Object *obj) cpu->id_isar3 =3D 0x01111131; cpu->id_isar4 =3D 0x01310132; cpu->id_isar5 =3D 0x00000000; + cpu->id_isar6 =3D 0x00000000; cpu->clidr =3D 0x00000000; cpu->ctr =3D 0x8000c000; } @@ -1366,6 +1369,7 @@ static void cortex_r5_initfn(Object *obj) cpu->id_isar3 =3D 0x01112131; cpu->id_isar4 =3D 0x0010142; cpu->id_isar5 =3D 0x0; + cpu->id_isar6 =3D 0x0; cpu->mp_is_up =3D true; cpu->pmsav7_dregion =3D 16; define_arm_cp_regs(cpu, cortexr5_cp_reginfo); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8040493d5c..d0581d59d8 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -139,6 +139,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->id_isar3 =3D 0x01112131; cpu->id_isar4 =3D 0x00011142; cpu->id_isar5 =3D 0x00011121; + cpu->id_isar6 =3D 0; cpu->id_aa64pfr0 =3D 0x00002222; cpu->id_aa64dfr0 =3D 0x10305106; cpu->pmceid0 =3D 0x00000000; @@ -199,6 +200,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->id_isar3 =3D 0x01112131; cpu->id_isar4 =3D 0x00011142; cpu->id_isar5 =3D 0x00011121; + cpu->id_isar6 =3D 0; cpu->id_aa64pfr0 =3D 0x00002222; cpu->id_aa64dfr0 =3D 0x10305106; cpu->id_aa64isar0 =3D 0x00011120; diff --git a/target/arm/helper.c b/target/arm/helper.c index a855da045b..e62f02d4e5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4851,11 +4851,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->id_mmfr4 }, - /* 7 is as yet unallocated and must RAZ */ - { .name =3D "ID_ISAR7_RESERVED", .state =3D ARM_CP_STATE_BOTH, + { .name =3D "ID_ISAR6", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .resetvalue =3D cpu->id_isar6 }, REGINFO_SENTINEL }; define_arm_cp_regs(cpu, v6_idregs); --=20 2.17.1 From nobody Tue Feb 10 10:58:19 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530231492219889.6103919646227; Thu, 28 Jun 2018 17:18:12 -0700 (PDT) Received: from localhost ([::1]:39240 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYh72-0005On-N3 for importer@patchew.org; Thu, 28 Jun 2018 20:18:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41431) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYh4p-00045J-IK for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYh4o-0006iE-ES for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:51 -0400 Received: from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:38964) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYh4o-0006hx-6F for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:50 -0400 Received: by mail-pg0-x22a.google.com with SMTP id n2-v6so3167834pgq.6 for ; Thu, 28 Jun 2018 17:15:50 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id j3-v6sm11687618pff.35.2018.06.28.17.15.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jun 2018 17:15:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YHXLcyZt1QNkfP6YbxOwlV259R+b3jcKBj1+zMF8BSQ=; b=JVdbwcdCYIwxJ4S/N7FIP6FHooaxTogS+ulMnXxyFoIZNiTMbj+DCvM8qeHLGaPuW/ 6a5fyNANJrw6mvE24BXYETuGmLTNIIls3clqYqqcNVfYDwVtkej8X4yC+T2x4uBMeJWw 9mefiIFY8R/IxfUkp7v3lHh6b75kUnjnStLLQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YHXLcyZt1QNkfP6YbxOwlV259R+b3jcKBj1+zMF8BSQ=; b=Khm34ODZ7bOgJXaBIXtjSb2Ult5XPvX7NskHIgJwq/xG3ue4ydlard2jP3YjaZAkga U/siuDJsAyLjT3DeuJLAsuz6ux8VhAutpvuQ38CMc5wclcQE4y/j3jDsPTuI3bHbv2dh lGrziUJNixcMC+s1ycsYo5cAT7RFrmnUnE1bZE2iAn9LDY6m/lKIuIAvGUa16upqGhWB OpTFTONUpnm+nvwe7rKXkeqMPWeV50KSEjov62urQ1/bfR5PDH6j5vWTbIoTDK9uwGLR bPIVAh39ZL7Lqo+afkRvGjAUkzOfZw42m7md67IxpJerKPWIQDzYwx+If4GS3PG9MnHv 5TxQ== X-Gm-Message-State: APt69E1MguceOiiFJRKJ2Ld4aqXNODgY23t8mrdgw7J34xJ/Pp1TtnGs sca/BEFdCTT72UiQmqZmBxYN5d9ukRA= X-Google-Smtp-Source: AAOMgpcLciaFCQCutD4APH4XN+EKyrrOhVDgnKch6aqfvXgCMYOpEX5erEgZjwZpYj7dsg5AYf08yQ== X-Received: by 2002:a62:c1c5:: with SMTP id i188-v6mr12142891pfg.155.1530231349016; Thu, 28 Jun 2018 17:15:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 17:15:38 -0700 Message-Id: <20180629001538.11415-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629001538.11415-1-richard.henderson@linaro.org> References: <20180629001538.11415-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH 6/6] target/arm: Set ISAR bits for -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For the supported extensions, fill in the appropriate bits in ID_ISAR5, ID_ISAR6, ID_AA64ISAR0, ID_AA64ISAR1. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 24 +++++++++++++++++------- target/arm/cpu64.c | 36 ++++++++++++++++++++++++++++-------- 2 files changed, 45 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index de1a07a9f1..943c589445 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1795,19 +1795,29 @@ static void arm_max_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); } else { cortex_a15_initfn(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8_AES); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 4, 4, 2); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 8, 4, 1); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 12, 4, 1); + set_feature(&cpu->env, ARM_FEATURE_CRC); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 16, 4, 1); + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 24, 4, 1); + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 28, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); + cpu->id_isar6 =3D deposit32(cpu->id_isar6, 4, 4, 1); + #ifdef CONFIG_USER_ONLY /* We don't set these in system emulation mode for the moment, * since we don't correctly set the ID registers to advertise them, */ set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_V8_AES); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); - set_feature(&cpu->env, ARM_FEATURE_CRC); - set_feature(&cpu->env, ARM_FEATURE_V8_RDM); - set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); - set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); #endif } } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d0581d59d8..b24fee45e3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -230,6 +230,34 @@ static void aarch64_max_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); } else { aarch64_a57_initfn(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); + cpu->id_aa64isar0 =3D deposit64(cpu->id_aa64isar0, 12, 4, 2); + + set_feature(&cpu->env, ARM_FEATURE_V8_ATOMICS); + cpu->id_aa64isar0 =3D deposit64(cpu->id_aa64isar0, 20, 4, 2); + + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); + cpu->id_aa64isar0 =3D deposit64(cpu->id_aa64isar0, 28, 4, 1); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 24, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); + cpu->id_aa64isar0 =3D deposit64(cpu->id_aa64isar0, 32, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); + cpu->id_aa64isar0 =3D deposit64(cpu->id_aa64isar0, 36, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_SM4); + cpu->id_aa64isar0 =3D deposit64(cpu->id_aa64isar0, 40, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); + cpu->id_aa64isar0 =3D deposit64(cpu->id_aa64isar0, 44, 4, 1); + cpu->id_isar6 =3D deposit32(cpu->id_isar6, 4, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); + cpu->id_aa64isar1 =3D deposit64(cpu->id_aa64isar1, 16, 4, 1); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 28, 4, 1); + #ifdef CONFIG_USER_ONLY /* We don't set these in system emulation mode for the moment, * since we don't correctly set the ID registers to advertise them, @@ -237,15 +265,7 @@ static void aarch64_max_initfn(Object *obj) * whereas the architecture requires them to be present in both if * present in either. */ - set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); - set_feature(&cpu->env, ARM_FEATURE_V8_SM3); - set_feature(&cpu->env, ARM_FEATURE_V8_SM4); - set_feature(&cpu->env, ARM_FEATURE_V8_ATOMICS); - set_feature(&cpu->env, ARM_FEATURE_V8_RDM); - set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); set_feature(&cpu->env, ARM_FEATURE_V8_FP16); - set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); set_feature(&cpu->env, ARM_FEATURE_SVE); /* For usermode -cpu max we can use a larger and more efficient DCZ * blocksize since we don't have to follow what the hardware does. --=20 2.17.1