From nobody Tue Feb 10 16:27:00 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153020695837124.5422832628052; Thu, 28 Jun 2018 10:29:18 -0700 (PDT) Received: from localhost ([::1]:37766 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYajL-0000Fs-Fr for importer@patchew.org; Thu, 28 Jun 2018 13:29:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33124) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYahJ-0007QL-3i for qemu-devel@nongnu.org; Thu, 28 Jun 2018 13:27:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYahH-0003uI-JA for qemu-devel@nongnu.org; Thu, 28 Jun 2018 13:27:09 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:44830 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fYahH-0003tI-Dl for qemu-devel@nongnu.org; Thu, 28 Jun 2018 13:27:07 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id EFC4D8182D1F; Thu, 28 Jun 2018 17:27:06 +0000 (UTC) Received: from localhost (unknown [10.36.112.11]) by smtp.corp.redhat.com (Postfix) with ESMTP id 523EA111CB9A; Thu, 28 Jun 2018 17:27:02 +0000 (UTC) From: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 19:26:55 +0200 Message-Id: <20180628172657.11646-3-marcandre.lureau@redhat.com> In-Reply-To: <20180628172657.11646-1-marcandre.lureau@redhat.com> References: <20180628172657.11646-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Thu, 28 Jun 2018 17:27:07 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Thu, 28 Jun 2018 17:27:07 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'marcandre.lureau@redhat.com' RCPT:'' Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [PATCH v6 2/4] tpm: implement virtual memory device for TPM PPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , "Michael S. Tsirkin" , stefanb@linux.vnet.ibm.com, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Igor Mammedov , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Stefan Berger Implement a virtual memory device for the TPM Physical Presence interface. The memory is located at 0xFED45000 and used by ACPI to send messages to the firmware (BIOS) and by the firmware to provide parameters for each one of the supported codes. This device should be used by all TPM interfaces on x86 and can be added by calling tpm_ppi_init_io(). Note: bios_linker cannot be used to allocate the PPI memory region, since the reserved memory should stay stable across reboots, and might be needed before the ACPI tables are installed. Signed-off-by: Stefan Berger Signed-off-by: Marc-Andr=C3=A9 Lureau --- v5 (Marc-Andr=C3=A9): - replace mmio region with ram v4 (Marc-Andr=C3=A9): - pass TPM_PPI_ADDR_BASE as argument to tpm_ppi_init_io() - only enable PPI if property is set v3 (Marc-Andr=C3=A9): - merge CRB support - use trace events instead of DEBUG printf - headers inclusion simplification v2: - moved to byte access since an infrequently used device; this simplifies code - increase size of device to 0x400 - move device to 0xfffef000 since SeaBIOS has some code at 0xffff0000: 'On the emulators, the bios at 0xf0000 is also at 0xffff0000' --- hw/tpm/tpm_ppi.h | 25 +++++++++++++++++++++++++ include/hw/acpi/tpm.h | 6 ++++++ hw/tpm/tpm_crb.c | 8 ++++++++ hw/tpm/tpm_ppi.c | 33 +++++++++++++++++++++++++++++++++ hw/tpm/tpm_tis.c | 8 ++++++++ hw/tpm/Makefile.objs | 2 +- hw/tpm/trace-events | 4 ++++ 7 files changed, 85 insertions(+), 1 deletion(-) create mode 100644 hw/tpm/tpm_ppi.h create mode 100644 hw/tpm/tpm_ppi.c diff --git a/hw/tpm/tpm_ppi.h b/hw/tpm/tpm_ppi.h new file mode 100644 index 0000000000..10e760fdd5 --- /dev/null +++ b/hw/tpm/tpm_ppi.h @@ -0,0 +1,25 @@ +/* + * TPM Physical Presence Interface + * + * Copyright (C) 2018 IBM Corporation + * + * Authors: + * Stefan Berger + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ +#ifndef TPM_TPM_PPI_H +#define TPM_TPM_PPI_H + +#include "hw/acpi/tpm.h" +#include "exec/address-spaces.h" + +typedef struct TPMPPI { + MemoryRegion ram; +} TPMPPI; + +bool tpm_ppi_init(TPMPPI *tpmppi, struct MemoryRegion *m, + hwaddr addr, Object *obj, Error **errp); + +#endif /* TPM_TPM_PPI_H */ diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h index 46ac4dc581..c082df7d1d 100644 --- a/include/hw/acpi/tpm.h +++ b/include/hw/acpi/tpm.h @@ -187,4 +187,10 @@ REG32(CRB_DATA_BUFFER, 0x80) #define TPM2_START_METHOD_MMIO 6 #define TPM2_START_METHOD_CRB 7 =20 +/* + * Physical Presence Interface + */ +#define TPM_PPI_ADDR_SIZE 0x400 +#define TPM_PPI_ADDR_BASE 0xFED45000 + #endif /* HW_ACPI_TPM_H */ diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index d5b0ac5920..b243222fd6 100644 --- a/hw/tpm/tpm_crb.c +++ b/hw/tpm/tpm_crb.c @@ -29,6 +29,7 @@ #include "sysemu/reset.h" #include "tpm_int.h" #include "tpm_util.h" +#include "tpm_ppi.h" #include "trace.h" =20 typedef struct CRBState { @@ -43,6 +44,7 @@ typedef struct CRBState { size_t be_buffer_size; =20 bool ppi_enabled; + TPMPPI ppi; } CRBState; =20 #define CRB(obj) OBJECT_CHECK(CRBState, (obj), TYPE_TPM_CRB) @@ -294,6 +296,12 @@ static void tpm_crb_realize(DeviceState *dev, Error **= errp) memory_region_add_subregion(get_system_memory(), TPM_CRB_ADDR_BASE + sizeof(s->regs), &s->cmdmem); =20 + if (s->ppi_enabled && + !tpm_ppi_init(&s->ppi, get_system_memory(), + TPM_PPI_ADDR_BASE, OBJECT(s), errp)) { + return; + } + qemu_register_reset(tpm_crb_reset, dev); } =20 diff --git a/hw/tpm/tpm_ppi.c b/hw/tpm/tpm_ppi.c new file mode 100644 index 0000000000..987daf099f --- /dev/null +++ b/hw/tpm/tpm_ppi.c @@ -0,0 +1,33 @@ +/* + * tpm_ppi.c - TPM Physical Presence Interface + * + * Copyright (C) 2018 IBM Corporation + * + * Authors: + * Stefan Berger + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" + +#include "qapi/error.h" +#include "tpm_ppi.h" + +bool tpm_ppi_init(TPMPPI *tpmppi, struct MemoryRegion *m, + hwaddr addr, Object *obj, Error **errp) +{ + Error *err =3D NULL; + + memory_region_init_ram(&tpmppi->ram, obj, "tpm-ppi", + TPM_PPI_ADDR_SIZE, &err); + if (err) { + error_propagate(errp, err); + return false; + } + + memory_region_add_subregion(m, addr, &tpmppi->ram); + return true; +} diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c index d9ddf9b723..70432ffe8b 100644 --- a/hw/tpm/tpm_tis.c +++ b/hw/tpm/tpm_tis.c @@ -31,6 +31,7 @@ #include "sysemu/tpm_backend.h" #include "tpm_int.h" #include "tpm_util.h" +#include "tpm_ppi.h" #include "trace.h" =20 #define TPM_TIS_NUM_LOCALITIES 5 /* per spec */ @@ -83,6 +84,7 @@ typedef struct TPMState { size_t be_buffer_size; =20 bool ppi_enabled; + TPMPPI ppi; } TPMState; =20 #define TPM(obj) OBJECT_CHECK(TPMState, (obj), TYPE_TPM_TIS) @@ -979,6 +981,12 @@ static void tpm_tis_realizefn(DeviceState *dev, Error = **errp) =20 memory_region_add_subregion(isa_address_space(ISA_DEVICE(dev)), TPM_TIS_ADDR_BASE, &s->mmio); + + if (s->ppi_enabled && + !tpm_ppi_init(&s->ppi, isa_address_space(ISA_DEVICE(dev)), + TPM_PPI_ADDR_BASE, OBJECT(s), errp)) { + return; + } } =20 static void tpm_tis_initfn(Object *obj) diff --git a/hw/tpm/Makefile.objs b/hw/tpm/Makefile.objs index 1dc9f8bf2c..eedd8b6858 100644 --- a/hw/tpm/Makefile.objs +++ b/hw/tpm/Makefile.objs @@ -1,4 +1,4 @@ -common-obj-y +=3D tpm_util.o +common-obj-y +=3D tpm_util.o tpm_ppi.o common-obj-$(CONFIG_TPM_TIS) +=3D tpm_tis.o common-obj-$(CONFIG_TPM_CRB) +=3D tpm_crb.o common-obj-$(CONFIG_TPM_PASSTHROUGH) +=3D tpm_passthrough.o diff --git a/hw/tpm/trace-events b/hw/tpm/trace-events index 25bee0cecf..81f9923401 100644 --- a/hw/tpm/trace-events +++ b/hw/tpm/trace-events @@ -8,6 +8,10 @@ tpm_crb_mmio_write(uint64_t addr, unsigned size, uint32_t = val) "CRB write 0x" TA tpm_passthrough_handle_request(void *cmd) "processing command %p" tpm_passthrough_reset(void) "reset" =20 +# hw/tpm/tpm_ppi.c +tpm_ppi_mmio_read(uint64_t addr, unsigned size, uint32_t val) "PPI read 0x= " TARGET_FMT_plx " len:%u val: 0x%" PRIx32 +tpm_ppi_mmio_write(uint64_t addr, unsigned size, uint32_t val) "PPI write = 0x" TARGET_FMT_plx " len:%u val: 0x%" PRIx32 + # hw/tpm/tpm_util.c tpm_util_get_buffer_size_hdr_len(uint32_t len, size_t expected) "tpm_resp-= >hdr.len =3D %u, expected =3D %zu" tpm_util_get_buffer_size_len(uint32_t len, size_t expected) "tpm_resp->len= =3D %u, expected =3D %zu" --=20 2.18.0.rc1