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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+cJgkwx/ep9kNHhp/NZWR+Qsl0Zh1HJMnithEE7rNEI=; b=XdghUrcA3PUsKTeIIO/xXyJjYMeUpMiU5gx5HCuxt5D+VtENUNoGXuWFbs83Z8KZvb WmGnm5pCA90Xm84cIlIGeL+ojzFySJyCAZXATTUE/E4+gR3c6GC+O2n2ABt6KYHbZoi2 LuGOjHx5aQvmeeILYJsreFzqpzDfZR2zOI1cA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+cJgkwx/ep9kNHhp/NZWR+Qsl0Zh1HJMnithEE7rNEI=; b=mRIRd3yN3Roh0qDVr5wS7VvshiKa2H0UC0oqIkkxSBB44zwV18fngLgHbM9y2rrr69 f9S651JF+cQVz+UOoDr9+XwGy55ZvHb6h7+8dTBA9zK4K+glu4yUo6P/UBi/pKBtn/Ex +5NgwNag1guMfXt6mj5omDZLUDnvJg3xmPvIkyO9GHG9fNTQJ19zgemytrMyvze7pPHx sBvZASqBUWMdoCAGVC5O8/SAUnS7y9GIaBXkXNGhaANvKngvNyaZf08hjzop3om7iz4W se1I9gJJ0waBCYMn4Luf6FF9glV4XG+uatkOkpE1W39UlX4o3gYtY24RHMMut19v5WEN Ydrg== X-Gm-Message-State: APt69E2AD+cA/oh/em0o7ILPZApDUMnW/1VArtJokgabMtx3/zjGKCGE XOxyoT5Lq9fTFkhcD6Gaxy/wTa+Abu8= X-Google-Smtp-Source: ADUXVKInZebU6zQpOdsEf6mGoooBdNdw0EDxIDqP7qWhzhuSQrQk98ZpQzq4OuUW4Fksf2STZzMUnA== X-Received: by 2002:a17:902:8d91:: with SMTP id v17-v6mr8773071plo.9.1530155022151; Wed, 27 Jun 2018 20:03:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:14 -0700 Message-Id: <20180628030330.15615-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::230 Subject: [Qemu-devel] [PATCH v3 07/23] target/openrisc: Link more translation blocks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Track direct jumps via dc->jmp_pc_imm. Use that in preference to jmp_pc when possible. Emit goto_tb in that case, and lookup_and_goto_tb otherwise. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 96 +++++++++++++++++++++---------------- 1 file changed, 55 insertions(+), 41 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 22848b17ad..a618d39242 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -38,13 +38,16 @@ =20 /* is_jmp field values */ #define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */ -#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_JUMP DISAS_TARGET_1 /* exit via jmp_pc/jmp_pc_imm */ =20 typedef struct DisasContext { DisasContextBase base; uint32_t mem_idx; uint32_t tb_flags; uint32_t delayed_branch; + + /* If not -1, jmp_pc contains this value and so is a direct jump. */ + target_ulong jmp_pc_imm; } DisasContext; =20 /* Include the auto-generated decoder. */ @@ -160,34 +163,6 @@ static void check_ov64s(DisasContext *dc) } \ } while (0) =20 -static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) -{ - if (unlikely(dc->base.singlestep_enabled)) { - return false; - } - -#ifndef CONFIG_USER_ONLY - return (dc->base.tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE= _MASK); -#else - return true; -#endif -} - -static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) -{ - if (use_goto_tb(dc, dest)) { - tcg_gen_movi_tl(cpu_pc, dest); - tcg_gen_goto_tb(n); - tcg_gen_exit_tb(dc->base.tb, n); - } else { - tcg_gen_movi_tl(cpu_pc, dest); - if (dc->base.singlestep_enabled) { - gen_exception(dc, EXCP_DEBUG); - } - tcg_gen_exit_tb(NULL, 0); - } -} - static void gen_ove_cy(DisasContext *dc) { if (dc->tb_flags & SR_OVE) { @@ -621,6 +596,7 @@ static bool trans_l_j(DisasContext *dc, arg_l_j *a, uin= t32_t insn) target_ulong tmp_pc =3D dc->base.pc_next + a->n * 4; =20 tcg_gen_movi_tl(jmp_pc, tmp_pc); + dc->jmp_pc_imm =3D tmp_pc; dc->delayed_branch =3D 2; return true; } @@ -634,6 +610,7 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a,= uint32_t insn) /* Optimize jal being used to load the PC for PIC. */ if (tmp_pc !=3D ret_pc) { tcg_gen_movi_tl(jmp_pc, tmp_pc); + dc->jmp_pc_imm =3D tmp_pc; dc->delayed_branch =3D 2; } return true; @@ -1267,6 +1244,8 @@ static void openrisc_tr_init_disas_context(DisasConte= xtBase *dcb, CPUState *cs) dc->mem_idx =3D cpu_mmu_index(env, false); dc->tb_flags =3D dc->base.tb->flags; dc->delayed_branch =3D (dc->tb_flags & TB_FLAGS_DFLAG) !=3D 0; + dc->jmp_pc_imm =3D -1; + bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns =3D MIN(dc->base.max_insns, bound); } @@ -1319,37 +1298,72 @@ static void openrisc_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cs) } dc->base.pc_next +=3D 4; =20 - /* delay slot */ - if (dc->delayed_branch) { - dc->delayed_branch--; - if (!dc->delayed_branch) { - tcg_gen_mov_tl(cpu_pc, jmp_pc); - tcg_gen_discard_tl(jmp_pc); - dc->base.is_jmp =3D DISAS_UPDATE; - return; - } + /* When exiting the delay slot normally, exit via jmp_pc. + * For DISAS_NORETURN, we have raised an exception and already exited. + * For DISAS_EXIT, we found l.rfe in a delay slot. There's nothing + * in the manual saying this is illegal, but it surely it should. + * At least or1ksim overrides pcnext and ignores the branch. + */ + if (dc->delayed_branch + && --dc->delayed_branch =3D=3D 0 + && dc->base.is_jmp =3D=3D DISAS_NEXT) { + dc->base.is_jmp =3D DISAS_JUMP; } } =20 static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong jmp_dest; =20 /* If we have already exited the TB, nothing following has effect. */ if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { return; } =20 + /* Adjust the delayed branch state for the next TB. */ if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) !=3D (dc->delayed_branch != =3D 0)) { tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch !=3D 0); } =20 - tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4); + /* For DISAS_TOO_MANY, jump to the next insn. */ + jmp_dest =3D dc->base.pc_next; + tcg_gen_movi_tl(cpu_ppc, jmp_dest - 4); + switch (dc->base.is_jmp) { + case DISAS_JUMP: + jmp_dest =3D dc->jmp_pc_imm; + if (jmp_dest =3D=3D -1) { + /* The jump destination is indirect/computed; use jmp_pc. */ + tcg_gen_mov_tl(cpu_pc, jmp_pc); + tcg_gen_discard_tl(jmp_pc); + if (unlikely(dc->base.singlestep_enabled)) { + gen_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_lookup_and_goto_ptr(); + } + break; + } + /* The jump destination is direct; use jmp_pc_imm. + However, we will have stored into jmp_pc as well; + we know now that it wasn't needed. */ + tcg_gen_discard_tl(jmp_pc); + /* fallthru */ + case DISAS_TOO_MANY: - gen_goto_tb(dc, 0, dc->base.pc_next); + if (unlikely(dc->base.singlestep_enabled)) { + tcg_gen_movi_tl(cpu_pc, jmp_dest); + gen_exception(dc, EXCP_DEBUG); + } else if ((dc->base.pc_first ^ jmp_dest) & TARGET_PAGE_MASK) { + tcg_gen_movi_tl(cpu_pc, jmp_dest); + tcg_gen_lookup_and_goto_ptr(); + } else { + tcg_gen_goto_tb(0); + tcg_gen_movi_tl(cpu_pc, jmp_dest); + tcg_gen_exit_tb(dc->base.tb, 0); + } break; - case DISAS_UPDATE: + case DISAS_EXIT: if (unlikely(dc->base.singlestep_enabled)) { gen_exception(dc, EXCP_DEBUG); --=20 2.17.1