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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id p20-v6sm4577638pff.90.2018.06.26.21.33.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 21:33:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iG8HT096URRb4CWAiRTwQ1cVUSLxVdPPA37onBhzXoI=; b=JIOKqtY0fKjngKNtOnlNhv3HvytEvRnFMUiFqNTwwkTmTNbQjz6LQEopDhUjljOdqQ vTlJTwrQVwyFMNdyd0eRza2CYn2mi/5Aut8UMz/tkd4Wm0dAhiMxkr5CNeU0KUGDi7wR qw/bsn3EIjk7zCXyZuTO84Xj0VsrUIESOY1/g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iG8HT096URRb4CWAiRTwQ1cVUSLxVdPPA37onBhzXoI=; b=sRQc1uKaZs2Ax7+Q1DTanFNhznrWaLyRMx4zO2l3bqUcbbU+96SxndZfIiCDd63C1e By8VjvptEBit1UkLmo0C3K2888GDwqLuJGSRFt70+CBJP4Hn3sW8KZm0nKTClUZi5yH6 bhRWp50CWbrwTQR0gV/27aWetl0yVsxcrbzuRrMQv7/j7C6QKV0SUfCgcZfZ7OJ2qa9t XHi2yF/fdn7mS5KZmEXvQm3dAsmMlwCQfEjpxH/QW6hmvhKwuSJqcOoTcVybChdyxbiG VhS2HgjsV158pLlE5+kukCUvy0Bt9d7AoYkp9k/2ct34194vDlINFdKCc3PCz8aGyeod rfow== X-Gm-Message-State: APt69E2GRTaoE9In5YpCP7w3t9PqQOecNRJU7ZtEFe0RV6JrH6BPDU1C pIKgUxWp1O0qUlPDvdlFZ6wNhTKy2WY= X-Google-Smtp-Source: AAOMgpcTHi4hvBYBUc2nqzK/lvdeYlmSIDOhe6Tv0ilBf9kgs+0SPKy1+ph7UdmbrFjMPM7K99pQ8g== X-Received: by 2002:a62:f705:: with SMTP id h5-v6mr4290259pfi.169.1530074022520; Tue, 26 Jun 2018 21:33:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 21:33:01 -0700 Message-Id: <20180627043328.11531-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180627043328.11531-1-richard.henderson@linaro.org> References: <20180627043328.11531-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::236 Subject: [Qemu-devel] [PATCH v6 08/35] target/arm: Implement SVE Floating Point Accumulating Reduction Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 7 +++++ target/arm/sve_helper.c | 56 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 45 ++++++++++++++++++++++++++++++ target/arm/sve.decode | 5 ++++ 4 files changed, 113 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index eb0645dd43..68e55a8d03 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -720,6 +720,13 @@ DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(sve_fadda_h, TCG_CALL_NO_RWG, + i64, i64, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_fadda_s, TCG_CALL_NO_RWG, + i64, i64, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_fadda_d, TCG_CALL_NO_RWG, + i64, i64, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_6(sve_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_6(sve_fadd_s, TCG_CALL_NO_RWG, diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 2f416e5e28..2d08b7dcd3 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -2811,6 +2811,62 @@ uint32_t HELPER(sve_while)(void *vd, uint32_t count,= uint32_t pred_desc) return predtest_ones(d, oprsz, esz_mask); } =20 +uint64_t HELPER(sve_fadda_h)(uint64_t nn, void *vm, void *vg, + void *status, uint32_t desc) +{ + intptr_t i =3D 0, opr_sz =3D simd_oprsz(desc); + float16 result =3D nn; + + do { + uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); + do { + if (pg & 1) { + float16 mm =3D *(float16 *)(vm + H1_2(i)); + result =3D float16_add(result, mm, status); + } + i +=3D sizeof(float16), pg >>=3D sizeof(float16); + } while (i & 15); + } while (i < opr_sz); + + return result; +} + +uint64_t HELPER(sve_fadda_s)(uint64_t nn, void *vm, void *vg, + void *status, uint32_t desc) +{ + intptr_t i =3D 0, opr_sz =3D simd_oprsz(desc); + float32 result =3D nn; + + do { + uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); + do { + if (pg & 1) { + float32 mm =3D *(float32 *)(vm + H1_2(i)); + result =3D float32_add(result, mm, status); + } + i +=3D sizeof(float32), pg >>=3D sizeof(float32); + } while (i & 15); + } while (i < opr_sz); + + return result; +} + +uint64_t HELPER(sve_fadda_d)(uint64_t nn, void *vm, void *vg, + void *status, uint32_t desc) +{ + intptr_t i =3D 0, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *m =3D vm; + uint8_t *pg =3D vg; + + for (i =3D 0; i < opr_sz; i++) { + if (pg[H1(i)] & 1) { + nn =3D float64_add(nn, m[i], status); + } + } + + return nn; +} + /* Fully general three-operand expander, controlled by a predicate, * With the extra float_status parameter. */ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index acad6374ef..483ad33179 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3383,6 +3383,51 @@ DO_ZZI(UMIN, umin) =20 #undef DO_ZZI =20 +/* + *** SVE Floating Point Accumulating Reduction Group + */ + +static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a, uint32_t insn) +{ + typedef void fadda_fn(TCGv_i64, TCGv_i64, TCGv_ptr, + TCGv_ptr, TCGv_ptr, TCGv_i32); + static fadda_fn * const fns[3] =3D { + gen_helper_sve_fadda_h, + gen_helper_sve_fadda_s, + gen_helper_sve_fadda_d, + }; + unsigned vsz =3D vec_full_reg_size(s); + TCGv_ptr t_rm, t_pg, t_fpst; + TCGv_i64 t_val; + TCGv_i32 t_desc; + + if (a->esz =3D=3D 0) { + return false; + } + if (!sve_access_check(s)) { + return true; + } + + t_val =3D load_esz(cpu_env, vec_reg_offset(s, a->rn, 0, a->esz), a->es= z); + t_rm =3D tcg_temp_new_ptr(); + t_pg =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm)); + tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); + t_fpst =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + t_desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); + + fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc); + + tcg_temp_free_i32(t_desc); + tcg_temp_free_ptr(t_fpst); + tcg_temp_free_ptr(t_pg); + tcg_temp_free_ptr(t_rm); + + write_fp_dreg(s, a->rd, t_val); + tcg_temp_free_i64(t_val); + return true; +} + /* *** SVE Floating Point Arithmetic - Unpredicated Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index e8531e28cd..675b81aaa0 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -676,6 +676,11 @@ UMIN_zzi 00100101 .. 101 011 110 ........ .....= @rdn_i8u # SVE integer multiply immediate (unpredicated) MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s =20 +### SVE FP Accumulating Reduction Group + +# SVE floating-point serial reduction (predicated) +FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm + ### SVE Floating Point Arithmetic - Unpredicated Group =20 # SVE floating-point arithmetic (unpredicated) --=20 2.17.1