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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id p20-v6sm4577638pff.90.2018.06.26.21.34.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 21:34:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=r45jIobnF+wtoBKzXFQCmSBJ8FmsuLpFIk2TKAlXpxU=; b=idJ00xcqkfipev5FaBl0Bv4pSnx6QzXpkhpn+XRsROXKHe2ZRz2DEYqFDkZkaUbloQ c+ThOR9mczsV6bJVUbiu+170XU74PENysndxc7jdnHByNyN5o9HYpcR+L+r2MCMvGqCC 2mETfakPAe3o7MIy0SfghYcppOVsG+xGfUQIY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=r45jIobnF+wtoBKzXFQCmSBJ8FmsuLpFIk2TKAlXpxU=; b=TOuux+F/ZJbcQwimSl9w+MgYg6bktC/dzXQ9DcO2o6CqiZmf42TEh/njD+8kZ6i7tT On4fzSjhiGWORgfgYtdiSODOInEAIFW535OIZT3Gp/AXhZmo7zUC+tK3wOGEj7i84i8Y VDr/fnpEsSSwGgTb8xr4C4MatV5QQJWh6hLc1VESwqlmNzw42EvjKFRHLI8wPEDZDXe3 2Omb9ib4y9oe3kEBfjkbltXD68cXUQWCX63VRKQ/Uda/9dgmL6o+4XrsuLs1rYbqGW8B pv/FEn2iUl0W9/Dpe4upDsajo5pkUUq3ELiKKHpq1lOLljz/P2OsSl8ScQv8n+oenYuP Fq0g== X-Gm-Message-State: APt69E1QEi2dxVz6099MwrwLB7XAKYyPh3Af+F+IxbveXfKdAOmWy7bp jvka1FQ8k8SsSE3aFs7Rq5nN7QoZeLQ= X-Google-Smtp-Source: ADUXVKJdY9iAO06h2HpEazVTalkBBNjo8LuKEuWZIMuzTqLNrVRA8JeP0LRUhBdMExYUsOipO6Zp0w== X-Received: by 2002:a17:902:722:: with SMTP id 31-v6mr4541650pli.3.1530074053168; Tue, 26 Jun 2018 21:34:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 21:33:23 -0700 Message-Id: <20180627043328.11531-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180627043328.11531-1-richard.henderson@linaro.org> References: <20180627043328.11531-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::233 Subject: [Qemu-devel] [PATCH v6 30/35] target/arm: Pass index to AdvSIMD FCMLA (indexed) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For aa64 advsimd, we had been passing the pre-indexed vector. However, sve applies the index to each 128-bit segment, so we need to pass in the index separately. For aa32 advsimd, the fp32 operation always has index 0, but we failed to interpret the fp16 index correctly. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- v6: * Fix double-indexing in translate-a64.c * Fix non-indexing of fp16 in translate.c. --- target/arm/translate-a64.c | 21 ++++++++++++--------- target/arm/translate.c | 32 +++++++++++++++++++++++--------- target/arm/vec_helper.c | 10 ++++++---- 3 files changed, 41 insertions(+), 22 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8d8a4cecb0..eb3a4ab2f0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -12669,15 +12669,18 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) case 0x13: /* FCMLA #90 */ case 0x15: /* FCMLA #180 */ case 0x17: /* FCMLA #270 */ - tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), - vec_full_reg_offset(s, rn), - vec_reg_offset(s, rm, index, size), fpst, - is_q ? 16 : 8, vec_full_reg_size(s), - extract32(insn, 13, 2), /* rot */ - size =3D=3D MO_64 - ? gen_helper_gvec_fcmlas_idx - : gen_helper_gvec_fcmlah_idx); - tcg_temp_free_ptr(fpst); + { + int rot =3D extract32(insn, 13, 2); + int data =3D (index << 2) | rot; + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), fpst, + is_q ? 16 : 8, vec_full_reg_size(s), data, + size =3D=3D MO_64 + ? gen_helper_gvec_fcmlas_idx + : gen_helper_gvec_fcmlah_idx); + tcg_temp_free_ptr(fpst); + } return; } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 2a3e4f5d4c..a7a980b1f2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7826,26 +7826,42 @@ static int disas_neon_insn_3same_ext(DisasContext *= s, uint32_t insn) =20 static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) { - int rd, rn, rm, rot, size, opr_sz; + gen_helper_gvec_3_ptr *fn_gvec_ptr; + int rd, rn, rm, opr_sz, data; TCGv_ptr fpst; bool q; =20 q =3D extract32(insn, 6, 1); VFP_DREG_D(rd, insn); VFP_DREG_N(rn, insn); - VFP_DREG_M(rm, insn); if ((rd | rn) & q) { return 1; } =20 if ((insn & 0xff000f10) =3D=3D 0xfe000800) { /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */ - rot =3D extract32(insn, 20, 2); - size =3D extract32(insn, 23, 1); - if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) - || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { + int rot =3D extract32(insn, 20, 2); + int size =3D extract32(insn, 23, 1); + int index; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) { return 1; } + if (size =3D=3D 0) { + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + return 1; + } + /* For fp16, rm is just Vm, and index is M. */ + rm =3D extract32(insn, 0, 4); + index =3D extract32(insn, 5, 1); + } else { + /* For fp32, rm is the usual M:Vm, and index is 0. */ + VFP_DREG_M(rm, insn); + index =3D 0; + } + data =3D (index << 2) | rot; + fn_gvec_ptr =3D (size ? gen_helper_gvec_fcmlas_idx + : gen_helper_gvec_fcmlah_idx); } else { return 1; } @@ -7864,9 +7880,7 @@ static int disas_neon_insn_2reg_scalar_ext(DisasConte= xt *s, uint32_t insn) tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), vfp_reg_offset(1, rn), vfp_reg_offset(1, rm), fpst, - opr_sz, opr_sz, rot, - size ? gen_helper_gvec_fcmlas_idx - : gen_helper_gvec_fcmlah_idx); + opr_sz, opr_sz, data, fn_gvec_ptr); tcg_temp_free_ptr(fpst); return 0; } diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 073e5c58e7..8f2dc4b989 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -317,10 +317,11 @@ void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void= *vm, float_status *fpst =3D vfpst; intptr_t flip =3D extract32(desc, SIMD_DATA_SHIFT, 1); uint32_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); + intptr_t index =3D extract32(desc, SIMD_DATA_SHIFT + 2, 2); uint32_t neg_real =3D flip ^ neg_imag; uintptr_t i; - float16 e1 =3D m[H2(flip)]; - float16 e3 =3D m[H2(1 - flip)]; + float16 e1 =3D m[H2(2 * index + flip)]; + float16 e3 =3D m[H2(2 * index + 1 - flip)]; =20 /* Shift boolean to the sign bit so we can xor to negate. */ neg_real <<=3D 15; @@ -377,10 +378,11 @@ void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void= *vm, float_status *fpst =3D vfpst; intptr_t flip =3D extract32(desc, SIMD_DATA_SHIFT, 1); uint32_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); + intptr_t index =3D extract32(desc, SIMD_DATA_SHIFT + 2, 2); uint32_t neg_real =3D flip ^ neg_imag; uintptr_t i; - float32 e1 =3D m[H4(flip)]; - float32 e3 =3D m[H4(1 - flip)]; + float32 e1 =3D m[H4(2 * index + flip)]; + float32 e3 =3D m[H4(2 * index + 1 - flip)]; =20 /* Shift boolean to the sign bit so we can xor to negate. */ neg_real <<=3D 31; --=20 2.17.1