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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id p20-v6sm4577638pff.90.2018.06.26.21.34.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 21:34:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jLi5kdXWigewkTKucYfYsu8zvwTxz4aJuC7qXtngMOQ=; b=GhdOHjFYVgRUMkS6M7sRvhqp3XKkXgR70riE4PCAKKRi2qW6NQdd7XtsUQb4eAunCu bwKcdZuSn0VyUqRF7O6VjoiLsemR/6HF7RUGeKj9shZsrZzggNVFgZYqVnK5320jVY59 L5i2SCZThddkhIe/qMnaAluXspX6XW1deNV0Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jLi5kdXWigewkTKucYfYsu8zvwTxz4aJuC7qXtngMOQ=; b=C5p0o4aLr9e0+FsveJO5US4a9JhWchl0LiclBN2RH6MM6w7F2sBfeFOtys50pLVwRb pWUxLaZxWF9tfbkIRZ7ffZ6Rq+hnlZGOM/FEYynNJW4gXAwjX0l/1JNoTkebhH4olXFX oX9liJVddZ4Sh6548yysyG3uXLcKLQkhF5J5LUg5Mwe7T3OrppzhpYbDT0HuDEObfQv9 E6Po3RrEQ2Q1ROv96aA6Q0x4bDa//hHMzoOPXXLonAsUoQuIo4FLUoIwybkKfesHwMav RX5WsuLJmkNMKIW/RETMPmpCpCVG3VpZx2r9MtKYMXgLyoIvSEx0kJvzfdmhqa7hC6N4 tduQ== X-Gm-Message-State: APt69E28w/Nrqnuz94ZWjd909op6rqp0uTYgqU0O54ed+4s09BZjbU8y g4vsN7uS9BRI4gcxIl0Wzx1XQhIsCTg= X-Google-Smtp-Source: ADUXVKIUTNm2VxT/lm/W6tB1ngZt7T5/R5pzN2Pgib8A644aRxjvqGjMZnf9tXfg91jzr5JJbA/2KA== X-Received: by 2002:a65:6689:: with SMTP id b9-v6mr3747646pgw.326.1530074049246; Tue, 26 Jun 2018 21:34:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 21:33:20 -0700 Message-Id: <20180627043328.11531-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180627043328.11531-1-richard.henderson@linaro.org> References: <20180627043328.11531-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v6 27/35] target/arm: Implement SVE MOVPRFX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v6: Fix comment typos --- target/arm/translate-sve.c | 60 +++++++++++++++++++++++++++++++++++++- target/arm/sve.decode | 7 +++++ 2 files changed, 66 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index ff8ae67e2b..4883de3fab 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -351,6 +351,23 @@ static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz = *a, gen_helper_gvec_4 *fn) return true; } =20 +/* Select active elememnts from Zn and inactive elements from Zm, + * storing the result in Zd. + */ +static void do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int = esz) +{ + static gen_helper_gvec_4 * const fns[4] =3D { + gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h, + gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d + }; + unsigned vsz =3D vec_full_reg_size(s); + tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + pred_full_reg_offset(s, pg), + vsz, vsz, 0, fns[esz]); +} + #define DO_ZPZZ(NAME, name) \ static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a, \ uint32_t insn) \ @@ -401,7 +418,13 @@ static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_= esz *a, uint32_t insn) return do_zpzz_ool(s, a, fns[a->esz]); } =20 -DO_ZPZZ(SEL, sel) +static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn) +{ + if (sve_access_check(s)) { + do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz); + } + return true; +} =20 #undef DO_ZPZZ =20 @@ -5035,3 +5058,38 @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr= *a, uint32_t insn) sve_access_check(s); return true; } + +/* + * Move Prefix + * + * TODO: The implementation so far could handle predicated merging movprfx. + * The helper functions as written take an extra source register to + * use in the operation, but the result is only written when predication + * succeeds. For unpredicated movprfx, we need to rearrange the helpers + * to allow the final write back to the destination to be unconditional. + * For predicated zeroing movprfx, we need to rearrange the helpers to + * allow the final write back to zero inactives. + * + * In the meantime, just emit the moves. + */ + +static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a, uint32_t insn) +{ + return do_mov_z(s, a->rd, a->rn); +} + +static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + if (sve_access_check(s)) { + do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz); + } + return true; +} + +static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + if (sve_access_check(s)) { + do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz); + } + return true; +} diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 2aca9f0bb0..c725ee2584 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -270,6 +270,10 @@ ORV 00000100 .. 011 000 001 ... ..... ....= . @rd_pg_rn EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn =20 +# SVE constructive prefix (predicated) +MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn +MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn + # SVE integer add reduction (predicated) # Note that saddv requires size !=3D 3. UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn @@ -418,6 +422,9 @@ ADR_p64 00000100 11 1 ..... 1010 .. ..... .....= @rd_rn_msz_rm =20 ### SVE Integer Misc - Unpredicated Group =20 +# SVE constructive prefix (unpredicated) +MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5 + # SVE floating-point exponential accelerator # Note esz !=3D 0 FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn --=20 2.17.1