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From: Peter Maydell <peter.maydell@linaro.org>
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Subject: [Qemu-devel] [PULL 27/32] hw/arm/smmuv3: Cache/invalidate config
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From: Eric Auger <eric.auger@redhat.com>
Let's cache config data to avoid fetching and parsing STE/CD
structures on each translation. We invalidate them on data structure
invalidation commands.
We put in place a per-smmu mutex to protect the config cache. This
will be useful too to protect the IOTLB cache. The caches can be
accessed without BQL, ie. in IO dataplane. The same kind of mutex was
put in place in the intel viommu.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1529653501-15358-3-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/smmu-common.h | 5 ++
include/hw/arm/smmuv3.h | 1 +
hw/arm/smmu-common.c | 24 ++++++-
hw/arm/smmuv3.c | 135 +++++++++++++++++++++++++++++++++--
hw/arm/trace-events | 6 ++
5 files changed, 164 insertions(+), 7 deletions(-)
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index c41eb5c3b00..7ce95ca0dcb 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -75,6 +75,8 @@ typedef struct SMMUDevice {
int devfn;
IOMMUMemoryRegion iommu;
AddressSpace as;
+ uint32_t cfg_cache_hits;
+ uint32_t cfg_cache_misses;
} SMMUDevice;
=20
typedef struct SMMUNotifierNode {
@@ -142,4 +144,7 @@ int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUA=
ccessFlags perm,
*/
SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova);
=20
+/* Return the iommu mr associated to @sid, or NULL if none */
+IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);
+
#endif /* HW_ARM_SMMU_COMMON */
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
index 23f70363e54..36b2f452539 100644
--- a/include/hw/arm/smmuv3.h
+++ b/include/hw/arm/smmuv3.h
@@ -59,6 +59,7 @@ typedef struct SMMUv3State {
SMMUQueue eventq, cmdq;
=20
qemu_irq irq[4];
+ QemuMutex mutex;
} SMMUv3State;
=20
typedef enum {
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index 3c5f7245b52..db242c73dfb 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -310,6 +310,24 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, voi=
d *opaque, int devfn)
return &sdev->as;
}
=20
+IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid)
+{
+ uint8_t bus_n, devfn;
+ SMMUPciBus *smmu_bus;
+ SMMUDevice *smmu;
+
+ bus_n =3D PCI_BUS_NUM(sid);
+ smmu_bus =3D smmu_find_smmu_pcibus(s, bus_n);
+ if (smmu_bus) {
+ devfn =3D sid & 0x7;
+ smmu =3D smmu_bus->pbdev[devfn];
+ if (smmu) {
+ return &smmu->iommu;
+ }
+ }
+ return NULL;
+}
+
static void smmu_base_realize(DeviceState *dev, Error **errp)
{
SMMUState *s =3D ARM_SMMU(dev);
@@ -321,7 +339,7 @@ static void smmu_base_realize(DeviceState *dev, Error *=
*errp)
error_propagate(errp, local_err);
return;
}
-
+ s->configs =3D g_hash_table_new_full(NULL, NULL, NULL, g_free);
s->smmu_pcibus_by_busptr =3D g_hash_table_new(NULL, NULL);
=20
if (s->primary_bus) {
@@ -333,7 +351,9 @@ static void smmu_base_realize(DeviceState *dev, Error *=
*errp)
=20
static void smmu_base_reset(DeviceState *dev)
{
- /* will be filled later on */
+ SMMUState *s =3D ARM_SMMU(dev);
+
+ g_hash_table_remove_all(s->configs);
}
=20
static Property smmu_dev_properties[] =3D {
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 70b8f295aa9..df704c26f8a 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -544,6 +544,58 @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr,=
SMMUTransCfg *cfg,
return decode_cd(cfg, &cd, event);
}
=20
+/**
+ * smmuv3_get_config - Look up for a cached copy of configuration data for
+ * @sdev and on cache miss performs a configuration structure decoding from
+ * guest RAM.
+ *
+ * @sdev: SMMUDevice handle
+ * @event: output event info
+ *
+ * The configuration cache contains data resulting from both STE and CD
+ * decoding under the form of an SMMUTransCfg struct. The hash table is in=
dexed
+ * by the SMMUDevice handle.
+ */
+static SMMUTransCfg *smmuv3_get_config(SMMUDevice *sdev, SMMUEventInfo *ev=
ent)
+{
+ SMMUv3State *s =3D sdev->smmu;
+ SMMUState *bc =3D &s->smmu_state;
+ SMMUTransCfg *cfg;
+
+ cfg =3D g_hash_table_lookup(bc->configs, sdev);
+ if (cfg) {
+ sdev->cfg_cache_hits++;
+ trace_smmuv3_config_cache_hit(smmu_get_sid(sdev),
+ sdev->cfg_cache_hits, sdev->cfg_cache_misses,
+ 100 * sdev->cfg_cache_hits /
+ (sdev->cfg_cache_hits + sdev->cfg_cache_misses=
));
+ } else {
+ sdev->cfg_cache_misses++;
+ trace_smmuv3_config_cache_miss(smmu_get_sid(sdev),
+ sdev->cfg_cache_hits, sdev->cfg_cache_misses,
+ 100 * sdev->cfg_cache_hits /
+ (sdev->cfg_cache_hits + sdev->cfg_cache_misses=
));
+ cfg =3D g_new0(SMMUTransCfg, 1);
+
+ if (!smmuv3_decode_config(&sdev->iommu, cfg, event)) {
+ g_hash_table_insert(bc->configs, sdev, cfg);
+ } else {
+ g_free(cfg);
+ cfg =3D NULL;
+ }
+ }
+ return cfg;
+}
+
+static void smmuv3_flush_config(SMMUDevice *sdev)
+{
+ SMMUv3State *s =3D sdev->smmu;
+ SMMUState *bc =3D &s->smmu_state;
+
+ trace_smmuv3_config_cache_inv(smmu_get_sid(sdev));
+ g_hash_table_remove(bc->configs, sdev);
+}
+
static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
IOMMUAccessFlags flag, int iommu_idx)
{
@@ -553,7 +605,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion=
*mr, hwaddr addr,
SMMUEventInfo event =3D {.type =3D SMMU_EVT_NONE, .sid =3D sid};
SMMUPTWEventInfo ptw_info =3D {};
SMMUTranslationStatus status;
- SMMUTransCfg cfg =3D {};
+ SMMUTransCfg *cfg =3D NULL;
IOMMUTLBEntry entry =3D {
.target_as =3D &address_space_memory,
.iova =3D addr,
@@ -562,27 +614,30 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegi=
on *mr, hwaddr addr,
.perm =3D IOMMU_NONE,
};
=20
+ qemu_mutex_lock(&s->mutex);
+
if (!smmu_enabled(s)) {
status =3D SMMU_TRANS_DISABLE;
goto epilogue;
}
=20
- if (smmuv3_decode_config(mr, &cfg, &event)) {
+ cfg =3D smmuv3_get_config(sdev, &event);
+ if (!cfg) {
status =3D SMMU_TRANS_ERROR;
goto epilogue;
}
=20
- if (cfg.aborted) {
+ if (cfg->aborted) {
status =3D SMMU_TRANS_ABORT;
goto epilogue;
}
=20
- if (cfg.bypassed) {
+ if (cfg->bypassed) {
status =3D SMMU_TRANS_BYPASS;
goto epilogue;
}
=20
- if (smmu_ptw(&cfg, addr, flag, &entry, &ptw_info)) {
+ if (smmu_ptw(cfg, addr, flag, &entry, &ptw_info)) {
switch (ptw_info.type) {
case SMMU_PTW_ERR_WALK_EABT:
event.type =3D SMMU_EVT_F_WALK_EABT;
@@ -628,6 +683,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion=
*mr, hwaddr addr,
}
=20
epilogue:
+ qemu_mutex_unlock(&s->mutex);
switch (status) {
case SMMU_TRANS_SUCCESS:
entry.perm =3D flag;
@@ -664,6 +720,7 @@ epilogue:
=20
static int smmuv3_cmdq_consume(SMMUv3State *s)
{
+ SMMUState *bs =3D ARM_SMMU(s);
SMMUCmdError cmd_error =3D SMMU_CERROR_NONE;
SMMUQueue *q =3D &s->cmdq;
SMMUCommandType type =3D 0;
@@ -698,6 +755,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
=20
trace_smmuv3_cmdq_opcode(smmu_cmd_string(type));
=20
+ qemu_mutex_lock(&s->mutex);
switch (type) {
case SMMU_CMD_SYNC:
if (CMD_SYNC_CS(&cmd) & CMD_SYNC_SIG_IRQ) {
@@ -706,10 +764,74 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
break;
case SMMU_CMD_PREFETCH_CONFIG:
case SMMU_CMD_PREFETCH_ADDR:
+ break;
case SMMU_CMD_CFGI_STE:
+ {
+ uint32_t sid =3D CMD_SID(&cmd);
+ IOMMUMemoryRegion *mr =3D smmu_iommu_mr(bs, sid);
+ SMMUDevice *sdev;
+
+ if (CMD_SSEC(&cmd)) {
+ cmd_error =3D SMMU_CERROR_ILL;
+ break;
+ }
+
+ if (!mr) {
+ break;
+ }
+
+ trace_smmuv3_cmdq_cfgi_ste(sid);
+ sdev =3D container_of(mr, SMMUDevice, iommu);
+ smmuv3_flush_config(sdev);
+
+ break;
+ }
case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */
+ {
+ uint32_t start =3D CMD_SID(&cmd), end, i;
+ uint8_t range =3D CMD_STE_RANGE(&cmd);
+
+ if (CMD_SSEC(&cmd)) {
+ cmd_error =3D SMMU_CERROR_ILL;
+ break;
+ }
+
+ end =3D start + (1 << (range + 1)) - 1;
+ trace_smmuv3_cmdq_cfgi_ste_range(start, end);
+
+ for (i =3D start; i <=3D end; i++) {
+ IOMMUMemoryRegion *mr =3D smmu_iommu_mr(bs, i);
+ SMMUDevice *sdev;
+
+ if (!mr) {
+ continue;
+ }
+ sdev =3D container_of(mr, SMMUDevice, iommu);
+ smmuv3_flush_config(sdev);
+ }
+ break;
+ }
case SMMU_CMD_CFGI_CD:
case SMMU_CMD_CFGI_CD_ALL:
+ {
+ uint32_t sid =3D CMD_SID(&cmd);
+ IOMMUMemoryRegion *mr =3D smmu_iommu_mr(bs, sid);
+ SMMUDevice *sdev;
+
+ if (CMD_SSEC(&cmd)) {
+ cmd_error =3D SMMU_CERROR_ILL;
+ break;
+ }
+
+ if (!mr) {
+ break;
+ }
+
+ trace_smmuv3_cmdq_cfgi_cd(sid);
+ sdev =3D container_of(mr, SMMUDevice, iommu);
+ smmuv3_flush_config(sdev);
+ break;
+ }
case SMMU_CMD_TLBI_NH_ALL:
case SMMU_CMD_TLBI_NH_ASID:
case SMMU_CMD_TLBI_NH_VA:
@@ -735,6 +857,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
"Illegal command type: %d\n", CMD_TYPE(&cmd));
break;
}
+ qemu_mutex_unlock(&s->mutex);
if (cmd_error) {
break;
}
@@ -1114,6 +1237,8 @@ static void smmu_realize(DeviceState *d, Error **errp)
return;
}
=20
+ qemu_mutex_init(&s->mutex);
+
memory_region_init_io(&sys->iomem, OBJECT(s),
&smmu_mem_ops, sys, TYPE_ARM_SMMUV3, 0x20000);
=20
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index 0ab66bb4a86..8ee4c21dd77 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -40,3 +40,9 @@ smmuv3_translate_success(const char *n, uint16_t sid, uin=
t64_t iova, uint64_t tr
smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64
smmuv3_decode_cd(uint32_t oas) "oas=3D%d"
smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz=
) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d"
+smmuv3_cmdq_cfgi_ste(int streamid) "streamid =3D%d"
+smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=3D0x%d - end=3D0x%d"
+smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid =3D %d"
+smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint=
32_t perc) "Config cache HIT for sid %d (hits=3D%d, misses=3D%d, hit rate=
=3D%d)"
+smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin=
t32_t perc) "Config cache MISS for sid %d (hits=3D%d, misses=3D%d, hit rate=
=3D%d)"
+smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d"
--=20
2.17.1