From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153003327416875.98562870709054; Tue, 26 Jun 2018 10:14:34 -0700 (PDT) Received: from localhost ([::1]:54097 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrXx-0006ff-3l for importer@patchew.org; Tue, 26 Jun 2018 13:14:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51929) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHG-00025L-7l for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHF-0007FY-H3 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43034) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHF-0007CU-9s for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:13 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrH2-0008SX-Sr for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:00 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:27 +0100 Message-Id: <20180626165658.31394-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 01/32] aspeed/smc: fix dummy cycles count when in dual IO mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: C=C3=A9dric Le Goater When configured in dual I/O mode, address and data are sent in dual mode, including the dummy byte cycles in between. Adapt the count to the IO setting. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Andrew Jeffery Message-id: 20180612065716.10587-2-clg@kaod.org Signed-off-by: Peter Maydell --- hw/ssi/aspeed_smc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 5059396bc62..fce126e6ee9 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -66,6 +66,8 @@ =20 /* CEx Control Register */ #define R_CTRL0 (0x10 / 4) +#define CTRL_IO_DUAL_DATA (1 << 29) +#define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */ #define CTRL_CMD_SHIFT 16 #define CTRL_CMD_MASK 0xff #define CTRL_DUMMY_HIGH_SHIFT 14 @@ -492,8 +494,13 @@ static int aspeed_smc_flash_dummies(const AspeedSMCFla= sh *fl) uint32_t r_ctrl0 =3D s->regs[s->r_ctrl0 + fl->id]; uint32_t dummy_high =3D (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1; uint32_t dummy_low =3D (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3; + uint32_t dummies =3D ((dummy_high << 2) | dummy_low) * 8; =20 - return ((dummy_high << 2) | dummy_low) * 8; + if (r_ctrl0 & CTRL_IO_DUAL_ADDR_DATA) { + dummies /=3D 2; + } + + return dummies; } =20 static void aspeed_smc_flash_send_addr(AspeedSMCFlash *fl, uint32_t addr) --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530032972406308.402489467746; Tue, 26 Jun 2018 10:09:32 -0700 (PDT) Received: from localhost ([::1]:54062 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrT9-0002W7-Jy for importer@patchew.org; Tue, 26 Jun 2018 13:09:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51924) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHG-000258-1c for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHF-0007F7-2j for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43036) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHE-0007DT-Ry for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:13 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrH3-0008T7-JA for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:01 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:28 +0100 Message-Id: <20180626165658.31394-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 02/32] aspeed/smc: fix HW strapping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: C=C3=A9dric Le Goater Only the flash type is strapped by HW. The 4BYTE mode is set by firmware when the flash device is detected. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Andrew Jeffery Message-id: 20180612065716.10587-3-clg@kaod.org Signed-off-by: Peter Maydell --- hw/ssi/aspeed_smc.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index fce126e6ee9..b1537089358 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -639,23 +639,17 @@ static void aspeed_smc_reset(DeviceState *d) aspeed_smc_segment_to_reg(&s->ctrl->segments[i]); } =20 - /* HW strapping for AST2500 FMC controllers */ + /* HW strapping flash type for FMC controllers */ if (s->ctrl->segments =3D=3D aspeed_segments_ast2500_fmc) { /* flash type is fixed to SPI for CE0 and CE1 */ s->regs[s->r_conf] |=3D (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0); s->regs[s->r_conf] |=3D (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1); - - /* 4BYTE mode is autodetected for CE0. Let's force it to 1 for - * now */ - s->regs[s->r_ce_ctrl] |=3D (1 << (CTRL_EXTENDED0)); } =20 /* HW strapping for AST2400 FMC controllers (SCU70). Let's use the * configuration of the palmetto-bmc machine */ if (s->ctrl->segments =3D=3D aspeed_segments_fmc) { s->regs[s->r_conf] |=3D (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0); - - s->regs[s->r_ce_ctrl] |=3D (1 << (CTRL_EXTENDED0)); } } =20 --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530033130910346.32256249150225; Tue, 26 Jun 2018 10:12:10 -0700 (PDT) Received: from localhost ([::1]:54079 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrVe-0004cf-Kx for importer@patchew.org; Tue, 26 Jun 2018 13:12:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51923) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHG-000257-1V for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHF-0007Ex-0G for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43030) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHE-00079F-PD for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:12 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrH4-0008Ta-9d for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:02 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:29 +0100 Message-Id: <20180626165658.31394-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/32] aspeed/smc: rename aspeed_smc_flash_send_addr() to aspeed_smc_flash_setup() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: C=C3=A9dric Le Goater Also handle the fake transfers for dummy bytes in this setup routine. It will be useful when we activate MMIO execution. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Andrew Jeffery Message-id: 20180612065716.10587-4-clg@kaod.org Signed-off-by: Peter Maydell --- hw/ssi/aspeed_smc.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index b1537089358..b29bfd3124a 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -503,10 +503,11 @@ static int aspeed_smc_flash_dummies(const AspeedSMCFl= ash *fl) return dummies; } =20 -static void aspeed_smc_flash_send_addr(AspeedSMCFlash *fl, uint32_t addr) +static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr) { const AspeedSMCState *s =3D fl->controller; uint8_t cmd =3D aspeed_smc_flash_cmd(fl); + int i; =20 /* Flash access can not exceed CS segment */ addr =3D aspeed_smc_check_segment_addr(fl, addr); @@ -519,6 +520,18 @@ static void aspeed_smc_flash_send_addr(AspeedSMCFlash = *fl, uint32_t addr) ssi_transfer(s->spi, (addr >> 16) & 0xff); ssi_transfer(s->spi, (addr >> 8) & 0xff); ssi_transfer(s->spi, (addr & 0xff)); + + /* + * Use fake transfers to model dummy bytes. The value should + * be configured to some non-zero value in fast read mode and + * zero in read mode. But, as the HW allows inconsistent + * settings, let's check for fast read mode. + */ + if (aspeed_smc_flash_mode(fl) =3D=3D CTRL_FREADMODE) { + for (i =3D 0; i < aspeed_smc_flash_dummies(fl); i++) { + ssi_transfer(fl->controller->spi, 0xFF); + } + } } =20 static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned = size) @@ -537,19 +550,7 @@ static uint64_t aspeed_smc_flash_read(void *opaque, hw= addr addr, unsigned size) case CTRL_READMODE: case CTRL_FREADMODE: aspeed_smc_flash_select(fl); - aspeed_smc_flash_send_addr(fl, addr); - - /* - * Use fake transfers to model dummy bytes. The value should - * be configured to some non-zero value in fast read mode and - * zero in read mode. But, as the HW allows inconsistent - * settings, let's check for fast read mode. - */ - if (aspeed_smc_flash_mode(fl) =3D=3D CTRL_FREADMODE) { - for (i =3D 0; i < aspeed_smc_flash_dummies(fl); i++) { - ssi_transfer(fl->controller->spi, 0xFF); - } - } + aspeed_smc_flash_setup(fl, addr); =20 for (i =3D 0; i < size; i++) { ret |=3D ssi_transfer(s->spi, 0x0) << (8 * i); @@ -586,7 +587,7 @@ static void aspeed_smc_flash_write(void *opaque, hwaddr= addr, uint64_t data, break; case CTRL_WRITEMODE: aspeed_smc_flash_select(fl); - aspeed_smc_flash_send_addr(fl, addr); + aspeed_smc_flash_setup(fl, addr); =20 for (i =3D 0; i < size; i++) { ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153003294844039.53787842957797; Tue, 26 Jun 2018 10:09:08 -0700 (PDT) Received: from localhost ([::1]:54061 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrSl-0002EA-Ju for importer@patchew.org; Tue, 26 Jun 2018 13:09:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51891) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHF-00024V-Fx for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHE-0007Ec-Jp for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:13 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43034) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHE-0007CU-D8 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:12 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrH5-0008U0-0B for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:03 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:30 +0100 Message-Id: <20180626165658.31394-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 04/32] MAINTAINERS: Adopt the Gumstix computers-on-module machines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 These COMs are hard to find, and the companie dropped the support few years ago. Per the "Gumstix Product Changes, Known Issues, and EOL" pdf: - Phasing out: PXA270-based Verdex product line September 2012 - Phasing out: PXA255-based Basix & Connex September 2009 However there are still booting SD card image availables, very convenient to stress test the QEMU SD card implementation. Therefore I volunteer to keep an eye on this file, while it is useful for testing. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Message-id: 20180606144706.29732-1-f4bug@amsat.org Signed-off-by: Peter Maydell --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 2874ddce609..1676b1ba712 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -501,9 +501,10 @@ F: include/hw/arm/digic.h F: hw/*/digic* =20 Gumstix +M: Philippe Mathieu-Daud=C3=A9 L: qemu-devel@nongnu.org L: qemu-arm@nongnu.org -S: Orphan +S: Odd Fixes F: hw/arm/gumstix.c =20 i.MX31 --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530032553165579.2175476383346; Tue, 26 Jun 2018 10:02:33 -0700 (PDT) Received: from localhost ([::1]:54032 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrMK-0005qI-B9 for importer@patchew.org; Tue, 26 Jun 2018 13:02:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHF-000241-0v for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHE-0007E6-1d for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:13 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43030) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHD-00079F-Qx for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:11 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrH5-0008UW-Nw for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:03 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:31 +0100 Message-Id: <20180626165658.31394-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 05/32] xilinx_spips: Make dma transactions as per dma_burst_size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Sai Pavan Boddu Qspi dma has a burst length of 64 bytes, So limit the transactions w.r.t dma-burst-size property. Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias Message-id: 1529660880-30376-1-git-send-email-sai.pavan.boddu@xilinx.com Signed-off-by: Peter Maydell --- include/hw/ssi/xilinx_spips.h | 5 ++++- hw/ssi/xilinx_spips.c | 23 ++++++++++++++++++++--- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index d398a4e81c3..a0a0ae7584a 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -37,6 +37,8 @@ typedef struct XilinxSPIPS XilinxSPIPS; /* Bite off 4k chunks at a time */ #define LQSPI_CACHE_SIZE 1024 =20 +#define QSPI_DMA_MAX_BURST_SIZE 2048 + typedef enum { READ =3D 0x3, READ_4 =3D 0x13, FAST_READ =3D 0xb, FAST_READ_4 =3D 0x0c, @@ -95,7 +97,6 @@ typedef struct { XilinxQSPIPS parent_obj; =20 StreamSlave *dma; - uint8_t dma_buf[4]; int gqspi_irqline; =20 uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX]; @@ -113,6 +114,8 @@ typedef struct { uint8_t rx_fifo_g_align; uint8_t tx_fifo_g_align; bool man_start_com_g; + uint32_t dma_burst_size; + uint8_t dma_buf[QSPI_DMA_MAX_BURST_SIZE]; } XlnxZynqMPQSPIPS; =20 typedef struct XilinxSPIPSClass { diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index f599025956d..c052bfc4b3c 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -851,12 +851,17 @@ static void xlnx_zynqmp_qspips_notify(void *opaque) { size_t ret; uint32_t num; - const void *rxd =3D pop_buf(recv_fifo, 4, &num); + const void *rxd; + int len; + + len =3D recv_fifo->num >=3D rq->dma_burst_size ? rq->dma_burst_siz= e : + recv_fifo->num; + rxd =3D pop_buf(recv_fifo, len, &num); =20 memcpy(rq->dma_buf, rxd, num); =20 - ret =3D stream_push(rq->dma, rq->dma_buf, 4); - assert(ret =3D=3D 4); + ret =3D stream_push(rq->dma, rq->dma_buf, num); + assert(ret =3D=3D num); xlnx_zynqmp_qspips_check_flush(rq); } } @@ -1333,6 +1338,12 @@ static void xlnx_zynqmp_qspips_realize(DeviceState *= dev, Error **errp) XlnxZynqMPQSPIPS *s =3D XLNX_ZYNQMP_QSPIPS(dev); XilinxSPIPSClass *xsc =3D XILINX_SPIPS_GET_CLASS(s); =20 + if (s->dma_burst_size > QSPI_DMA_MAX_BURST_SIZE) { + error_setg(errp, + "qspi dma burst size %u exceeds maximum limit %d", + s->dma_burst_size, QSPI_DMA_MAX_BURST_SIZE); + return; + } xilinx_qspips_realize(dev, errp); fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size); fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size); @@ -1411,6 +1422,11 @@ static const VMStateDescription vmstate_xlnx_zynqmp_= qspips =3D { } }; =20 +static Property xilinx_zynqmp_qspips_properties[] =3D { + DEFINE_PROP_UINT32("dma-burst-size", XlnxZynqMPQSPIPS, dma_burst_size,= 64), + DEFINE_PROP_END_OF_LIST(), +}; + static Property xilinx_qspips_properties[] =3D { /* We had to turn this off for 2.10 as it is not compatible with migra= tion. * It can be enabled but will prevent the device to be migrated. @@ -1463,6 +1479,7 @@ static void xlnx_zynqmp_qspips_class_init(ObjectClass= *klass, void * data) dc->realize =3D xlnx_zynqmp_qspips_realize; dc->reset =3D xlnx_zynqmp_qspips_reset; dc->vmsd =3D &vmstate_xlnx_zynqmp_qspips; + dc->props =3D xilinx_zynqmp_qspips_properties; xsc->reg_ops =3D &xlnx_zynqmp_qspips_ops; xsc->rx_fifo_size =3D RXFF_A_Q; xsc->tx_fifo_size =3D TXFF_A_Q; --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530032947095509.0097322574019; Tue, 26 Jun 2018 10:09:07 -0700 (PDT) Received: from localhost ([::1]:54060 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrSg-0002CY-9o for importer@patchew.org; Tue, 26 Jun 2018 13:09:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51861) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHE-00023g-RT for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHE-0007E1-1s for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:12 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43032) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHD-0007By-Q7 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:11 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrH6-0008Uw-Ed for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:04 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:32 +0100 Message-Id: <20180626165658.31394-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/32] MAINTAINERS: Add ASPEED BMCs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Joel Stanley This adds Cedric as the maintainer, with Andrew and I as reviewers, for the ASPEED boards and the peripherals we have developed. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Andrew Jeffery Acked-by: C=C3=A9dric Le Goater Signed-off-by: Joel Stanley Message-id: 20180625140055.32223-1-joel@jms.id.au Signed-off-by: Peter Maydell --- MAINTAINERS | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1676b1ba712..8c626f6a079 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -645,6 +645,17 @@ M: Subbaraya Sundeep S: Maintained F: hw/arm/msf2-som.c =20 +ASPEED BMCs +M: C=C3=A9dric Le Goater +R: Andrew Jeffery +R: Joel Stanley +L: qemu-arm@nongnu.org +S: Maintained +F: hw/*/*aspeed* +F: include/hw/*/*aspeed* +F: hw/net/ftgmac100.c +F: include/hw/net/ftgmac100.h + CRIS Machines ------------- Axis Dev88 --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530032359263117.94784965986798; Tue, 26 Jun 2018 09:59:19 -0700 (PDT) Received: from localhost ([::1]:54009 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrJC-0003JL-Hn for importer@patchew.org; Tue, 26 Jun 2018 12:59:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51821) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHD-000237-QG for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHD-0007DD-3t for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:11 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43032) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHC-0007By-SP for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:11 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrH7-0008VN-51 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:05 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:33 +0100 Message-Id: <20180626165658.31394-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/32] hw/input/pckbd: Use qemu_log_mask(GUEST_ERROR) instead of fprintf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Message-id: 20180624040609.17572-2-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/input/pckbd.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c index f33e3fc63d6..07c8801387b 100644 --- a/hw/input/pckbd.c +++ b/hw/input/pckbd.c @@ -22,6 +22,7 @@ * THE SOFTWARE. */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "hw/hw.h" #include "hw/isa/isa.h" #include "hw/i386/pc.h" @@ -308,7 +309,8 @@ static void kbd_write_command(void *opaque, hwaddr addr, /* ignore that */ break; default: - fprintf(stderr, "qemu: unsupported keyboard cmd=3D0x%02x\n", (int)= val); + qemu_log_mask(LOG_GUEST_ERROR, + "unsupported keyboard cmd=3D0x%02" PRIx64 "\n", val); break; } } --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530032576474606.6624208774516; Tue, 26 Jun 2018 10:02:56 -0700 (PDT) Received: from localhost ([::1]:54033 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrMl-0006BN-L4 for importer@patchew.org; Tue, 26 Jun 2018 13:02:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51838) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHE-00023N-73 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHD-0007DJ-4k for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:12 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43030) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHC-00079F-OY for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:11 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrH7-0008Vo-Qw for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:05 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:34 +0100 Message-Id: <20180626165658.31394-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 08/32] hw/input/tsc2005: Use qemu_log_mask(GUEST_ERROR) instead of fprintf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Message-id: 20180624040609.17572-3-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/input/tsc2005.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/input/tsc2005.c b/hw/input/tsc2005.c index 7990954b6cd..4dd95596ab7 100644 --- a/hw/input/tsc2005.c +++ b/hw/input/tsc2005.c @@ -19,6 +19,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" #include "hw/hw.h" #include "qemu/timer.h" #include "ui/console.h" @@ -208,9 +209,10 @@ static void tsc2005_write(TSC2005State *s, int reg, ui= nt16_t data) } s->nextprecision =3D (data >> 13) & 1; s->timing[0] =3D data & 0x1fff; - if ((s->timing[0] >> 11) =3D=3D 3) - fprintf(stderr, "%s: illegal conversion clock setting\n", - __func__); + if ((s->timing[0] >> 11) =3D=3D 3) { + qemu_log_mask(LOG_GUEST_ERROR, + "tsc2005_write: illegal conversion clock setting= \n"); + } break; case 0xd: /* CFR1 */ s->timing[1] =3D data & 0xf07; @@ -221,8 +223,9 @@ static void tsc2005_write(TSC2005State *s, int reg, uin= t16_t data) break; =20 default: - fprintf(stderr, "%s: write into read-only register %x\n", - __func__, reg); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write into read-only register 0x%x\n", + __func__, reg); } } =20 --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530032622955680.4953041052827; Tue, 26 Jun 2018 10:03:42 -0700 (PDT) Received: from localhost ([::1]:54034 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrNW-0006hB-6k for importer@patchew.org; Tue, 26 Jun 2018 13:03:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51802) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHD-00022j-8G for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHC-0007Ci-5B for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:11 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43032) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHB-0007By-Uj for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:10 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrH8-0008WF-Gv for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:06 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:35 +0100 Message-Id: <20180626165658.31394-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 09/32] hw/dma/omap_dma: Use qemu_log_mask(UNIMP) instead of printf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Message-id: 20180624040609.17572-4-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/dma/omap_dma.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c index abd18c67eaf..ab3a1b04515 100644 --- a/hw/dma/omap_dma.c +++ b/hw/dma/omap_dma.c @@ -18,6 +18,7 @@ * with this program; if not, see . */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "qemu-common.h" #include "qemu/timer.h" #include "hw/arm/omap.h" @@ -1439,8 +1440,9 @@ static int omap_dma_sys_read(struct omap_dma_s *s, in= t offset, case 0x480: /* DMA_PCh0_SR */ case 0x482: /* DMA_PCh1_SR */ case 0x4c0: /* DMA_PChD_SR_0 */ - printf("%s: Physical Channel Status Registers not implemented.\n", - __func__); + qemu_log_mask(LOG_UNIMP, + "%s: Physical Channel Status Registers not implement= ed\n", + __func__); *ret =3D 0xff; break; =20 --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530032359308281.4016088239438; Tue, 26 Jun 2018 09:59:19 -0700 (PDT) Received: from localhost ([::1]:54008 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrJB-0003It-Av for importer@patchew.org; Tue, 26 Jun 2018 12:59:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51781) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHC-000226-Dj for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHB-0007CA-58 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:10 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43030) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHA-00079F-Rw for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrH9-00004z-8T for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:07 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:36 +0100 Message-Id: <20180626165658.31394-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/32] hw/dma/omap_dma: Use qemu_log_mask(GUEST_ERROR) instead of fprintf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Message-id: 20180624040609.17572-5-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/dma/omap_dma.c | 64 +++++++++++++++++++++++++++++------------------ 1 file changed, 40 insertions(+), 24 deletions(-) diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c index ab3a1b04515..cbb920f31d3 100644 --- a/hw/dma/omap_dma.c +++ b/hw/dma/omap_dma.c @@ -879,15 +879,18 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s, ch->burst[0] =3D (value & 0x0180) >> 7; ch->pack[0] =3D (value & 0x0040) >> 6; ch->port[0] =3D (enum omap_dma_port) ((value & 0x003c) >> 2); - if (ch->port[0] >=3D __omap_dma_port_last) - printf("%s: invalid DMA port %i\n", __func__, - ch->port[0]); - if (ch->port[1] >=3D __omap_dma_port_last) - printf("%s: invalid DMA port %i\n", __func__, - ch->port[1]); + if (ch->port[0] >=3D __omap_dma_port_last) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid DMA port %i\n", + __func__, ch->port[0]); + } + if (ch->port[1] >=3D __omap_dma_port_last) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid DMA port %i\n", + __func__, ch->port[1]); + } ch->data_type =3D 1 << (value & 3); if ((value & 3) =3D=3D 3) { - printf("%s: bad data_type for DMA channel\n", __func__); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad data_type for DMA channel\n", __func__); ch->data_type >>=3D 1; } break; @@ -1899,14 +1902,18 @@ static void omap_dma4_write(void *opaque, hwaddr ad= dr, if (value & 2) /* SOFTRESET */ omap_dma_reset(s->dma); s->ocp =3D value & 0x3321; - if (((s->ocp >> 12) & 3) =3D=3D 3) /* MIDLEMODE */ - fprintf(stderr, "%s: invalid DMA power mode\n", __func__); + if (((s->ocp >> 12) & 3) =3D=3D 3) { /* MIDLEMODE */ + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid DMA power mode\n", + __func__); + } return; =20 case 0x78: /* DMA4_GCR */ s->gcr =3D value & 0x00ff00ff; - if ((value & 0xff) =3D=3D 0x00) /* MAX_CHANNEL_FIFO_DEPTH */ - fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __func__); + if ((value & 0xff) =3D=3D 0x00) { /* MAX_CHANNEL_FIFO_DEPTH */ + qemu_log_mask(LOG_GUEST_ERROR, "%s: wrong FIFO depth in GCR\n", + __func__); + } return; =20 case 0x80 ... 0xfff: @@ -1935,9 +1942,11 @@ static void omap_dma4_write(void *opaque, hwaddr add= r, case 0x00: /* DMA4_CCR */ ch->buf_disable =3D (value >> 25) & 1; ch->src_sync =3D (value >> 24) & 1; /* XXX For CamDMA must be 1 */ - if (ch->buf_disable && !ch->src_sync) - fprintf(stderr, "%s: Buffering disable is not allowed in " - "destination synchronised mode\n", __func__); + if (ch->buf_disable && !ch->src_sync) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Buffering disable is not allowed in " + "destination synchronised mode\n", __func__); + } ch->prefetch =3D (value >> 23) & 1; ch->bs =3D (value >> 18) & 1; ch->transparent_copy =3D (value >> 17) & 1; @@ -1947,9 +1956,11 @@ static void omap_dma4_write(void *opaque, hwaddr add= r, ch->suspend =3D (value & 0x0100) >> 8; ch->priority =3D (value & 0x0040) >> 6; ch->fs =3D (value & 0x0020) >> 5; - if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) - fprintf(stderr, "%s: For a packet transfer at least one port " - "must be constant-addressed\n", __func__); + if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: For a packet transfer at least one port " + "must be constant-addressed\n", __func__); + } ch->sync =3D (value & 0x001f) | ((value >> 14) & 0x0060); /* XXX must be 0x01 for CamDMA */ =20 @@ -1978,9 +1989,11 @@ static void omap_dma4_write(void *opaque, hwaddr add= r, ch->endian_lock[0] =3D(value >> 20) & 1; ch->endian[1] =3D(value >> 19) & 1; ch->endian_lock[1] =3D(value >> 18) & 1; - if (ch->endian[0] !=3D ch->endian[1]) - fprintf(stderr, "%s: DMA endianness conversion enable attempt\= n", - __func__); + if (ch->endian[0] !=3D ch->endian[1]) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: DMA endianness conversion enable attempt\n", + __func__); + } ch->write_mode =3D (value >> 16) & 3; ch->burst[1] =3D (value & 0xc000) >> 14; ch->pack[1] =3D (value & 0x2000) >> 13; @@ -1988,12 +2001,15 @@ static void omap_dma4_write(void *opaque, hwaddr ad= dr, ch->burst[0] =3D (value & 0x0180) >> 7; ch->pack[0] =3D (value & 0x0040) >> 6; ch->translate[0] =3D (value & 0x003c) >> 2; - if (ch->translate[0] | ch->translate[1]) - fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\= n", - __func__); + if (ch->translate[0] | ch->translate[1]) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad MReqAddressTranslate sideband signal\n", + __func__); + } ch->data_type =3D 1 << (value & 3); if ((value & 3) =3D=3D 3) { - printf("%s: bad data_type for DMA channel\n", __func__); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad data_type for DMA channel\n", __func__); ch->data_type >>=3D 1; } break; --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Tue, 26 Jun 2018 12:57:10 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43032) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHB-0007By-1d for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrH9-00005R-VQ for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:07 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:37 +0100 Message-Id: <20180626165658.31394-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/32] hw/ssi/omap_spi: Use qemu_log_mask(GUEST_ERROR) instead of fprintf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 20180624040609.17572-6-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/ssi/omap_spi.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/ssi/omap_spi.c b/hw/ssi/omap_spi.c index 34163e5646e..f278a551605 100644 --- a/hw/ssi/omap_spi.c +++ b/hw/ssi/omap_spi.c @@ -20,6 +20,7 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "hw/hw.h" #include "hw/arm/omap.h" =20 @@ -294,11 +295,15 @@ static void omap_mcspi_write(void *opaque, hwaddr add= r, case 0x2c: /* MCSPI_CHCONF */ if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */ omap_mcspi_dmarequest_update(s->ch + ch); - if (((value >> 12) & 3) =3D=3D 3) /* TRM */ - fprintf(stderr, "%s: invalid TRM value (3)\n", __func__); - if (((value >> 7) & 0x1f) < 3) /* WL */ - fprintf(stderr, "%s: invalid WL value (%" PRIx64 ")\n", - __func__, (value >> 7) & 0x1f); + if (((value >> 12) & 3) =3D=3D 3) { /* TRM */ + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid TRM value (3)\n", + __func__); + } + if (((value >> 7) & 0x1f) < 3) { /* WL */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid WL value (%" PRIx64 ")\n", + __func__, (value >> 7) & 0x1f); + } s->ch[ch].config =3D value & 0x7fffff; break; =20 --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530032757824832.1171067735961; Tue, 26 Jun 2018 10:05:57 -0700 (PDT) Received: from localhost ([::1]:54045 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrPh-0008EQ-2c for importer@patchew.org; Tue, 26 Jun 2018 13:05:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51794) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHD-00022Y-19 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHC-0007Ca-1X for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:11 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43030) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHB-00079F-Qt for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHA-00005i-LV for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:08 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:38 +0100 Message-Id: <20180626165658.31394-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 12/32] hw/sd/omap_mmc: Use qemu_log_mask(UNIMP) instead of printf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Message-id: 20180624040609.17572-7-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/sd/omap_mmc.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c index 5b47cadf113..aa2a816f765 100644 --- a/hw/sd/omap_mmc.c +++ b/hw/sd/omap_mmc.c @@ -17,6 +17,7 @@ * with this program; if not, see . */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "hw/hw.h" #include "hw/arm/omap.h" #include "hw/sd/sd.h" @@ -449,10 +450,14 @@ static void omap_mmc_write(void *opaque, hwaddr offse= t, s->enable =3D (value >> 11) & 1; s->be =3D (value >> 10) & 1; s->clkdiv =3D (value >> 0) & (s->rev >=3D 2 ? 0x3ff : 0xff); - if (s->mode !=3D 0) - printf("SD mode %i unimplemented!\n", s->mode); - if (s->be !=3D 0) - printf("SD FIFO byte sex unimplemented!\n"); + if (s->mode !=3D 0) { + qemu_log_mask(LOG_UNIMP, + "omap_mmc_wr: mode #%i unimplemented\n", s->mode= ); + } + if (s->be !=3D 0) { + qemu_log_mask(LOG_UNIMP, + "omap_mmc_wr: Big Endian not implemented\n"); + } if (s->dw !=3D 0 && s->lines < 4) printf("4-bit SD bus enabled\n"); if (!s->enable) --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530032548698398.57595334719736; Tue, 26 Jun 2018 10:02:28 -0700 (PDT) Received: from localhost ([::1]:54031 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrMG-0005pH-18 for importer@patchew.org; Tue, 26 Jun 2018 13:02:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51815) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHD-00022z-L4 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHC-0007D1-MJ for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:11 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43034) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHC-0007CU-Dt for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:10 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHB-00006D-CI for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:09 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:39 +0100 Message-Id: <20180626165658.31394-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 13/32] hw/i2c/omap_i2c: Use qemu_log_mask(UNIMP) instead of fprintf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Message-id: 20180624040609.17572-8-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/i2c/omap_i2c.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c index 26e3e5ebf6e..d02e734ea8e 100644 --- a/hw/i2c/omap_i2c.c +++ b/hw/i2c/omap_i2c.c @@ -17,6 +17,7 @@ * with this program; if not, see . */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "hw/hw.h" #include "hw/i2c/i2c.h" #include "hw/arm/omap.h" @@ -339,14 +340,15 @@ static void omap_i2c_write(void *opaque, hwaddr addr, } break; } - if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */ - fprintf(stderr, "%s: I^2C slave mode not supported\n", - __func__); + if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */ + qemu_log_mask(LOG_UNIMP, "%s: I^2C slave mode not supported\n", + __func__); break; } - if ((value & (1 << 15)) && value & (1 << 8)) { /* XA */ - fprintf(stderr, "%s: 10-bit addressing mode not supported\n", - __func__); + if ((value & (1 << 15)) && value & (1 << 8)) { /* XA */ + qemu_log_mask(LOG_UNIMP, + "%s: 10-bit addressing mode not supported\n", + __func__); break; } if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */ @@ -392,8 +394,10 @@ static void omap_i2c_write(void *opaque, hwaddr addr, s->stat |=3D 0x3f; omap_i2c_interrupts_update(s); } - if (value & (1 << 15)) /* ST_EN */ - fprintf(stderr, "%s: System Test not supported\n", __func__); + if (value & (1 << 15)) { /* ST_EN */ + qemu_log_mask(LOG_UNIMP, + "%s: System Test not supported\n", __func__); + } break; =20 default: --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530032830172507.65819673474334; Tue, 26 Jun 2018 10:07:10 -0700 (PDT) Received: from localhost ([::1]:54051 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrQr-0000lI-F9 for importer@patchew.org; Tue, 26 Jun 2018 13:07:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51856) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHE-00023V-Kr for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHD-0007Di-L7 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:12 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43034) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHD-0007CU-DU for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:11 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHC-00006T-45 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:10 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:40 +0100 Message-Id: <20180626165658.31394-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 14/32] hw/arm/omap1: Use qemu_log_mask(GUEST_ERROR) instead of fprintf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 TCMI_VERBOSE is no more used, drop the OMAP_8/16/32B_REG macros. Suggested-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Message-id: 20180624040609.17572-9-f4bug@amsat.org Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 18 ------------------ hw/arm/omap1.c | 18 ++++++++++++------ 2 files changed, 12 insertions(+), 24 deletions(-) diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index b398607b06c..39abba753d4 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -993,24 +993,6 @@ enum { #define OMAP_GPIOSW_INVERTED 0x0001 #define OMAP_GPIOSW_OUTPUT 0x0002 =20 -# define TCMI_VERBOSE 1 - -# ifdef TCMI_VERBOSE -# define OMAP_8B_REG(paddr) \ - fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \ - __func__, paddr) -# define OMAP_16B_REG(paddr) \ - fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \ - __func__, paddr) -# define OMAP_32B_REG(paddr) \ - fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \ - __func__, paddr) -# else -# define OMAP_8B_REG(paddr) -# define OMAP_16B_REG(paddr) -# define OMAP_32B_REG(paddr) -# endif - # define OMAP_MPUI_REG_MASK 0x000007ff =20 #endif /* hw_omap_h */ diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 9af04728e39..539d29ef9ce 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -34,12 +34,18 @@ #include "qemu/cutils.h" #include "qemu/bcd.h" =20 +static inline void omap_log_badwidth(const char *funcname, hwaddr addr, in= t sz) +{ + qemu_log_mask(LOG_GUEST_ERROR, "%s: %d-bit register %#08" HWADDR_PRIx = "\n", + funcname, 8 * sz, addr); +} + /* Should signal the TCMI/GPMC */ uint32_t omap_badwidth_read8(void *opaque, hwaddr addr) { uint8_t ret; =20 - OMAP_8B_REG(addr); + omap_log_badwidth(__func__, addr, 1); cpu_physical_memory_read(addr, &ret, 1); return ret; } @@ -49,7 +55,7 @@ void omap_badwidth_write8(void *opaque, hwaddr addr, { uint8_t val8 =3D value; =20 - OMAP_8B_REG(addr); + omap_log_badwidth(__func__, addr, 1); cpu_physical_memory_write(addr, &val8, 1); } =20 @@ -57,7 +63,7 @@ uint32_t omap_badwidth_read16(void *opaque, hwaddr addr) { uint16_t ret; =20 - OMAP_16B_REG(addr); + omap_log_badwidth(__func__, addr, 2); cpu_physical_memory_read(addr, &ret, 2); return ret; } @@ -67,7 +73,7 @@ void omap_badwidth_write16(void *opaque, hwaddr addr, { uint16_t val16 =3D value; =20 - OMAP_16B_REG(addr); + omap_log_badwidth(__func__, addr, 2); cpu_physical_memory_write(addr, &val16, 2); } =20 @@ -75,7 +81,7 @@ uint32_t omap_badwidth_read32(void *opaque, hwaddr addr) { uint32_t ret; =20 - OMAP_32B_REG(addr); + omap_log_badwidth(__func__, addr, 4); cpu_physical_memory_read(addr, &ret, 4); return ret; } @@ -83,7 +89,7 @@ uint32_t omap_badwidth_read32(void *opaque, hwaddr addr) void omap_badwidth_write32(void *opaque, hwaddr addr, uint32_t value) { - OMAP_32B_REG(addr); + omap_log_badwidth(__func__, addr, 4); cpu_physical_memory_write(addr, &value, 4); } =20 --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153003275671384.26363550194469; Tue, 26 Jun 2018 10:05:56 -0700 (PDT) Received: from localhost ([::1]:54046 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrPf-0008ET-T2 for importer@patchew.org; Tue, 26 Jun 2018 13:05:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51876) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHF-00024I-6y for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHE-0007ED-4T for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:13 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43036) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHD-0007DT-Ru for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:12 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHC-000072-RE for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:10 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:41 +0100 Message-Id: <20180626165658.31394-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 15/32] hw/arm/omap: Use qemu_log_mask(GUEST_ERROR) instead of fprintf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Message-id: 20180624040609.17572-10-f4bug@amsat.org Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 39abba753d4..e7fbd340f37 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -21,6 +21,7 @@ # define hw_omap_h "omap.h" #include "hw/irq.h" #include "target/arm/cpu-qom.h" +#include "qemu/log.h" =20 # define OMAP_EMIFS_BASE 0x00000000 # define OMAP2_Q0_BASE 0x00000000 @@ -944,8 +945,6 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion= *sysmem, unsigned long sdram_size, const char *core); =20 -#define OMAP_FMT_plx "%#08" HWADDR_PRIx - uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); void omap_badwidth_write8(void *opaque, hwaddr addr, uint32_t value); @@ -959,11 +958,12 @@ void omap_badwidth_write32(void *opaque, hwaddr addr, void omap_mpu_wakeup(void *opaque, int irq, int req); =20 # define OMAP_BAD_REG(paddr) \ - fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \ - __func__, paddr) + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"= \n", \ + __func__, paddr) # define OMAP_RO_REG(paddr) \ - fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \ - __func__, paddr) + qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ + HWADDR_PRIx "\n", \ + __func__, paddr) =20 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area (Board-specifc tags are not here) */ --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530032788792778.2387187777176; Tue, 26 Jun 2018 10:06:28 -0700 (PDT) Received: from localhost ([::1]:54050 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrQ4-0000Bm-UO for importer@patchew.org; Tue, 26 Jun 2018 13:06:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51914) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHF-00024y-St for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHF-0007FD-3h for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:13 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43032) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHE-0007By-S0 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:13 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHD-00007O-H9 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:11 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:42 +0100 Message-Id: <20180626165658.31394-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 16/32] hw/arm/stellaris: Use qemu_log_mask(UNIMP) instead of fprintf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Message-id: 20180624040609.17572-11-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/stellaris.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index a8f1f6a9128..d06e366402e 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -560,7 +560,7 @@ static void ssys_write(void *opaque, hwaddr offset, case 0x040: /* SRCR0 */ case 0x044: /* SRCR1 */ case 0x048: /* SRCR2 */ - fprintf(stderr, "Peripheral reset not implemented\n"); + qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); break; case 0x054: /* IMC */ s->int_mask =3D value & 0x7f; --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530033021728978.5696670704635; Tue, 26 Jun 2018 10:10:21 -0700 (PDT) Received: from localhost ([::1]:54063 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrTp-00035H-U7 for importer@patchew.org; Tue, 26 Jun 2018 13:10:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51935) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHG-00025s-Dn for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHF-0007Fd-II for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43038) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHF-0007Ej-Ad for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:13 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHE-00007x-9W for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:12 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:43 +0100 Message-Id: <20180626165658.31394-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 17/32] hw/net/stellaris_enet: Fix a typo X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 Suggested-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20180624040609.17572-12-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/net/stellaris_enet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/stellaris_enet.c b/hw/net/stellaris_enet.c index 04bd10ada3f..1e7329517cf 100644 --- a/hw/net/stellaris_enet.c +++ b/hw/net/stellaris_enet.c @@ -340,7 +340,7 @@ static uint64_t stellaris_enet_read(void *opaque, hwadd= r offset, return s->np; case 0x38: /* TR */ return 0; - case 0x3c: /* Undocuented: Timestamp? */ + case 0x3c: /* Undocumented: Timestamp? */ return 0; default: hw_error("stellaris_enet_read: Bad offset %x\n", (int)offset); --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530033383061671.3922502417823; Tue, 26 Jun 2018 10:16:23 -0700 (PDT) Received: from localhost ([::1]:54110 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrZm-000865-7a for importer@patchew.org; Tue, 26 Jun 2018 13:16:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51958) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHH-00026k-5O for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHG-0007GS-D1 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:15 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43034) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHG-0007CU-6C for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:14 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHF-00008W-3o for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:13 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:44 +0100 Message-Id: <20180626165658.31394-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 18/32] hw/net/stellaris_enet: Use qemu_log_mask(GUEST_ERROR) instead of hw_error X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 hw_error() finally calls abort(), but there is no need to abort here. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20180624040609.17572-13-f4bug@amsat.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/net/stellaris_enet.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/net/stellaris_enet.c b/hw/net/stellaris_enet.c index 1e7329517cf..165562d7886 100644 --- a/hw/net/stellaris_enet.c +++ b/hw/net/stellaris_enet.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "net/net.h" +#include "qemu/log.h" #include =20 //#define DEBUG_STELLARIS_ENET 1 @@ -343,7 +344,9 @@ static uint64_t stellaris_enet_read(void *opaque, hwadd= r offset, case 0x3c: /* Undocumented: Timestamp? */ return 0; default: - hw_error("stellaris_enet_read: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, "stellaris_enet_rd%d: Illegal regis= ter" + " 0x02%" HWADDR_PRIx "\n", + size * 8, offset); return 0; } } @@ -442,7 +445,9 @@ static void stellaris_enet_write(void *opaque, hwaddr o= ffset, /* Ignored. */ break; default: - hw_error("stellaris_enet_write: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, "stellaris_enet_wr%d: Illegal regis= ter " + "0x02%" HWADDR_PRIx " =3D 0x%" PRIx= 64 "\n", + size * 8, offset, value); } } =20 --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530033129361907.4577198180515; Tue, 26 Jun 2018 10:12:09 -0700 (PDT) Received: from localhost ([::1]:54080 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrVg-0004cx-Go for importer@patchew.org; Tue, 26 Jun 2018 13:12:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51969) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHH-00027T-RT for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHH-0007Gn-21 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:15 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43040) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHG-0007GJ-Qn for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:14 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHF-00009a-P2 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:13 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:45 +0100 Message-Id: <20180626165658.31394-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 19/32] hw/net/smc91c111: Use qemu_log_mask(GUEST_ERROR) instead of hw_error X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 hw_error() finally calls abort(), but there is no need to abort here. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Message-id: 20180624040609.17572-14-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/net/smc91c111.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/net/smc91c111.c b/hw/net/smc91c111.c index c8cc5379b78..9094c0b47ca 100644 --- a/hw/net/smc91c111.c +++ b/hw/net/smc91c111.c @@ -11,6 +11,7 @@ #include "hw/sysbus.h" #include "net/net.h" #include "hw/devices.h" +#include "qemu/log.h" /* For crc32 */ #include =20 @@ -478,7 +479,9 @@ static void smc91c111_writeb(void *opaque, hwaddr offse= t, } break; } - hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, "smc91c111_write(bank:%d) Illegal regis= ter" + " 0x%" HWADDR_PRIx " =3D 0x%x\n", + s->bank, offset, value); } =20 static uint32_t smc91c111_readb(void *opaque, hwaddr offset) @@ -621,7 +624,9 @@ static uint32_t smc91c111_readb(void *opaque, hwaddr of= fset) } break; } - hw_error("smc91c111_read: Bad reg %d:%x\n", s->bank, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, "smc91c111_read(bank:%d) Illegal regist= er" + " 0x%" HWADDR_PRIx "\n", + s->bank, offset); return 0; } =20 --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530033525015430.5181125240629; Tue, 26 Jun 2018 10:18:45 -0700 (PDT) Received: from localhost ([::1]:54116 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrc2-0000yx-3S for importer@patchew.org; Tue, 26 Jun 2018 13:18:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51989) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHI-00028N-O9 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHH-0007HP-Vn for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:16 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43040) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHH-0007GJ-ON for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:15 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHG-0000A0-FD for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:14 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:46 +0100 Message-Id: <20180626165658.31394-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 20/32] hw/net/smc91c111: Use qemu_log_mask(UNIMP) instead of fprintf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Message-id: 20180624040609.17572-15-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/net/smc91c111.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/net/smc91c111.c b/hw/net/smc91c111.c index 9094c0b47ca..d2fd2040e81 100644 --- a/hw/net/smc91c111.c +++ b/hw/net/smc91c111.c @@ -362,10 +362,14 @@ static void smc91c111_writeb(void *opaque, hwaddr off= set, SET_HIGH(gpr, value); return; case 12: /* Control */ - if (value & 1) - fprintf(stderr, "smc91c111:EEPROM store not implemented\n"= ); - if (value & 2) - fprintf(stderr, "smc91c111:EEPROM reload not implemented\n= "); + if (value & 1) { + qemu_log_mask(LOG_UNIMP, + "smc91c111: EEPROM store not implemented\n"); + } + if (value & 2) { + qemu_log_mask(LOG_UNIMP, + "smc91c111: EEPROM reload not implemented\n"= ); + } value &=3D ~3; SET_LOW(ctr, value); return; --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530033151626444.4588302307328; Tue, 26 Jun 2018 10:12:31 -0700 (PDT) Received: from localhost ([::1]:54081 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrW2-0004ux-Pd for importer@patchew.org; Tue, 26 Jun 2018 13:12:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51991) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHJ-00028k-1t for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHI-0007Hc-ED for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:17 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43042) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHI-0007HC-7z for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:16 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHH-0000AS-5B for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:15 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:47 +0100 Message-Id: <20180626165658.31394-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 21/32] hw/arm/stellaris: Fix gptm_write() error message X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 Missed in df3692e04b2. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20180624040609.17572-16-f4bug@amsat.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/stellaris.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index d06e366402e..42baa768b2d 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -294,7 +294,7 @@ static void gptm_write(void *opaque, hwaddr offset, break; default: qemu_log_mask(LOG_GUEST_ERROR, - "GPTM: read at bad offset 0x%x\n", (int)offset); + "GPTM: write at bad offset 0x%x\n", (int)offset); } gptm_update_irq(s); } --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530033680965170.590513873315; Tue, 26 Jun 2018 10:21:20 -0700 (PDT) Received: from localhost ([::1]:54130 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXreT-0002u3-7H for importer@patchew.org; Tue, 26 Jun 2018 13:21:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52007) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHK-00029w-5S for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHJ-0007I6-EE for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:18 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43042) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHJ-0007HC-6K for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:17 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHH-0000Ah-So for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:15 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:48 +0100 Message-Id: <20180626165658.31394-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 22/32] hw/arm/stellaris: Use HWADDR_PRIx to display register address X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 Suggested-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20180624040609.17572-17-f4bug@amsat.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/stellaris.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 42baa768b2d..dc521b4a5a8 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -212,7 +212,8 @@ static uint64_t gptm_read(void *opaque, hwaddr offset, return 0; default: qemu_log_mask(LOG_GUEST_ERROR, - "GPTM: read at bad offset 0x%x\n", (int)offset); + "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n", + offset); return 0; } } @@ -294,7 +295,8 @@ static void gptm_write(void *opaque, hwaddr offset, break; default: qemu_log_mask(LOG_GUEST_ERROR, - "GPTM: write at bad offset 0x%x\n", (int)offset); + "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n", + offset); } gptm_update_irq(s); } --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530033317046906.2612769504327; Tue, 26 Jun 2018 10:15:17 -0700 (PDT) Received: from localhost ([::1]:54099 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrYa-00077n-41 for importer@patchew.org; Tue, 26 Jun 2018 13:15:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52029) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHL-0002CW-V5 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHK-0007IN-1G for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:20 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43044) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHJ-0007Hu-L3 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:17 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHI-0000BL-JK for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:16 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:49 +0100 Message-Id: <20180626165658.31394-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 23/32] tcg: Support MMU protection regions smaller than TARGET_PAGE_SIZE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for MMU protection regions that are smaller than TARGET_PAGE_SIZE. We do this by marking the TLB entry for those pages with a flag TLB_RECHECK. This flag causes us to always take the slow-path for accesses. In the slow path we can then special case them to always call tlb_fill() again, so we have the correct information for the exact address being accessed. This change allows us to handle reading and writing from small regions; we cannot deal with execution from the small region. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20180620130619.11362-2-peter.maydell@linaro.org --- accel/tcg/softmmu_template.h | 24 ++++--- include/exec/cpu-all.h | 5 +- accel/tcg/cputlb.c | 131 +++++++++++++++++++++++++++++------ 3 files changed, 130 insertions(+), 30 deletions(-) diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h index 239ea6692b4..c47591c9709 100644 --- a/accel/tcg/softmmu_template.h +++ b/accel/tcg/softmmu_template.h @@ -98,10 +98,12 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, size_t mmu_idx, size_t index, target_ulong addr, - uintptr_t retaddr) + uintptr_t retaddr, + bool recheck) { CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; - return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, DATA_SIZE); + return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, recheck, + DATA_SIZE); } #endif =20 @@ -138,7 +140,8 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_u= long addr, =20 /* ??? Note that the io helpers always read data in the target byte ordering. We should push the LE/BE request down into io. = */ - res =3D glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr); + res =3D glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr, + tlb_addr & TLB_RECHECK); res =3D TGT_LE(res); return res; } @@ -205,7 +208,8 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_u= long addr, =20 /* ??? Note that the io helpers always read data in the target byte ordering. We should push the LE/BE request down into io. = */ - res =3D glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr); + res =3D glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr, + tlb_addr & TLB_RECHECK); res =3D TGT_BE(res); return res; } @@ -259,10 +263,12 @@ static inline void glue(io_write, SUFFIX)(CPUArchStat= e *env, size_t mmu_idx, size_t index, DATA_TYPE val, target_ulong addr, - uintptr_t retaddr) + uintptr_t retaddr, + bool recheck) { CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; - return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, DATA_SI= ZE); + return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, + recheck, DATA_SIZE); } =20 void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, @@ -298,7 +304,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, /* ??? Note that the io helpers always read data in the target byte ordering. We should push the LE/BE request down into io. = */ val =3D TGT_LE(val); - glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr); + glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, + retaddr, tlb_addr & TLB_RECHECK); return; } =20 @@ -375,7 +382,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, /* ??? Note that the io helpers always read data in the target byte ordering. We should push the LE/BE request down into io. = */ val =3D TGT_BE(val); - glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr); + glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr, + tlb_addr & TLB_RECHECK); return; } =20 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 7fa726b8e36..7338f57062f 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -330,11 +330,14 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS - 2)) /* Set if TLB entry is an IO callback. */ #define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) +/* Set if TLB entry must have MMU lookup repeated for every access */ +#define TLB_RECHECK (1 << (TARGET_PAGE_BITS - 4)) =20 /* Use this mask to check interception with an alignment mask * in a TCG backend. */ -#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO) +#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ + | TLB_RECHECK) =20 void dump_exec_info(FILE *f, fprintf_function cpu_fprintf); void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 719cca2268b..eebe97dabb7 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -613,27 +613,42 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, target_ulong code_address; uintptr_t addend; CPUTLBEntry *te, *tv, tn; - hwaddr iotlb, xlat, sz; + hwaddr iotlb, xlat, sz, paddr_page; + target_ulong vaddr_page; unsigned vidx =3D env->vtlb_index++ % CPU_VTLB_SIZE; int asidx =3D cpu_asidx_from_attrs(cpu, attrs); =20 assert_cpu_is_self(cpu); - assert(size >=3D TARGET_PAGE_SIZE); - if (size !=3D TARGET_PAGE_SIZE) { - tlb_add_large_page(env, vaddr, size); - } =20 - sz =3D size; - section =3D address_space_translate_for_iotlb(cpu, asidx, paddr, &xlat= , &sz, - attrs, &prot); + if (size < TARGET_PAGE_SIZE) { + sz =3D TARGET_PAGE_SIZE; + } else { + if (size > TARGET_PAGE_SIZE) { + tlb_add_large_page(env, vaddr, size); + } + sz =3D size; + } + vaddr_page =3D vaddr & TARGET_PAGE_MASK; + paddr_page =3D paddr & TARGET_PAGE_MASK; + + section =3D address_space_translate_for_iotlb(cpu, asidx, paddr_page, + &xlat, &sz, attrs, &prot); assert(sz >=3D TARGET_PAGE_SIZE); =20 tlb_debug("vaddr=3D" TARGET_FMT_lx " paddr=3D0x" TARGET_FMT_plx " prot=3D%x idx=3D%d\n", vaddr, paddr, prot, mmu_idx); =20 - address =3D vaddr; - if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(secti= on->mr)) { + address =3D vaddr_page; + if (size < TARGET_PAGE_SIZE) { + /* + * Slow-path the TLB entries; we will repeat the MMU check and TLB + * fill on every access. + */ + address |=3D TLB_RECHECK; + } + if (!memory_region_is_ram(section->mr) && + !memory_region_is_romd(section->mr)) { /* IO memory case */ address |=3D TLB_MMIO; addend =3D 0; @@ -643,10 +658,10 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, } =20 code_address =3D address; - iotlb =3D memory_region_section_get_iotlb(cpu, section, vaddr, paddr, = xlat, - prot, &address); + iotlb =3D memory_region_section_get_iotlb(cpu, section, vaddr_page, + paddr_page, xlat, prot, &addre= ss); =20 - index =3D (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + index =3D (vaddr_page >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); te =3D &env->tlb_table[mmu_idx][index]; /* do not discard the translation in te, evict it into a victim tlb */ tv =3D &env->tlb_v_table[mmu_idx][vidx]; @@ -662,18 +677,18 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, * TARGET_PAGE_BITS, and either * + the ram_addr_t of the page base of the target RAM (if NOTDIRTY o= r ROM) * + the offset within section->mr of the page base (otherwise) - * We subtract the vaddr (which is page aligned and thus won't + * We subtract the vaddr_page (which is page aligned and thus won't * disturb the low bits) to give an offset which can be added to the * (non-page-aligned) vaddr of the eventual memory access to get * the MemoryRegion offset for the access. Note that the vaddr we * subtract here is that of the page base, and not the same as the * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ - env->iotlb[mmu_idx][index].addr =3D iotlb - vaddr; + env->iotlb[mmu_idx][index].addr =3D iotlb - vaddr_page; env->iotlb[mmu_idx][index].attrs =3D attrs; =20 /* Now calculate the new entry */ - tn.addend =3D addend - vaddr; + tn.addend =3D addend - vaddr_page; if (prot & PAGE_READ) { tn.addr_read =3D address; } else { @@ -694,7 +709,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, tn.addr_write =3D address | TLB_MMIO; } else if (memory_region_is_ram(section->mr) && cpu_physical_memory_is_clean( - memory_region_get_ram_addr(section->mr) + xlat)) { + memory_region_get_ram_addr(section->mr) + xlat)) { tn.addr_write =3D address | TLB_NOTDIRTY; } else { tn.addr_write =3D address; @@ -767,7 +782,8 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail= (void *ptr) =20 static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, - target_ulong addr, uintptr_t retaddr, int size) + target_ulong addr, uintptr_t retaddr, + bool recheck, int size) { CPUState *cpu =3D ENV_GET_CPU(env); hwaddr mr_offset; @@ -777,6 +793,29 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEn= try *iotlbentry, bool locked =3D false; MemTxResult r; =20 + if (recheck) { + /* + * This is a TLB_RECHECK access, where the MMU protection + * covers a smaller range than a target page, and we must + * repeat the MMU check here. This tlb_fill() call might + * longjump out if this access should cause a guest exception. + */ + int index; + target_ulong tlb_addr; + + tlb_fill(cpu, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); + + index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + tlb_addr =3D env->tlb_table[mmu_idx][index].addr_read; + if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) { + /* RAM access */ + uintptr_t haddr =3D addr + env->tlb_table[mmu_idx][index].adde= nd; + + return ldn_p((void *)haddr, size); + } + /* Fall through for handling IO accesses */ + } + section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -811,7 +850,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, uint64_t val, target_ulong addr, - uintptr_t retaddr, int size) + uintptr_t retaddr, bool recheck, int size) { CPUState *cpu =3D ENV_GET_CPU(env); hwaddr mr_offset; @@ -820,6 +859,30 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry= *iotlbentry, bool locked =3D false; MemTxResult r; =20 + if (recheck) { + /* + * This is a TLB_RECHECK access, where the MMU protection + * covers a smaller range than a target page, and we must + * repeat the MMU check here. This tlb_fill() call might + * longjump out if this access should cause a guest exception. + */ + int index; + target_ulong tlb_addr; + + tlb_fill(cpu, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); + + index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write; + if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) { + /* RAM access */ + uintptr_t haddr =3D addr + env->tlb_table[mmu_idx][index].adde= nd; + + stn_p((void *)haddr, size, val); + return; + } + /* Fall through for handling IO accesses */ + } + section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -903,6 +966,32 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, t= arget_ulong addr) tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0= ); } } + + if (unlikely(env->tlb_table[mmu_idx][index].addr_code & TLB_RECHECK)) { + /* + * This is a TLB_RECHECK access, where the MMU protection + * covers a smaller range than a target page, and we must + * repeat the MMU check here. This tlb_fill() call might + * longjump out if this access should cause a guest exception. + */ + int index; + target_ulong tlb_addr; + + tlb_fill(cpu, addr, 0, MMU_INST_FETCH, mmu_idx, 0); + + index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + tlb_addr =3D env->tlb_table[mmu_idx][index].addr_code; + if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) { + /* RAM access. We can't handle this, so for now just stop */ + cpu_abort(cpu, "Unable to handle guest executing from RAM with= in " + "a small MPU region at 0x" TARGET_FMT_lx, addr); + } + /* + * Fall through to handle IO accesses (which will almost certainly + * also result in failure) + */ + } + iotlbentry =3D &env->iotlb[mmu_idx][index]; section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr =3D section->mr; @@ -1011,8 +1100,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, tlb_addr =3D tlbe->addr_write & ~TLB_INVALID_MASK; } =20 - /* Notice an IO access */ - if (unlikely(tlb_addr & TLB_MMIO)) { + /* Notice an IO access or a needs-MMU-lookup access */ + if (unlikely(tlb_addr & (TLB_MMIO | TLB_RECHECK))) { /* There's really nothing that can be done to support this apart from stop-the-world. */ goto stop_the_world; --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153003319090083.74080231583537; Tue, 26 Jun 2018 10:13:10 -0700 (PDT) Received: from localhost ([::1]:54082 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrWg-0005Vk-1L for importer@patchew.org; Tue, 26 Jun 2018 13:13:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52031) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHM-0002Cb-1V for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHL-0007Im-1E for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:20 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43044) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHK-0007Hu-OZ for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:18 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHJ-0000Ba-Bf for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:17 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:50 +0100 Message-Id: <20180626165658.31394-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 24/32] target/arm: Set page (region) size in get_phys_addr_pmsav7() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We want to handle small MPU region sizes for ARMv7M. To do this, make get_phys_addr_pmsav7() set the page size to the region size if it is less that TARGET_PAGE_SIZE, rather than working only in TARGET_PAGE_SIZE chunks. Since the core TCG code con't handle execution from small MPU regions, we strip the exec permission from them so that any execution attempts will cause an MPU exception, rather than allowing it to end up with a cpu_abort() in get_page_addr_code(). (The previous code's intention was to make any small page be treated as having no permissions, but unfortunately errors in the implementation meant that it didn't behave that way. It's possible that some binaries using small regions were accidentally working with our old behaviour and won't now.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20180620130619.11362-3-peter.maydell@linaro.org --- target/arm/helper.c | 37 ++++++++++++++++++++++++++----------- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1248d84e6fa..a7edeb66633 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9596,6 +9596,7 @@ static inline bool m_is_system_region(CPUARMState *en= v, uint32_t address) static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_= idx, hwaddr *phys_ptr, int *prot, + target_ulong *page_size, ARMMMUFaultInfo *fi) { ARMCPU *cpu =3D arm_env_get_cpu(env); @@ -9603,6 +9604,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, bool is_user =3D regime_is_user(env, mmu_idx); =20 *phys_ptr =3D address; + *page_size =3D TARGET_PAGE_SIZE; *prot =3D 0; =20 if (regime_translation_disabled(env, mmu_idx) || @@ -9675,16 +9677,12 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, rsize++; } } - if (rsize < TARGET_PAGE_BITS) { - qemu_log_mask(LOG_UNIMP, - "DRSR[%d]: No support for MPU (sub)region si= ze of" - " %" PRIu32 " bytes. Minimum is %d.\n", - n, (1 << rsize), TARGET_PAGE_SIZE); - continue; - } if (srdis) { continue; } + if (rsize < TARGET_PAGE_BITS) { + *page_size =3D 1 << rsize; + } break; } =20 @@ -9765,6 +9763,17 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, u= int32_t address, =20 fi->type =3D ARMFault_Permission; fi->level =3D 1; + /* + * Core QEMU code can't handle execution from small pages yet, so + * don't try it. This way we'll get an MPU exception, rather than + * eventually causing QEMU to exit in get_page_addr_code(). + */ + if (*page_size < TARGET_PAGE_SIZE && (*prot & PAGE_EXEC)) { + qemu_log_mask(LOG_UNIMP, + "MPU: No support for execution from regions " + "smaller than 1K\n"); + *prot &=3D ~PAGE_EXEC; + } return !(*prot & (1 << access_type)); } =20 @@ -10334,7 +10343,7 @@ static bool get_phys_addr(CPUARMState *env, target_= ulong address, } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret =3D get_phys_addr_pmsav7(env, address, access_type, mmu_id= x, - phys_ptr, prot, fi); + phys_ptr, prot, page_size, fi); } else { /* Pre-v7 MPU */ ret =3D get_phys_addr_pmsav5(env, address, access_type, mmu_id= x, @@ -10396,9 +10405,15 @@ bool arm_tlb_fill(CPUState *cs, vaddr address, core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, &attrs, &prot, &page_size, fi, NULL); if (!ret) { - /* Map a single [sub]page. */ - phys_addr &=3D TARGET_PAGE_MASK; - address &=3D TARGET_PAGE_MASK; + /* + * Map a single [sub]page. Regions smaller than our declared + * target page size are handled specially, so for those we + * pass in the exact addresses. + */ + if (page_size >=3D TARGET_PAGE_SIZE) { + phys_addr &=3D TARGET_PAGE_MASK; + address &=3D TARGET_PAGE_MASK; + } tlb_set_page_with_attrs(cs, address, phys_addr, attrs, prot, mmu_idx, page_size); return 0; --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530033431868231.60562194514932; Tue, 26 Jun 2018 10:17:11 -0700 (PDT) Received: from localhost ([::1]:54111 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXraZ-0000C0-0J for importer@patchew.org; Tue, 26 Jun 2018 13:17:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52043) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHM-0002Dm-VQ for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHL-0007J0-Gv for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:21 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43046) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHL-0007IZ-6B for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:19 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHK-0000CC-5O for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:18 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:51 +0100 Message-Id: <20180626165658.31394-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 25/32] target/arm: Handle small regions in get_phys_addr_pmsav8() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Allow ARMv8M to handle small MPU and SAU region sizes, by making get_phys_add_pmsav8() set the page size to the 1 if the MPU or SAU region covers less than a TARGET_PAGE_SIZE. We choose to use a size of 1 because it makes no difference to the core code, and avoids having to track both the base and limit for SAU and MPU and then convert into an artificially restricted "page size" that the core code will then ignore. Since the core TCG code can't handle execution from small MPU regions, we strip the exec permission from them so that any execution attempts will cause an MPU exception, rather than allowing it to end up with a cpu_abort() in get_page_addr_code(). (The previous code's intention was to make any small page be treated as having no permissions, but unfortunately errors in the implementation meant that it didn't behave that way. It's possible that some binaries using small regions were accidentally working with our old behaviour and won't now.) We also retain an existing bug, where we ignored the possibility that the SAU region might not cover the entire page, in the case of executable regions. This is necessary because some currently-working guest code images rely on being able to execute from addresses which are covered by a page-sized MPU region but a smaller SAU region. We can remove this workaround if we ever support execution from small regions. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20180620130619.11362-4-peter.maydell@linaro.org --- target/arm/helper.c | 78 ++++++++++++++++++++++++++++++++------------- 1 file changed, 55 insertions(+), 23 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a7edeb66633..3c6a4c565b1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -41,6 +41,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_u= long address, =20 /* Security attributes for an address, as returned by v8m_security_lookup.= */ typedef struct V8M_SAttributes { + bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE= */ bool ns; bool nsc; uint8_t sregion; @@ -9804,6 +9805,8 @@ static void v8m_security_lookup(CPUARMState *env, uin= t32_t address, int r; bool idau_exempt =3D false, idau_ns =3D true, idau_nsc =3D true; int idau_region =3D IREGION_NOTVALID; + uint32_t addr_page_base =3D address & TARGET_PAGE_MASK; + uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); =20 if (cpu->idau) { IDAUInterfaceClass *iic =3D IDAU_INTERFACE_GET_CLASS(cpu->idau); @@ -9841,6 +9844,9 @@ static void v8m_security_lookup(CPUARMState *env, uin= t32_t address, uint32_t limit =3D env->sau.rlar[r] | 0x1f; =20 if (base <=3D address && limit >=3D address) { + if (base > addr_page_base || limit < addr_page_limit) { + sattrs->subpage =3D true; + } if (sattrs->srvalid) { /* If we hit in more than one region then we must = report * as Secure, not NS-Callable, with no valid region @@ -9880,13 +9886,16 @@ static void v8m_security_lookup(CPUARMState *env, u= int32_t address, static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, ARMMMUFaultInfo *fi, uint32_t *mr= egion) + int *prot, bool *is_subpage, + ARMMMUFaultInfo *fi, uint32_t *mregion) { /* Perform a PMSAv8 MPU lookup (without also doing the SAU check * that a full phys-to-virt translation does). * mregion is (if not NULL) set to the region number which matched, * or -1 if no region number is returned (MPU off, address did not * hit a region, address hit in multiple regions). + * We set is_subpage to true if the region hit doesn't cover the + * entire TARGET_PAGE the address is within. */ ARMCPU *cpu =3D arm_env_get_cpu(env); bool is_user =3D regime_is_user(env, mmu_idx); @@ -9894,7 +9903,10 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint= 32_t address, int n; int matchregion =3D -1; bool hit =3D false; + uint32_t addr_page_base =3D address & TARGET_PAGE_MASK; + uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); =20 + *is_subpage =3D false; *phys_ptr =3D address; *prot =3D 0; if (mregion) { @@ -9932,6 +9944,10 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint= 32_t address, continue; } =20 + if (base > addr_page_base || limit < addr_page_limit) { + *is_subpage =3D true; + } + if (hit) { /* Multiple regions match -- always a failure (unlike * PMSAv7 where highest-numbered-region wins) @@ -9943,23 +9959,6 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint= 32_t address, =20 matchregion =3D n; hit =3D true; - - if (base & ~TARGET_PAGE_MASK) { - qemu_log_mask(LOG_UNIMP, - "MPU_RBAR[%d]: No support for MPU region bas= e" - "address of 0x%" PRIx32 ". Minimum alignment= is " - "%d\n", - n, base, TARGET_PAGE_BITS); - continue; - } - if ((limit + 1) & ~TARGET_PAGE_MASK) { - qemu_log_mask(LOG_UNIMP, - "MPU_RBAR[%d]: No support for MPU region lim= it" - "address of 0x%" PRIx32 ". Minimum alignment= is " - "%d\n", - n, limit, TARGET_PAGE_BITS); - continue; - } } } =20 @@ -9995,6 +9994,18 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint= 32_t address, =20 fi->type =3D ARMFault_Permission; fi->level =3D 1; + /* + * Core QEMU code can't handle execution from small pages yet, so + * don't try it. This means any attempted execution will generate + * an MPU exception, rather than eventually causing QEMU to exit in + * get_page_addr_code(). + */ + if (*is_subpage && (*prot & PAGE_EXEC)) { + qemu_log_mask(LOG_UNIMP, + "MPU: No support for execution from regions " + "smaller than 1K\n"); + *prot &=3D ~PAGE_EXEC; + } return !(*prot & (1 << access_type)); } =20 @@ -10002,10 +10013,13 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, u= int32_t address, static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_= idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, ARMMMUFaultInfo *fi) + int *prot, target_ulong *page_size, + ARMMMUFaultInfo *fi) { uint32_t secure =3D regime_is_secure(env, mmu_idx); V8M_SAttributes sattrs =3D {}; + bool ret; + bool mpu_is_subpage; =20 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); @@ -10033,6 +10047,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, = uint32_t address, } else { fi->type =3D ARMFault_QEMU_SFault; } + *page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZE; *phys_ptr =3D address; *prot =3D 0; return true; @@ -10055,6 +10070,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, = uint32_t address, * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). */ fi->type =3D ARMFault_QEMU_SFault; + *page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZE; *phys_ptr =3D address; *prot =3D 0; return true; @@ -10062,8 +10078,22 @@ static bool get_phys_addr_pmsav8(CPUARMState *env,= uint32_t address, } } =20 - return pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, - txattrs, prot, fi, NULL); + ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, + txattrs, prot, &mpu_is_subpage, fi, NULL); + /* + * TODO: this is a temporary hack to ignore the fact that the SAU regi= on + * is smaller than a page if this is an executable region. We never + * supported small MPU regions, but we did (accidentally) allow small + * SAU regions, and if we now made small SAU regions not be executable + * then this would break previously working guest code. We can't + * remove this until/unless we implement support for execution from + * small regions. + */ + if (*prot & PAGE_EXEC) { + sattrs.subpage =3D false; + } + *page_size =3D sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; + return ret; } =20 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, @@ -10339,7 +10369,7 @@ static bool get_phys_addr(CPUARMState *env, target_= ulong address, if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ ret =3D get_phys_addr_pmsav8(env, address, access_type, mmu_id= x, - phys_ptr, attrs, prot, fi); + phys_ptr, attrs, prot, page_size, f= i); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret =3D get_phys_addr_pmsav7(env, address, access_type, mmu_id= x, @@ -10757,6 +10787,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t = addr, uint32_t op) uint32_t mregion; bool targetpriv; bool targetsec =3D env->v7m.secure; + bool is_subpage; =20 /* Work out what the security state and privilege level we're * interested in is... @@ -10786,7 +10817,8 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t = addr, uint32_t op) if (arm_current_el(env) !=3D 0 || alt) { /* We can ignore the return value as prot is always set */ pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, - &phys_addr, &attrs, &prot, &fi, &mregion); + &phys_addr, &attrs, &prot, &is_subpage, + &fi, &mregion); if (mregion =3D=3D -1) { mrvalid =3D false; mregion =3D 0; --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530033590503354.08955677043605; Tue, 26 Jun 2018 10:19:50 -0700 (PDT) Received: from localhost ([::1]:54119 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrd3-0001iI-Op for importer@patchew.org; Tue, 26 Jun 2018 13:19:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52058) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHO-0002Ew-33 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHM-0007JW-H8 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:22 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43046) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHM-0007IZ-79 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:20 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHK-0000CT-U2 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:18 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:52 +0100 Message-Id: <20180626165658.31394-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 26/32] hw/arm/smmuv3: Fix translate error handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Jia He In case the STE's config is "Bypass" we currently don't set the IOMMUTLBEntry perm flags and the access does not succeed. Also if the config is 0b0xx (Aborted/Reserved), decode_ste and smmuv3_decode_config currently returns -EINVAL and we don't enter the expected code path: we record an event whereas we should not. This patch fixes those bugs and simplifies the error handling. decode_ste and smmuv3_decode_config now return 0 if aborted or bypassed config was found. Only bad config info produces negative error values. In smmuv3_translate we more clearly differentiate errors, bypass/smmu disabled, aborted and success cases. Also trace points are differentiated. Fixes: 9bde7f0674fe ("hw/arm/smmuv3: Implement translate callback") Reported-by: jia.he@hxt-semitech.com Signed-off-by: jia.he@hxt-semitech.com Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 1529653501-15358-2-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 12 ++++- hw/arm/smmuv3.c | 96 +++++++++++++++++++++++++++------------- hw/arm/trace-events | 7 +-- 3 files changed, 80 insertions(+), 35 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index a9d714b56e6..bab25d640eb 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -23,6 +23,14 @@ =20 #include "hw/arm/smmu-common.h" =20 +typedef enum SMMUTranslationStatus { + SMMU_TRANS_DISABLE, + SMMU_TRANS_ABORT, + SMMU_TRANS_BYPASS, + SMMU_TRANS_ERROR, + SMMU_TRANS_SUCCESS, +} SMMUTranslationStatus; + /* MMIO Registers */ =20 REG32(IDR0, 0x0) @@ -315,7 +323,7 @@ enum { /* Command completion notification */ /* Events */ =20 typedef enum SMMUEventType { - SMMU_EVT_OK =3D 0x00, + SMMU_EVT_NONE =3D 0x00, SMMU_EVT_F_UUT , SMMU_EVT_C_BAD_STREAMID , SMMU_EVT_F_STE_FETCH , @@ -337,7 +345,7 @@ typedef enum SMMUEventType { } SMMUEventType; =20 static const char *event_stringify[] =3D { - [SMMU_EVT_OK] =3D "SMMU_EVT_OK", + [SMMU_EVT_NONE] =3D "no recorded event", [SMMU_EVT_F_UUT] =3D "SMMU_EVT_F_UUT", [SMMU_EVT_C_BAD_STREAMID] =3D "SMMU_EVT_C_BAD_STREAMID", [SMMU_EVT_F_STE_FETCH] =3D "SMMU_EVT_F_STE_FETCH", diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 978330900d5..70b8f295aa9 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -23,6 +23,7 @@ #include "hw/qdev-core.h" #include "hw/pci/pci.h" #include "exec/address-spaces.h" +#include "cpu.h" #include "trace.h" #include "qemu/log.h" #include "qemu/error-report.h" @@ -154,7 +155,7 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo = *info) EVT_SET_SID(&evt, info->sid); =20 switch (info->type) { - case SMMU_EVT_OK: + case SMMU_EVT_NONE: return; case SMMU_EVT_F_UUT: EVT_SET_SSID(&evt, info->u.f_uut.ssid); @@ -312,12 +313,11 @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint= 32_t ssid, return 0; } =20 -/* Returns <0 if the caller has no need to continue the translation */ +/* Returns < 0 in case of invalid STE, 0 otherwise */ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, STE *ste, SMMUEventInfo *event) { uint32_t config; - int ret =3D -EINVAL; =20 if (!STE_VALID(ste)) { goto bad_ste; @@ -326,13 +326,13 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *c= fg, config =3D STE_CONFIG(ste); =20 if (STE_CFG_ABORT(config)) { - cfg->aborted =3D true; /* abort but don't record any event */ - return ret; + cfg->aborted =3D true; + return 0; } =20 if (STE_CFG_BYPASS(config)) { cfg->bypassed =3D true; - return ret; + return 0; } =20 if (STE_CFG_S2_ENABLED(config)) { @@ -509,7 +509,7 @@ bad_cd: * the different configuration decoding steps * @event: must be zero'ed by the caller * - * return < 0 if the translation needs to be aborted (@event is filled + * return < 0 in case of config decoding error (@event is filled * accordingly). Return 0 otherwise. */ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg, @@ -518,19 +518,26 @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr= , SMMUTransCfg *cfg, SMMUDevice *sdev =3D container_of(mr, SMMUDevice, iommu); uint32_t sid =3D smmu_get_sid(sdev); SMMUv3State *s =3D sdev->smmu; - int ret =3D -EINVAL; + int ret; STE ste; CD cd; =20 - if (smmu_find_ste(s, sid, &ste, event)) { + ret =3D smmu_find_ste(s, sid, &ste, event); + if (ret) { return ret; } =20 - if (decode_ste(s, cfg, &ste, event)) { + ret =3D decode_ste(s, cfg, &ste, event); + if (ret) { return ret; } =20 - if (smmu_get_cd(s, &ste, 0 /* ssid */, &cd, event)) { + if (cfg->aborted || cfg->bypassed) { + return 0; + } + + ret =3D smmu_get_cd(s, &ste, 0 /* ssid */, &cd, event); + if (ret) { return ret; } =20 @@ -543,8 +550,9 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, SMMUDevice *sdev =3D container_of(mr, SMMUDevice, iommu); SMMUv3State *s =3D sdev->smmu; uint32_t sid =3D smmu_get_sid(sdev); - SMMUEventInfo event =3D {.type =3D SMMU_EVT_OK, .sid =3D sid}; + SMMUEventInfo event =3D {.type =3D SMMU_EVT_NONE, .sid =3D sid}; SMMUPTWEventInfo ptw_info =3D {}; + SMMUTranslationStatus status; SMMUTransCfg cfg =3D {}; IOMMUTLBEntry entry =3D { .target_as =3D &address_space_memory, @@ -553,23 +561,28 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegi= on *mr, hwaddr addr, .addr_mask =3D ~(hwaddr)0, .perm =3D IOMMU_NONE, }; - int ret =3D 0; =20 if (!smmu_enabled(s)) { - goto out; + status =3D SMMU_TRANS_DISABLE; + goto epilogue; } =20 - ret =3D smmuv3_decode_config(mr, &cfg, &event); - if (ret) { - goto out; + if (smmuv3_decode_config(mr, &cfg, &event)) { + status =3D SMMU_TRANS_ERROR; + goto epilogue; } =20 if (cfg.aborted) { - goto out; + status =3D SMMU_TRANS_ABORT; + goto epilogue; } =20 - ret =3D smmu_ptw(&cfg, addr, flag, &entry, &ptw_info); - if (ret) { + if (cfg.bypassed) { + status =3D SMMU_TRANS_BYPASS; + goto epilogue; + } + + if (smmu_ptw(&cfg, addr, flag, &entry, &ptw_info)) { switch (ptw_info.type) { case SMMU_PTW_ERR_WALK_EABT: event.type =3D SMMU_EVT_F_WALK_EABT; @@ -609,18 +622,41 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegi= on *mr, hwaddr addr, default: g_assert_not_reached(); } + status =3D SMMU_TRANS_ERROR; + } else { + status =3D SMMU_TRANS_SUCCESS; } -out: - if (ret) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s translation failed for iova=3D0x%"PRIx64"(%d)\n", - mr->parent_obj.name, addr, ret); - entry.perm =3D IOMMU_NONE; - smmuv3_record_event(s, &event); - } else if (!cfg.aborted) { + +epilogue: + switch (status) { + case SMMU_TRANS_SUCCESS: entry.perm =3D flag; - trace_smmuv3_translate(mr->parent_obj.name, sid, addr, - entry.translated_addr, entry.perm); + trace_smmuv3_translate_success(mr->parent_obj.name, sid, addr, + entry.translated_addr, entry.perm); + break; + case SMMU_TRANS_DISABLE: + entry.perm =3D flag; + entry.addr_mask =3D ~TARGET_PAGE_MASK; + trace_smmuv3_translate_disable(mr->parent_obj.name, sid, addr, + entry.perm); + break; + case SMMU_TRANS_BYPASS: + entry.perm =3D flag; + entry.addr_mask =3D ~TARGET_PAGE_MASK; + trace_smmuv3_translate_bypass(mr->parent_obj.name, sid, addr, + entry.perm); + break; + case SMMU_TRANS_ABORT: + /* no event is recorded on abort */ + trace_smmuv3_translate_abort(mr->parent_obj.name, sid, addr, + entry.perm); + break; + case SMMU_TRANS_ERROR: + qemu_log_mask(LOG_GUEST_ERROR, + "%s translation failed for iova=3D0x%"PRIx64"(%s)\n", + mr->parent_obj.name, addr, smmu_event_string(event.t= ype)); + smmuv3_record_event(s, &event); + break; } =20 return entry; diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 2d927276021..0ab66bb4a86 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -33,9 +33,10 @@ smmuv3_record_event(const char *type, uint32_t sid) "%s = sid=3D%d" smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "SID:= 0x%x features:0x%x, sid_split:0x%x" smmuv3_find_ste_2lvl(uint64_t strtab_base, uint64_t l1ptr, int l1_ste_offs= et, uint64_t l2ptr, int l2_ste_offset, int max_l2_ste) "strtab_base:0x%"PRI= x64" l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64" l2_off:0x%x max_l2_st= e:%d" smmuv3_get_ste(uint64_t addr) "STE addr: 0x%"PRIx64 -smmuv3_translate_bypass(const char *n, uint16_t sid, uint64_t addr, bool i= s_write) "%s sid=3D%d bypass iova:0x%"PRIx64" is_write=3D%d" -smmuv3_translate_in(uint16_t sid, int pci_bus_num, uint64_t strtab_base) "= SID:0x%x bus:%d strtab_base:0x%"PRIx64 +smmuv3_translate_disable(const char *n, uint16_t sid, uint64_t addr, bool = is_write) "%s sid=3D%d bypass (smmu disabled) iova:0x%"PRIx64" is_write=3D%= d" +smmuv3_translate_bypass(const char *n, uint16_t sid, uint64_t addr, bool i= s_write) "%s sid=3D%d STE bypass iova:0x%"PRIx64" is_write=3D%d" +smmuv3_translate_abort(const char *n, uint16_t sid, uint64_t addr, bool is= _write) "%s sid=3D%d abort on iova:0x%"PRIx64" is_write=3D%d" +smmuv3_translate_success(const char *n, uint16_t sid, uint64_t iova, uint6= 4_t translated, int perm) "%s sid=3D%d iova=3D0x%"PRIx64" translated=3D0x%"= PRIx64" perm=3D0x%x" smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64 -smmuv3_translate(const char *n, uint16_t sid, uint64_t iova, uint64_t tran= slated, int perm) "%s sid=3D%d iova=3D0x%"PRIx64" translated=3D0x%"PRIx64" = perm=3D0x%x" smmuv3_decode_cd(uint32_t oas) "oas=3D%d" smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz= ) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d" --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 27/32] hw/arm/smmuv3: Cache/invalidate config data X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Eric Auger Let's cache config data to avoid fetching and parsing STE/CD structures on each translation. We invalidate them on data structure invalidation commands. We put in place a per-smmu mutex to protect the config cache. This will be useful too to protect the IOTLB cache. The caches can be accessed without BQL, ie. in IO dataplane. The same kind of mutex was put in place in the intel viommu. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 1529653501-15358-3-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 5 ++ include/hw/arm/smmuv3.h | 1 + hw/arm/smmu-common.c | 24 ++++++- hw/arm/smmuv3.c | 135 +++++++++++++++++++++++++++++++++-- hw/arm/trace-events | 6 ++ 5 files changed, 164 insertions(+), 7 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index c41eb5c3b00..7ce95ca0dcb 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -75,6 +75,8 @@ typedef struct SMMUDevice { int devfn; IOMMUMemoryRegion iommu; AddressSpace as; + uint32_t cfg_cache_hits; + uint32_t cfg_cache_misses; } SMMUDevice; =20 typedef struct SMMUNotifierNode { @@ -142,4 +144,7 @@ int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUA= ccessFlags perm, */ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova); =20 +/* Return the iommu mr associated to @sid, or NULL if none */ +IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid); + #endif /* HW_ARM_SMMU_COMMON */ diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 23f70363e54..36b2f452539 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -59,6 +59,7 @@ typedef struct SMMUv3State { SMMUQueue eventq, cmdq; =20 qemu_irq irq[4]; + QemuMutex mutex; } SMMUv3State; =20 typedef enum { diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 3c5f7245b52..db242c73dfb 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -310,6 +310,24 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, voi= d *opaque, int devfn) return &sdev->as; } =20 +IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid) +{ + uint8_t bus_n, devfn; + SMMUPciBus *smmu_bus; + SMMUDevice *smmu; + + bus_n =3D PCI_BUS_NUM(sid); + smmu_bus =3D smmu_find_smmu_pcibus(s, bus_n); + if (smmu_bus) { + devfn =3D sid & 0x7; + smmu =3D smmu_bus->pbdev[devfn]; + if (smmu) { + return &smmu->iommu; + } + } + return NULL; +} + static void smmu_base_realize(DeviceState *dev, Error **errp) { SMMUState *s =3D ARM_SMMU(dev); @@ -321,7 +339,7 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) error_propagate(errp, local_err); return; } - + s->configs =3D g_hash_table_new_full(NULL, NULL, NULL, g_free); s->smmu_pcibus_by_busptr =3D g_hash_table_new(NULL, NULL); =20 if (s->primary_bus) { @@ -333,7 +351,9 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) =20 static void smmu_base_reset(DeviceState *dev) { - /* will be filled later on */ + SMMUState *s =3D ARM_SMMU(dev); + + g_hash_table_remove_all(s->configs); } =20 static Property smmu_dev_properties[] =3D { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 70b8f295aa9..df704c26f8a 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -544,6 +544,58 @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr,= SMMUTransCfg *cfg, return decode_cd(cfg, &cd, event); } =20 +/** + * smmuv3_get_config - Look up for a cached copy of configuration data for + * @sdev and on cache miss performs a configuration structure decoding from + * guest RAM. + * + * @sdev: SMMUDevice handle + * @event: output event info + * + * The configuration cache contains data resulting from both STE and CD + * decoding under the form of an SMMUTransCfg struct. The hash table is in= dexed + * by the SMMUDevice handle. + */ +static SMMUTransCfg *smmuv3_get_config(SMMUDevice *sdev, SMMUEventInfo *ev= ent) +{ + SMMUv3State *s =3D sdev->smmu; + SMMUState *bc =3D &s->smmu_state; + SMMUTransCfg *cfg; + + cfg =3D g_hash_table_lookup(bc->configs, sdev); + if (cfg) { + sdev->cfg_cache_hits++; + trace_smmuv3_config_cache_hit(smmu_get_sid(sdev), + sdev->cfg_cache_hits, sdev->cfg_cache_misses, + 100 * sdev->cfg_cache_hits / + (sdev->cfg_cache_hits + sdev->cfg_cache_misses= )); + } else { + sdev->cfg_cache_misses++; + trace_smmuv3_config_cache_miss(smmu_get_sid(sdev), + sdev->cfg_cache_hits, sdev->cfg_cache_misses, + 100 * sdev->cfg_cache_hits / + (sdev->cfg_cache_hits + sdev->cfg_cache_misses= )); + cfg =3D g_new0(SMMUTransCfg, 1); + + if (!smmuv3_decode_config(&sdev->iommu, cfg, event)) { + g_hash_table_insert(bc->configs, sdev, cfg); + } else { + g_free(cfg); + cfg =3D NULL; + } + } + return cfg; +} + +static void smmuv3_flush_config(SMMUDevice *sdev) +{ + SMMUv3State *s =3D sdev->smmu; + SMMUState *bc =3D &s->smmu_state; + + trace_smmuv3_config_cache_inv(smmu_get_sid(sdev)); + g_hash_table_remove(bc->configs, sdev); +} + static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, IOMMUAccessFlags flag, int iommu_idx) { @@ -553,7 +605,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, SMMUEventInfo event =3D {.type =3D SMMU_EVT_NONE, .sid =3D sid}; SMMUPTWEventInfo ptw_info =3D {}; SMMUTranslationStatus status; - SMMUTransCfg cfg =3D {}; + SMMUTransCfg *cfg =3D NULL; IOMMUTLBEntry entry =3D { .target_as =3D &address_space_memory, .iova =3D addr, @@ -562,27 +614,30 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegi= on *mr, hwaddr addr, .perm =3D IOMMU_NONE, }; =20 + qemu_mutex_lock(&s->mutex); + if (!smmu_enabled(s)) { status =3D SMMU_TRANS_DISABLE; goto epilogue; } =20 - if (smmuv3_decode_config(mr, &cfg, &event)) { + cfg =3D smmuv3_get_config(sdev, &event); + if (!cfg) { status =3D SMMU_TRANS_ERROR; goto epilogue; } =20 - if (cfg.aborted) { + if (cfg->aborted) { status =3D SMMU_TRANS_ABORT; goto epilogue; } =20 - if (cfg.bypassed) { + if (cfg->bypassed) { status =3D SMMU_TRANS_BYPASS; goto epilogue; } =20 - if (smmu_ptw(&cfg, addr, flag, &entry, &ptw_info)) { + if (smmu_ptw(cfg, addr, flag, &entry, &ptw_info)) { switch (ptw_info.type) { case SMMU_PTW_ERR_WALK_EABT: event.type =3D SMMU_EVT_F_WALK_EABT; @@ -628,6 +683,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, } =20 epilogue: + qemu_mutex_unlock(&s->mutex); switch (status) { case SMMU_TRANS_SUCCESS: entry.perm =3D flag; @@ -664,6 +720,7 @@ epilogue: =20 static int smmuv3_cmdq_consume(SMMUv3State *s) { + SMMUState *bs =3D ARM_SMMU(s); SMMUCmdError cmd_error =3D SMMU_CERROR_NONE; SMMUQueue *q =3D &s->cmdq; SMMUCommandType type =3D 0; @@ -698,6 +755,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) =20 trace_smmuv3_cmdq_opcode(smmu_cmd_string(type)); =20 + qemu_mutex_lock(&s->mutex); switch (type) { case SMMU_CMD_SYNC: if (CMD_SYNC_CS(&cmd) & CMD_SYNC_SIG_IRQ) { @@ -706,10 +764,74 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) break; case SMMU_CMD_PREFETCH_CONFIG: case SMMU_CMD_PREFETCH_ADDR: + break; case SMMU_CMD_CFGI_STE: + { + uint32_t sid =3D CMD_SID(&cmd); + IOMMUMemoryRegion *mr =3D smmu_iommu_mr(bs, sid); + SMMUDevice *sdev; + + if (CMD_SSEC(&cmd)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + + if (!mr) { + break; + } + + trace_smmuv3_cmdq_cfgi_ste(sid); + sdev =3D container_of(mr, SMMUDevice, iommu); + smmuv3_flush_config(sdev); + + break; + } case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */ + { + uint32_t start =3D CMD_SID(&cmd), end, i; + uint8_t range =3D CMD_STE_RANGE(&cmd); + + if (CMD_SSEC(&cmd)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + + end =3D start + (1 << (range + 1)) - 1; + trace_smmuv3_cmdq_cfgi_ste_range(start, end); + + for (i =3D start; i <=3D end; i++) { + IOMMUMemoryRegion *mr =3D smmu_iommu_mr(bs, i); + SMMUDevice *sdev; + + if (!mr) { + continue; + } + sdev =3D container_of(mr, SMMUDevice, iommu); + smmuv3_flush_config(sdev); + } + break; + } case SMMU_CMD_CFGI_CD: case SMMU_CMD_CFGI_CD_ALL: + { + uint32_t sid =3D CMD_SID(&cmd); + IOMMUMemoryRegion *mr =3D smmu_iommu_mr(bs, sid); + SMMUDevice *sdev; + + if (CMD_SSEC(&cmd)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + + if (!mr) { + break; + } + + trace_smmuv3_cmdq_cfgi_cd(sid); + sdev =3D container_of(mr, SMMUDevice, iommu); + smmuv3_flush_config(sdev); + break; + } case SMMU_CMD_TLBI_NH_ALL: case SMMU_CMD_TLBI_NH_ASID: case SMMU_CMD_TLBI_NH_VA: @@ -735,6 +857,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) "Illegal command type: %d\n", CMD_TYPE(&cmd)); break; } + qemu_mutex_unlock(&s->mutex); if (cmd_error) { break; } @@ -1114,6 +1237,8 @@ static void smmu_realize(DeviceState *d, Error **errp) return; } =20 + qemu_mutex_init(&s->mutex); + memory_region_init_io(&sys->iomem, OBJECT(s), &smmu_mem_ops, sys, TYPE_ARM_SMMUV3, 0x20000); =20 diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 0ab66bb4a86..8ee4c21dd77 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -40,3 +40,9 @@ smmuv3_translate_success(const char *n, uint16_t sid, uin= t64_t iova, uint64_t tr smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64 smmuv3_decode_cd(uint32_t oas) "oas=3D%d" smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz= ) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d" +smmuv3_cmdq_cfgi_ste(int streamid) "streamid =3D%d" +smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=3D0x%d - end=3D0x%d" +smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid =3D %d" +smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" +smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" +smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d" --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530034016188611.8788936497381; Tue, 26 Jun 2018 10:26:56 -0700 (PDT) Received: from localhost ([::1]:54167 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrjz-00070C-Bm for importer@patchew.org; Tue, 26 Jun 2018 13:26:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52086) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHQ-0002Gs-0k for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHO-0007KL-4g for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:24 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43048) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHN-0007JA-PA for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:22 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHM-0000DM-DD for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:20 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:54 +0100 Message-Id: <20180626165658.31394-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 28/32] hw/arm/smmuv3: IOTLB emulation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Eric Auger We emulate a TLB cache of size SMMU_IOTLB_MAX_SIZE=3D256. It is implemented as a hash table whose key is a combination of the 16b asid and 48b IOVA (Jenkins hash). Entries are invalidated on TLB invalidation commands, either globally, or per asid, or per asid/iova. Signed-off-by: Eric Auger Message-id: 1529653501-15358-4-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 13 +++++ hw/arm/smmu-common.c | 60 ++++++++++++++++++++++ hw/arm/smmuv3.c | 98 ++++++++++++++++++++++++++++++++++-- hw/arm/trace-events | 9 ++++ 4 files changed, 176 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 7ce95ca0dcb..d173806f1a3 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -67,6 +67,8 @@ typedef struct SMMUTransCfg { uint8_t tbi; /* Top Byte Ignore */ uint16_t asid; SMMUTransTableInfo tt[2]; + uint32_t iotlb_hits; /* counts IOTLB hits for this asid */ + uint32_t iotlb_misses; /* counts IOTLB misses for this asid */ } SMMUTransCfg; =20 typedef struct SMMUDevice { @@ -89,6 +91,11 @@ typedef struct SMMUPciBus { SMMUDevice *pbdev[0]; /* Parent array is sparse, so dynamically allo= c */ } SMMUPciBus; =20 +typedef struct SMMUIOTLBKey { + uint64_t iova; + uint16_t asid; +} SMMUIOTLBKey; + typedef struct SMMUState { /* */ SysBusDevice dev; @@ -147,4 +154,10 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_a= ddr_t iova); /* Return the iommu mr associated to @sid, or NULL if none */ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid); =20 +#define SMMU_IOTLB_MAX_SIZE 256 + +void smmu_iotlb_inv_all(SMMUState *s); +void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); +void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova); + #endif /* HW_ARM_SMMU_COMMON */ diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index db242c73dfb..f66e444f6f4 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -24,11 +24,43 @@ #include "qom/cpu.h" #include "hw/qdev-properties.h" #include "qapi/error.h" +#include "qemu/jhash.h" =20 #include "qemu/error-report.h" #include "hw/arm/smmu-common.h" #include "smmu-internal.h" =20 +/* IOTLB Management */ + +inline void smmu_iotlb_inv_all(SMMUState *s) +{ + trace_smmu_iotlb_inv_all(); + g_hash_table_remove_all(s->iotlb); +} + +static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value, + gpointer user_data) +{ + uint16_t asid =3D *(uint16_t *)user_data; + SMMUIOTLBKey *iotlb_key =3D (SMMUIOTLBKey *)key; + + return iotlb_key->asid =3D=3D asid; +} + +inline void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t io= va) +{ + SMMUIOTLBKey key =3D {.asid =3D asid, .iova =3D iova}; + + trace_smmu_iotlb_inv_iova(asid, iova); + g_hash_table_remove(s->iotlb, &key); +} + +inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) +{ + trace_smmu_iotlb_inv_asid(asid); + g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid); +} + /* VMSAv8-64 Translation */ =20 /** @@ -328,6 +360,31 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_= t sid) return NULL; } =20 +static guint smmu_iotlb_key_hash(gconstpointer v) +{ + SMMUIOTLBKey *key =3D (SMMUIOTLBKey *)v; + uint32_t a, b, c; + + /* Jenkins hash */ + a =3D b =3D c =3D JHASH_INITVAL + sizeof(*key); + a +=3D key->asid; + b +=3D extract64(key->iova, 0, 32); + c +=3D extract64(key->iova, 32, 32); + + __jhash_mix(a, b, c); + __jhash_final(a, b, c); + + return c; +} + +static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2) +{ + const SMMUIOTLBKey *k1 =3D v1; + const SMMUIOTLBKey *k2 =3D v2; + + return (k1->asid =3D=3D k2->asid) && (k1->iova =3D=3D k2->iova); +} + static void smmu_base_realize(DeviceState *dev, Error **errp) { SMMUState *s =3D ARM_SMMU(dev); @@ -340,6 +397,8 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) return; } s->configs =3D g_hash_table_new_full(NULL, NULL, NULL, g_free); + s->iotlb =3D g_hash_table_new_full(smmu_iotlb_key_hash, smmu_iotlb_key= _equal, + g_free, g_free); s->smmu_pcibus_by_busptr =3D g_hash_table_new(NULL, NULL); =20 if (s->primary_bus) { @@ -354,6 +413,7 @@ static void smmu_base_reset(DeviceState *dev) SMMUState *s =3D ARM_SMMU(dev); =20 g_hash_table_remove_all(s->configs); + g_hash_table_remove_all(s->iotlb); } =20 static Property smmu_dev_properties[] =3D { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index df704c26f8a..b6dc7ed6de6 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -605,6 +605,10 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, SMMUEventInfo event =3D {.type =3D SMMU_EVT_NONE, .sid =3D sid}; SMMUPTWEventInfo ptw_info =3D {}; SMMUTranslationStatus status; + SMMUState *bs =3D ARM_SMMU(s); + uint64_t page_mask, aligned_addr; + IOMMUTLBEntry *cached_entry =3D NULL; + SMMUTransTableInfo *tt; SMMUTransCfg *cfg =3D NULL; IOMMUTLBEntry entry =3D { .target_as =3D &address_space_memory, @@ -613,6 +617,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, .addr_mask =3D ~(hwaddr)0, .perm =3D IOMMU_NONE, }; + SMMUIOTLBKey key, *new_key; =20 qemu_mutex_lock(&s->mutex); =20 @@ -637,7 +642,57 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, goto epilogue; } =20 - if (smmu_ptw(cfg, addr, flag, &entry, &ptw_info)) { + tt =3D select_tt(cfg, addr); + if (!tt) { + if (event.record_trans_faults) { + event.type =3D SMMU_EVT_F_TRANSLATION; + event.u.f_translation.addr =3D addr; + event.u.f_translation.rnw =3D flag & 0x1; + } + status =3D SMMU_TRANS_ERROR; + goto epilogue; + } + + page_mask =3D (1ULL << (tt->granule_sz)) - 1; + aligned_addr =3D addr & ~page_mask; + + key.asid =3D cfg->asid; + key.iova =3D aligned_addr; + + cached_entry =3D g_hash_table_lookup(bs->iotlb, &key); + if (cached_entry) { + cfg->iotlb_hits++; + trace_smmu_iotlb_cache_hit(cfg->asid, aligned_addr, + cfg->iotlb_hits, cfg->iotlb_misses, + 100 * cfg->iotlb_hits / + (cfg->iotlb_hits + cfg->iotlb_misses)); + if ((flag & IOMMU_WO) && !(cached_entry->perm & IOMMU_WO)) { + status =3D SMMU_TRANS_ERROR; + if (event.record_trans_faults) { + event.type =3D SMMU_EVT_F_PERMISSION; + event.u.f_permission.addr =3D addr; + event.u.f_permission.rnw =3D flag & 0x1; + } + } else { + status =3D SMMU_TRANS_SUCCESS; + } + goto epilogue; + } + + cfg->iotlb_misses++; + trace_smmu_iotlb_cache_miss(cfg->asid, addr & ~page_mask, + cfg->iotlb_hits, cfg->iotlb_misses, + 100 * cfg->iotlb_hits / + (cfg->iotlb_hits + cfg->iotlb_misses)); + + if (g_hash_table_size(bs->iotlb) >=3D SMMU_IOTLB_MAX_SIZE) { + smmu_iotlb_inv_all(bs); + } + + cached_entry =3D g_new0(IOMMUTLBEntry, 1); + + if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) { + g_free(cached_entry); switch (ptw_info.type) { case SMMU_PTW_ERR_WALK_EABT: event.type =3D SMMU_EVT_F_WALK_EABT; @@ -679,6 +734,10 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, } status =3D SMMU_TRANS_ERROR; } else { + new_key =3D g_new0(SMMUIOTLBKey, 1); + new_key->asid =3D cfg->asid; + new_key->iova =3D aligned_addr; + g_hash_table_insert(bs->iotlb, new_key, cached_entry); status =3D SMMU_TRANS_SUCCESS; } =20 @@ -687,6 +746,9 @@ epilogue: switch (status) { case SMMU_TRANS_SUCCESS: entry.perm =3D flag; + entry.translated_addr =3D cached_entry->translated_addr + + (addr & page_mask); + entry.addr_mask =3D cached_entry->addr_mask; trace_smmuv3_translate_success(mr->parent_obj.name, sid, addr, entry.translated_addr, entry.perm); break; @@ -832,10 +894,39 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) smmuv3_flush_config(sdev); break; } - case SMMU_CMD_TLBI_NH_ALL: case SMMU_CMD_TLBI_NH_ASID: - case SMMU_CMD_TLBI_NH_VA: + { + uint16_t asid =3D CMD_ASID(&cmd); + + trace_smmuv3_cmdq_tlbi_nh_asid(asid); + smmu_iotlb_inv_asid(bs, asid); + break; + } + case SMMU_CMD_TLBI_NH_ALL: + case SMMU_CMD_TLBI_NSNH_ALL: + trace_smmuv3_cmdq_tlbi_nh(); + smmu_iotlb_inv_all(bs); + break; case SMMU_CMD_TLBI_NH_VAA: + { + dma_addr_t addr =3D CMD_ADDR(&cmd); + uint16_t vmid =3D CMD_VMID(&cmd); + + trace_smmuv3_cmdq_tlbi_nh_vaa(vmid, addr); + smmu_iotlb_inv_all(bs); + break; + } + case SMMU_CMD_TLBI_NH_VA: + { + uint16_t asid =3D CMD_ASID(&cmd); + uint16_t vmid =3D CMD_VMID(&cmd); + dma_addr_t addr =3D CMD_ADDR(&cmd); + bool leaf =3D CMD_LEAF(&cmd); + + trace_smmuv3_cmdq_tlbi_nh_va(vmid, asid, addr, leaf); + smmu_iotlb_inv_iova(bs, asid, addr); + break; + } case SMMU_CMD_TLBI_EL3_ALL: case SMMU_CMD_TLBI_EL3_VA: case SMMU_CMD_TLBI_EL2_ALL: @@ -844,7 +935,6 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) case SMMU_CMD_TLBI_EL2_VAA: case SMMU_CMD_TLBI_S12_VMALL: case SMMU_CMD_TLBI_S2_IPA: - case SMMU_CMD_TLBI_NSNH_ALL: case SMMU_CMD_ATC_INV: case SMMU_CMD_PRI_RESP: case SMMU_CMD_RESUME: diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 8ee4c21dd77..be69c5ddfe4 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -12,6 +12,11 @@ smmu_ptw_invalid_pte(int stage, int level, uint64_t base= addr, uint64_t pteaddr, smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr,= uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=3D%d level=3D%d i= ova=3D0x%"PRIx64" base@=3D0x%"PRIx64" pte@=3D0x%"PRIx64" pte=3D0x%"PRIx64" = page address =3D 0x%"PRIx64 smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t ptead= dr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=3D%d le= vel=3D%d base@=3D0x%"PRIx64" pte@=3D0x%"PRIx64" pte=3D0x%"PRIx64" iova=3D0x= %"PRIx64" block address =3D 0x%"PRIx64" block size =3D %d MiB" smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte)= "baseaddr=3D0x%"PRIx64" index=3D0x%x, pteaddr=3D0x%"PRIx64", pte=3D0x%"PRI= x64 +smmu_iotlb_cache_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t = miss, uint32_t p) "IOTLB cache HIT asid=3D%d addr=3D0x%"PRIx64" hit=3D%d mi= ss=3D%d hit rate=3D%d" +smmu_iotlb_cache_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t= miss, uint32_t p) "IOTLB cache MISS asid=3D%d addr=3D0x%"PRIx64" hit=3D%d = miss=3D%d hit rate=3D%d" +smmu_iotlb_inv_all(void) "IOTLB invalidate all" +smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=3D%d" +smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid= =3D%d addr=3D0x%"PRIx64 =20 #hw/arm/smmuv3.c smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "= addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" @@ -45,4 +50,8 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=3D0= x%d - end=3D0x%d" smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid =3D %d" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" +smmuv3_cmdq_tlbi_nh_va(int vmid, int asid, uint64_t addr, bool leaf) "vmid= =3D%d asid =3D%d addr=3D0x%"PRIx64" leaf=3D%d" +smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid =3D%d addr=3D0x%"PR= Ix64 +smmuv3_cmdq_tlbi_nh(void) "" +smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d" --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 29/32] hw/arm/smmuv3: Add notifications on invalidation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Eric Auger On TLB invalidation commands, let's call registered IOMMU notifiers. Those can only be UNMAP notifiers. SMMUv3 does not support notification on MAP (VFIO). This patch allows vhost use case where IOTLB API is notified on each guest IOTLB invalidation. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 1529653501-15358-5-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 6 +++ hw/arm/smmu-common.c | 34 +++++++++++++ hw/arm/smmuv3.c | 99 +++++++++++++++++++++++++++++++++++- hw/arm/trace-events | 5 ++ 4 files changed, 142 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index d173806f1a3..50e2912a95e 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -160,4 +160,10 @@ void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova); =20 +/* Unmap the range of all the notifiers registered to any IOMMU mr */ +void smmu_inv_notifiers_all(SMMUState *s); + +/* Unmap the range of all the notifiers registered to @mr */ +void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr); + #endif /* HW_ARM_SMMU_COMMON */ diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index f66e444f6f4..3098915d07c 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -385,6 +385,40 @@ static gboolean smmu_iotlb_key_equal(gconstpointer v1,= gconstpointer v2) return (k1->asid =3D=3D k2->asid) && (k1->iova =3D=3D k2->iova); } =20 +/* Unmap the whole notifier's range */ +static void smmu_unmap_notifier_range(IOMMUNotifier *n) +{ + IOMMUTLBEntry entry; + + entry.target_as =3D &address_space_memory; + entry.iova =3D n->start; + entry.perm =3D IOMMU_NONE; + entry.addr_mask =3D n->end - n->start; + + memory_region_notify_one(n, &entry); +} + +/* Unmap all notifiers attached to @mr */ +inline void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr) +{ + IOMMUNotifier *n; + + trace_smmu_inv_notifiers_mr(mr->parent_obj.name); + IOMMU_NOTIFIER_FOREACH(n, mr) { + smmu_unmap_notifier_range(n); + } +} + +/* Unmap all notifiers of all mr's */ +void smmu_inv_notifiers_all(SMMUState *s) +{ + SMMUNotifierNode *node; + + QLIST_FOREACH(node, &s->notifiers_list, next) { + smmu_inv_notifiers_mr(&node->sdev->iommu); + } +} + static void smmu_base_realize(DeviceState *dev, Error **errp) { SMMUState *s =3D ARM_SMMU(dev); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index b6dc7ed6de6..39fbcbf577c 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -780,6 +780,68 @@ epilogue: return entry; } =20 +/** + * smmuv3_notify_iova - call the notifier @n for a given + * @asid and @iova tuple. + * + * @mr: IOMMU mr region handle + * @n: notifier to be called + * @asid: address space ID or negative value if we don't care + * @iova: iova + */ +static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, + IOMMUNotifier *n, + int asid, + dma_addr_t iova) +{ + SMMUDevice *sdev =3D container_of(mr, SMMUDevice, iommu); + SMMUEventInfo event =3D {}; + SMMUTransTableInfo *tt; + SMMUTransCfg *cfg; + IOMMUTLBEntry entry; + + cfg =3D smmuv3_get_config(sdev, &event); + if (!cfg) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s error decoding the configuration for iommu mr=3D= %s\n", + __func__, mr->parent_obj.name); + return; + } + + if (asid >=3D 0 && cfg->asid !=3D asid) { + return; + } + + tt =3D select_tt(cfg, iova); + if (!tt) { + return; + } + + entry.target_as =3D &address_space_memory; + entry.iova =3D iova; + entry.addr_mask =3D (1 << tt->granule_sz) - 1; + entry.perm =3D IOMMU_NONE; + + memory_region_notify_one(n, &entry); +} + +/* invalidate an asid/iova tuple in all mr's */ +static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t i= ova) +{ + SMMUNotifierNode *node; + + QLIST_FOREACH(node, &s->notifiers_list, next) { + IOMMUMemoryRegion *mr =3D &node->sdev->iommu; + IOMMUNotifier *n; + + trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova); + + IOMMU_NOTIFIER_FOREACH(n, mr) { + smmuv3_notify_iova(mr, n, asid, iova); + } + } +} + static int smmuv3_cmdq_consume(SMMUv3State *s) { SMMUState *bs =3D ARM_SMMU(s); @@ -899,12 +961,14 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) uint16_t asid =3D CMD_ASID(&cmd); =20 trace_smmuv3_cmdq_tlbi_nh_asid(asid); + smmu_inv_notifiers_all(&s->smmu_state); smmu_iotlb_inv_asid(bs, asid); break; } case SMMU_CMD_TLBI_NH_ALL: case SMMU_CMD_TLBI_NSNH_ALL: trace_smmuv3_cmdq_tlbi_nh(); + smmu_inv_notifiers_all(&s->smmu_state); smmu_iotlb_inv_all(bs); break; case SMMU_CMD_TLBI_NH_VAA: @@ -913,6 +977,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) uint16_t vmid =3D CMD_VMID(&cmd); =20 trace_smmuv3_cmdq_tlbi_nh_vaa(vmid, addr); + smmuv3_inv_notifiers_iova(bs, -1, addr); smmu_iotlb_inv_all(bs); break; } @@ -924,6 +989,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) bool leaf =3D CMD_LEAF(&cmd); =20 trace_smmuv3_cmdq_tlbi_nh_va(vmid, asid, addr, leaf); + smmuv3_inv_notifiers_iova(bs, asid, addr); smmu_iotlb_inv_iova(bs, asid, addr); break; } @@ -1402,9 +1468,38 @@ static void smmuv3_notify_flag_changed(IOMMUMemoryRe= gion *iommu, IOMMUNotifierFlag old, IOMMUNotifierFlag new) { + SMMUDevice *sdev =3D container_of(iommu, SMMUDevice, iommu); + SMMUv3State *s3 =3D sdev->smmu; + SMMUState *s =3D &(s3->smmu_state); + SMMUNotifierNode *node =3D NULL; + SMMUNotifierNode *next_node =3D NULL; + + if (new & IOMMU_NOTIFIER_MAP) { + int bus_num =3D pci_bus_num(sdev->bus); + PCIDevice *pcidev =3D pci_find_device(sdev->bus, bus_num, sdev->de= vfn); + + warn_report("SMMUv3 does not support notification on MAP: " + "device %s will not function properly", pcidev->name); + } + if (old =3D=3D IOMMU_NOTIFIER_NONE) { - warn_report("SMMUV3 does not support vhost/vfio integration yet: " - "devices of those types will not function properly"); + trace_smmuv3_notify_flag_add(iommu->parent_obj.name); + node =3D g_malloc0(sizeof(*node)); + node->sdev =3D sdev; + QLIST_INSERT_HEAD(&s->notifiers_list, node, next); + return; + } + + /* update notifier node with new flags */ + QLIST_FOREACH_SAFE(node, &s->notifiers_list, next, next_node) { + if (node->sdev =3D=3D sdev) { + if (new =3D=3D IOMMU_NOTIFIER_NONE) { + trace_smmuv3_notify_flag_del(iommu->parent_obj.name); + QLIST_REMOVE(node, next); + g_free(node); + } + return; + } } } =20 diff --git a/hw/arm/trace-events b/hw/arm/trace-events index be69c5ddfe4..27b11d655df 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -17,6 +17,7 @@ smmu_iotlb_cache_miss(uint16_t asid, uint64_t addr, uint3= 2_t hit, uint32_t miss, smmu_iotlb_inv_all(void) "IOTLB invalidate all" smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=3D%d" smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid= =3D%d addr=3D0x%"PRIx64 +smmu_inv_notifiers_mr(const char *name) "iommu mr=3D%s" =20 #hw/arm/smmuv3.c smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "= addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" @@ -55,3 +56,7 @@ smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid = =3D%d addr=3D0x%"PRIx64 smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d" +smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" +smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" +smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova) = "iommu mr=3D%s asid=3D%d iova=3D0x%"PRIx64 + --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 30/32] aspeed/scu: introduce clock frequencies X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: C=C3=A9dric Le Goater All Aspeed SoC clocks are driven by an input source clock which can have different frequencies : 24MHz or 25MHz, and also, on the Aspeed AST2400 SoC, 48MHz. The H-PLL (CPU) clock is defined from a calculation using parameters in the H-PLL Parameter register or from a predefined set of frequencies if the setting is strapped by hardware (Aspeed AST2400 SoC). The other clocks of the SoC are then defined from the H-PLL using dividers. We introduce first the APB clock because it should be used to drive the Aspeed timer model. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Andrew Jeffery Message-id: 20180622075700.5923-2-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/misc/aspeed_scu.h | 70 +++++++++++++++++++++-- hw/misc/aspeed_scu.c | 106 +++++++++++++++++++++++++++++++++++ 2 files changed, 172 insertions(+), 4 deletions(-) diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index d70cc0aeca6..f662c38188f 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -30,6 +30,10 @@ typedef struct AspeedSCUState { uint32_t hw_strap1; uint32_t hw_strap2; uint32_t hw_prot_key; + + uint32_t clkin; + uint32_t hpll; + uint32_t apb_freq; } AspeedSCUState; =20 #define AST2400_A0_SILICON_REV 0x02000303U @@ -58,7 +62,64 @@ extern bool is_supported_silicon_rev(uint32_t silicon_re= v); * 1. 2012/12/29 Ryan Chen Create */ =20 -/* Hardware Strapping Register definition (for Aspeed AST2400 SOC) +/* SCU08 Clock Selection Register + * + * 31 Enable Video Engine clock dynamic slow down + * 30:28 Video Engine clock slow down setting + * 27 2D Engine GCLK clock source selection + * 26 2D Engine GCLK clock throttling enable + * 25:23 APB PCLK divider selection + * 22:20 LPC Host LHCLK divider selection + * 19 LPC Host LHCLK clock generation/output enable control + * 18:16 MAC AHB bus clock divider selection + * 15 SD/SDIO clock running enable + * 14:12 SD/SDIO divider selection + * 11 Reserved + * 10:8 Video port output clock delay control bit + * 7 ARM CPU/AHB clock slow down enable + * 6:4 ARM CPU/AHB clock slow down setting + * 3:2 ECLK clock source selection + * 1 CPU/AHB clock slow down idle timer + * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4]) + */ +#define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7) + +/* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC) + * + * 18 H-PLL parameter selection + * 0: Select H-PLL by strapping resistors + * 1: Select H-PLL by the programmed registers (SCU24[17:0]) + * 17 Enable H-PLL bypass mode + * 16 Turn off H-PLL + * 10:5 H-PLL Numerator + * 4 H-PLL Output Divider + * 3:0 H-PLL Denumerator + * + * (Output frequency) =3D 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+= 1)] + */ + +#define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18) +#define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17) +#define SCU_AST2400_H_PLL_OFF (0x1 << 16) + +/* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC) + * + * 21 Enable H-PLL reset + * 20 Enable H-PLL bypass mode + * 19 Turn off H-PLL + * 18:13 H-PLL Post Divider + * 12:5 H-PLL Numerator (M) + * 4:0 H-PLL Denumerator (N) + * + * (Output frequency) =3D CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1) + * + * The default frequency is 792Mhz when CLKIN =3D 24MHz + */ + +#define SCU_H_PLL_BYPASS_EN (0x1 << 20) +#define SCU_H_PLL_OFF (0x1 << 19) + +/* SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC) * * 31:29 Software defined strapping registers * 28:27 DRAM size setting (for VGA driver use) @@ -107,12 +168,13 @@ extern bool is_supported_silicon_rev(uint32_t silicon= _rev); #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) <= < 1) \ | (((x) >> 18) & 0x1)) #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << = 18)) -#define AST2400_CLK_25M_IN (0x1 << 23) +#define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23) #define AST2400_CLK_24M_IN 0 #define AST2400_CLK_48M_IN 1 #define AST2400_CLK_25M_IN_24M_USB_CKI 2 #define AST2400_CLK_25M_IN_48M_USB_CKI 3 =20 +#define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18) #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) @@ -160,8 +222,8 @@ extern bool is_supported_silicon_rev(uint32_t silicon_r= ev); #define AST2400_DIS_BOOT 3 =20 /* - * Hardware strapping register definition (for Aspeed AST2500 SoC and - * higher) + * SCU70 Hardware strapping register definition (for Aspeed AST2500 + * SoC and higher) * * 31 Enable SPI Flash Strap Auto Fetch Mode * 30 Enable GPIO Strap Mode diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 59315010db9..59333b50abd 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -168,6 +168,27 @@ static uint32_t aspeed_scu_get_random(void) return num; } =20 +static void aspeed_scu_set_apb_freq(AspeedSCUState *s) +{ + uint32_t apb_divider; + + switch (s->silicon_rev) { + case AST2400_A0_SILICON_REV: + case AST2400_A1_SILICON_REV: + apb_divider =3D 2; + break; + case AST2500_A0_SILICON_REV: + case AST2500_A1_SILICON_REV: + apb_divider =3D 4; + break; + default: + g_assert_not_reached(); + } + + s->apb_freq =3D s->hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1) + / apb_divider; +} + static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) { AspeedSCUState *s =3D ASPEED_SCU(opaque); @@ -222,6 +243,10 @@ static void aspeed_scu_write(void *opaque, hwaddr offs= et, uint64_t data, case PROT_KEY: s->regs[reg] =3D (data =3D=3D ASPEED_SCU_PROT_KEY) ? 1 : 0; return; + case CLK_SEL: + s->regs[reg] =3D data; + aspeed_scu_set_apb_freq(s); + break; =20 case FREQ_CNTR_EVAL: case VGA_SCRATCH1 ... VGA_SCRATCH8: @@ -247,19 +272,93 @@ static const MemoryRegionOps aspeed_scu_ops =3D { .valid.unaligned =3D false, }; =20 +static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s) +{ + if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) { + return 25000000; + } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) { + return 48000000; + } else { + return 24000000; + } +} + +/* + * Strapped frequencies for the AST2400 in MHz. They depend on the + * clkin frequency. + */ +static const uint32_t hpll_ast2400_freqs[][4] =3D { + { 384, 360, 336, 408 }, /* 24MHz or 48MHz */ + { 400, 375, 350, 425 }, /* 25MHz */ +}; + +static uint32_t aspeed_scu_calc_hpll_ast2400(AspeedSCUState *s) +{ + uint32_t hpll_reg =3D s->regs[HPLL_PARAM]; + uint8_t freq_select; + bool clk_25m_in; + + if (hpll_reg & SCU_AST2400_H_PLL_OFF) { + return 0; + } + + if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) { + uint32_t multiplier =3D 1; + + if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) { + uint32_t n =3D (hpll_reg >> 5) & 0x3f; + uint32_t od =3D (hpll_reg >> 4) & 0x1; + uint32_t d =3D hpll_reg & 0xf; + + multiplier =3D (2 - od) * ((n + 2) / (d + 1)); + } + + return s->clkin * multiplier; + } + + /* HW strapping */ + clk_25m_in =3D !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN); + freq_select =3D SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1); + + return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000; +} + +static uint32_t aspeed_scu_calc_hpll_ast2500(AspeedSCUState *s) +{ + uint32_t hpll_reg =3D s->regs[HPLL_PARAM]; + uint32_t multiplier =3D 1; + + if (hpll_reg & SCU_H_PLL_OFF) { + return 0; + } + + if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) { + uint32_t p =3D (hpll_reg >> 13) & 0x3f; + uint32_t m =3D (hpll_reg >> 5) & 0xff; + uint32_t n =3D hpll_reg & 0x1f; + + multiplier =3D ((m + 1) / (n + 1)) / (p + 1); + } + + return s->clkin * multiplier; +} + static void aspeed_scu_reset(DeviceState *dev) { AspeedSCUState *s =3D ASPEED_SCU(dev); const uint32_t *reset; + uint32_t (*calc_hpll)(AspeedSCUState *s); =20 switch (s->silicon_rev) { case AST2400_A0_SILICON_REV: case AST2400_A1_SILICON_REV: reset =3D ast2400_a0_resets; + calc_hpll =3D aspeed_scu_calc_hpll_ast2400; break; case AST2500_A0_SILICON_REV: case AST2500_A1_SILICON_REV: reset =3D ast2500_a1_resets; + calc_hpll =3D aspeed_scu_calc_hpll_ast2500; break; default: g_assert_not_reached(); @@ -270,6 +369,13 @@ static void aspeed_scu_reset(DeviceState *dev) s->regs[HW_STRAP1] =3D s->hw_strap1; s->regs[HW_STRAP2] =3D s->hw_strap2; s->regs[PROT_KEY] =3D s->hw_prot_key; + + /* + * All registers are set. Now compute the frequencies of the main cloc= ks + */ + s->clkin =3D aspeed_scu_get_clkin(s); + s->hpll =3D calc_hpll(s); + aspeed_scu_set_apb_freq(s); } =20 static uint32_t aspeed_silicon_revs[] =3D { --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530034126642707.2316460509588; Tue, 26 Jun 2018 10:28:46 -0700 (PDT) Received: from localhost ([::1]:54179 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrlg-0008Bv-GI for importer@patchew.org; Tue, 26 Jun 2018 13:28:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52103) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHR-0002I5-1y for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHQ-0007LO-2e for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:25 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43052) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHP-0007L2-QU for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:24 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHO-0000Er-Nt for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:22 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:57 +0100 Message-Id: <20180626165658.31394-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 31/32] aspeed: initialize the SCU controller first X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: C=C3=A9dric Le Goater The System Control Unit should be initialized first as it drives all the configuration of the SoC and other device models. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Acked-by: Andrew Jeffery Message-id: 20180622075700.5923-3-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed_soc.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 1955a892f4a..7cc05ee27ea 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -109,18 +109,6 @@ static void aspeed_soc_init(Object *obj) object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type); object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL); =20 - object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC); - object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL); - qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default()); - - object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIM= ER); - object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NUL= L); - qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default()); - - object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C); - object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL); - qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default()); - object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU); object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL); qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); @@ -133,6 +121,18 @@ static void aspeed_soc_init(Object *obj) object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), "hw-prot-key", &error_abort); =20 + object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC); + object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL); + qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default()); + + object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIM= ER); + object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NUL= L); + qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default()); + + object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C); + object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL); + qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default()); + object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename); object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL); qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default()); @@ -195,6 +195,14 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE, &s->sram); =20 + /* SCU */ + object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE); + /* VIC */ object_property_set_bool(OBJECT(&s->vic), true, "realized", &err); if (err) { @@ -219,14 +227,6 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); } =20 - /* SCU */ - object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE); - /* UART - attach an 8250 to the IO space as our UART5 */ if (serial_hd(0)) { qemu_irq uart5 =3D qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]); --=20 2.17.1 From nobody Wed Apr 16 22:45:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530034235881815.3250418074442; Tue, 26 Jun 2018 10:30:35 -0700 (PDT) Received: from localhost ([::1]:54188 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrnO-00015N-Mw for importer@patchew.org; Tue, 26 Jun 2018 13:30:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52124) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXrHS-0002JV-1R for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXrHR-0007Ls-0t for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:26 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43052) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fXrHQ-0007L2-PE for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:57:24 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fXrHP-0000F8-Dl for qemu-devel@nongnu.org; Tue, 26 Jun 2018 17:57:23 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 17:56:58 +0100 Message-Id: <20180626165658.31394-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626165658.31394-1-peter.maydell@linaro.org> References: <20180626165658.31394-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 32/32] aspeed/timer: use the APB frequency from the SCU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: C=C3=A9dric Le Goater The timer controller can be driven by either an external 1MHz clock or by the APB clock. Today, the model makes the assumption that the APB frequency is always set to 24MHz but this is incorrect. The AST2400 SoC on the palmetto machines uses a 48MHz input clock source and the APB can be set to 48MHz. The consequence is a general system slowdown. The QEMU machines using the AST2500 SoC do not seem impacted today because the APB frequency is still set to 24MHz. We fix the timer frequency for all SoCs by linking the Timer model to the SCU model. The APB frequency driving the timers is now the one configured for the SoC. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Reviewed-by: Andrew Jeffery Message-id: 20180622075700.5923-4-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/timer/aspeed_timer.h | 4 ++++ hw/arm/aspeed_soc.c | 2 ++ hw/timer/aspeed_timer.c | 19 +++++++++++++++---- 3 files changed, 21 insertions(+), 4 deletions(-) diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_time= r.h index bd6c1a7f960..040a0887343 100644 --- a/include/hw/timer/aspeed_timer.h +++ b/include/hw/timer/aspeed_timer.h @@ -24,6 +24,8 @@ =20 #include "qemu/timer.h" =20 +typedef struct AspeedSCUState AspeedSCUState; + #define ASPEED_TIMER(obj) \ OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER); #define TYPE_ASPEED_TIMER "aspeed.timer" @@ -55,6 +57,8 @@ typedef struct AspeedTimerCtrlState { uint32_t ctrl; uint32_t ctrl2; AspeedTimer timers[ASPEED_TIMER_NR_TIMERS]; + + AspeedSCUState *scu; } AspeedTimerCtrlState; =20 #endif /* ASPEED_TIMER_H */ diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 7cc05ee27ea..e68911af0f9 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -127,6 +127,8 @@ static void aspeed_soc_init(Object *obj) =20 object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIM= ER); object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NUL= L); + object_property_add_const_link(OBJECT(&s->timerctrl), "scu", + OBJECT(&s->scu), &error_abort); qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default()); =20 object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C); diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 1e31e22b6f1..5e3f51b66b4 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -10,8 +10,10 @@ */ =20 #include "qemu/osdep.h" +#include "qapi/error.h" #include "hw/sysbus.h" #include "hw/timer/aspeed_timer.h" +#include "hw/misc/aspeed_scu.h" #include "qemu-common.h" #include "qemu/bitops.h" #include "qemu/timer.h" @@ -26,7 +28,6 @@ #define TIMER_CLOCK_USE_EXT true #define TIMER_CLOCK_EXT_HZ 1000000 #define TIMER_CLOCK_USE_APB false -#define TIMER_CLOCK_APB_HZ 24000000 =20 #define TIMER_REG_STATUS 0 #define TIMER_REG_RELOAD 1 @@ -80,11 +81,11 @@ static inline bool timer_external_clock(AspeedTimer *t) return timer_ctrl_status(t, op_external_clock); } =20 -static uint32_t clock_rates[] =3D { TIMER_CLOCK_APB_HZ, TIMER_CLOCK_EXT_HZ= }; - static inline uint32_t calculate_rate(struct AspeedTimer *t) { - return clock_rates[timer_external_clock(t)]; + AspeedTimerCtrlState *s =3D timer_to_ctrl(t); + + return timer_external_clock(t) ? TIMER_CLOCK_EXT_HZ : s->scu->apb_freq; } =20 static inline uint32_t calculate_ticks(struct AspeedTimer *t, uint64_t now= _ns) @@ -449,6 +450,16 @@ static void aspeed_timer_realize(DeviceState *dev, Err= or **errp) int i; SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); AspeedTimerCtrlState *s =3D ASPEED_TIMER(dev); + Object *obj; + Error *err =3D NULL; + + obj =3D object_property_get_link(OBJECT(dev), "scu", &err); + if (!obj) { + error_propagate(errp, err); + error_prepend(errp, "required link 'scu' not found: "); + return; + } + s->scu =3D ASPEED_SCU(obj); =20 for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { aspeed_init_one_timer(s, i); --=20 2.17.1