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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id 67-v6sm5054306pfm.171.2018.06.26.09.19.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 09:19:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZLDLSIgWDyjMaIqCuJWD2ApdwCfXx57NZz00pzO3yA4=; b=a4bOINB4Xq6m7fRXFVtj9H6ua5FFTAT0TUy/CD5Pk/hUzzAHbGvA27C0XIf0KpBXOV FIh65tTy7WnIEYnfo9pVw+W921YPr5bCafx7eDhqbj6F58jnhGGSuBYXkTSm/NBjay4h +2XKmgZk2WXV4AHfnkmLqQDh9kBw1rbEYV7Ds= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZLDLSIgWDyjMaIqCuJWD2ApdwCfXx57NZz00pzO3yA4=; b=hUvBf6ghHRTNB/PZs2irFeGsfEKqpYK/xp7DSiPS6L/TYjbUxiy8bMHX8V89KssRRW BvhSfmFi6qGzWzd4Y6XII4JbVKaXb9dR7Im5xbASg0jiOixAEMDzs15RKFWkEXuRDCuB qCDiEdZW9bSvM2hKMArg3QFdOIeUoz1el0a72GxsOr3Z6P5dpgraHs8Les1tAkmLpslE d9cXOjQKttd6A/rmqpHMK5tZPI0/vRcgekbewAkIim9H5uWzBZhNMG6gRA5fk6rgsYcS /6oWDat3Rb1zg21QjSB7q/46q2XmtsbEMQVVa9pIAqKomxOwm8jSOQXN+yspZdKfvfOY 6MOw== X-Gm-Message-State: APt69E3XW+fSi/+WuvD2fz/utl7+wPgh1bNMmyYDxzDFX/lmFu1bZaFZ grNrasN5cBTsZ/uYDEGiNkLgkQ8WslE= X-Google-Smtp-Source: AAOMgpdRNZl/0mQ/6q0pMsHtB7EpRYDosGBVf3+KoXbLtWCBQVEh3exnNH1HRItelP1eB+SPVwDcSA== X-Received: by 2002:a62:234a:: with SMTP id j71-v6mr2161861pfj.221.1530029967682; Tue, 26 Jun 2018 09:19:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 09:19:11 -0700 Message-Id: <20180626161921.27941-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626161921.27941-1-richard.henderson@linaro.org> References: <20180626161921.27941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22c Subject: [Qemu-devel] [PATCH 03/13] target/ppc: Use atomic store for STQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Section 1.4 of the Power ISA v3.0B states that this insn is single-copy atomic. As we cannot (yet) issue 128-bit loads within TCG, use the generic helpers provided. Signed-off-by: Richard Henderson --- target/ppc/helper.h | 4 ++++ target/ppc/mem_helper.c | 14 ++++++++++++++ target/ppc/translate.c | 35 +++++++++++++++++++++++++++-------- 3 files changed, 45 insertions(+), 8 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 3f451a5d7e..cbc1228570 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -803,4 +803,8 @@ DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, e= nv) #if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128) DEF_HELPER_FLAGS_3(lq_le_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) DEF_HELPER_FLAGS_3(lq_be_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) +DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG, + void, env, tl, i64, i64, i32) +DEF_HELPER_FLAGS_5(stq_be_parallel, TCG_CALL_NO_WG, + void, env, tl, i64, i64, i32) #endif diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 44a8f3445a..57e301edc3 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -231,6 +231,20 @@ uint64_t helper_lq_be_parallel(CPUPPCState *env, targe= t_ulong addr, env->retxh =3D int128_gethi(ret); return int128_getlo(ret); } + +void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr, + uint64_t lo, uint64_t hi, uint32_t opidx) +{ + Int128 val =3D int128_make128(lo, hi); + helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC()); +} + +void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr, + uint64_t lo, uint64_t hi, uint32_t opidx) +{ + Int128 val =3D int128_make128(lo, hi); + helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); +} #endif =20 /*************************************************************************= ****/ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0923cc24e3..3d63a62269 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2760,6 +2760,7 @@ static void gen_std(DisasContext *ctx) if ((ctx->opcode & 0x3) =3D=3D 0x2) { /* stq */ bool legal_in_user_mode =3D (ctx->insns_flags2 & PPC2_LSQ_ISA207) = !=3D 0; bool le_is_supported =3D (ctx->insns_flags2 & PPC2_LSQ_ISA207) != =3D 0; + TCGv hi, lo; =20 if (!(ctx->insns_flags & PPC_64BX)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); @@ -2783,20 +2784,38 @@ static void gen_std(DisasContext *ctx) EA =3D tcg_temp_new(); gen_addr_imm_index(ctx, EA, 0x03); =20 - /* We only need to swap high and low halves. gen_qemu_st64_i64 does - necessary 64-bit byteswap already. */ - if (unlikely(ctx->le_mode)) { - gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); + /* Note that the low part is always in RS+1, even in LE mode. */ + lo =3D cpu_gpr[rs + 1]; + hi =3D cpu_gpr[rs]; + + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { +#ifdef CONFIG_ATOMIC128 + TCGv_i32 oi =3D tcg_temp_new_i32(); + if (ctx->le_mode) { + tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); + gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); + } else { + tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); + gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); + } + tcg_temp_free_i32(oi); +#else + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; +#endif + } else if (ctx->le_mode) { + tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); gen_addr_add(ctx, EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); + tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); } else { - gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); + tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); gen_addr_add(ctx, EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); + tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); } tcg_temp_free(EA); } else { - /* std / stdu*/ + /* std / stdu */ if (Rc(ctx->opcode)) { if (unlikely(rA(ctx->opcode) =3D=3D 0)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); --=20 2.17.1