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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id 67-v6sm5054306pfm.171.2018.06.26.09.19.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 09:19:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZLWqrKTay5s2fLcjH27HhBkYzDQBc58NJK/v5oxeTOw=; b=OJtRphyMO5W1hGRRJOQNuoLYfZvRGvwLJ8R9OGgfhZD4soI6WtCd9xcck1F7k1Fk9D sLgnuKtjuxpTmCog9R1vwDSdvbpPEwUq7DMuqo4ylI97kh4yKNTxEty9dinmjpI+0MgL UGCkkO/kY2kNjIhy8w91Wrv6SjJcVhnAyEIzg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZLWqrKTay5s2fLcjH27HhBkYzDQBc58NJK/v5oxeTOw=; b=co/CBbOWaFjd+s2qt7PHO/H6oPX6G9Wytrhn80Bekd0+X0CL/b2UCrq2bR/KhOlIf3 HYs+GbMd3/5Q68GLzyLzrq0Z8pvfFnKjlKwdTiv64m6B2DSFSco+GnGaaW8OZSOqa9a3 V4rBPDrROyfNKZD8nAIkelONti74ksRR+zhMGPAUxtbcr0xgIOeOsAHkVRJu57FgR/FJ diGPZbWw09roXOGYpqgEWfOPGjohQe0aWnYl6R1JBJzyg4t6utfIELcbRzuI1IXXY0v1 EaWMFRw3ZjRozznubU0MEVn5onN5WEy9JgLgT5EvVt5zi0n2zEtkW2tHUk+WMwMnmEel NH4w== X-Gm-Message-State: APt69E2qmLJG3WMkaoHLioGYV+thcrTNtNQ/2OqvC8nc8Ugy2UzM1XzP rDR9/ohYqRPt0OSuL+016a9kty5bUaw= X-Google-Smtp-Source: AAOMgpcEHMQJVovtFzBEQ/VHexozRFm8J4lvrdqM40z7ivzKKfWucyB31bi3Jp646t6P0MuDpzirEg== X-Received: by 2002:a62:1fd6:: with SMTP id l83-v6mr2268806pfj.182.1530029964566; Tue, 26 Jun 2018 09:19:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 09:19:09 -0700 Message-Id: <20180626161921.27941-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626161921.27941-1-richard.henderson@linaro.org> References: <20180626161921.27941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22d Subject: [Qemu-devel] [PATCH 01/13] target/ppc: Add do_unaligned_access hook X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows faults from MO_ALIGN to have the same effect as from gen_check_align. Signed-off-by: Richard Henderson --- target/ppc/internal.h | 5 +++++ target/ppc/excp_helper.c | 18 +++++++++++++++++- target/ppc/translate_init.inc.c | 1 + 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 1f441c6483..a9bcadff42 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -252,4 +252,9 @@ static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPC= State *env) void helper_compute_fprf_float16(CPUPPCState *env, float16 arg); void helper_compute_fprf_float32(CPUPPCState *env, float32 arg); void helper_compute_fprf_float128(CPUPPCState *env, float128 arg); + +/* Raise a data fault alignment exception for the specified virtual addres= s */ +void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index c092fbead0..d6e97a90e0 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -22,7 +22,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" - +#include "internal.h" #include "helper_regs.h" =20 //#define DEBUG_OP @@ -1198,3 +1198,19 @@ void helper_book3s_msgsnd(target_ulong rb) qemu_mutex_unlock_iothread(); } #endif + +void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + CPUPPCState *env =3D cs->env_ptr; + uint32_t insn; + + /* Restore state and reload the insn we executed, for filling in DSISR= . */ + cpu_restore_state(cs, retaddr, true); + insn =3D cpu_ldl_code(env, env->nip); + + cs->exception_index =3D POWERPC_EXCP_ALIGN; + env->error_code =3D insn & 0x03FF0000; + cpu_loop_exit(cs); +} diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index 76d6f3fd5e..7813b1b004 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10457,6 +10457,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->set_pc =3D ppc_cpu_set_pc; cc->gdb_read_register =3D ppc_cpu_gdb_read_register; cc->gdb_write_register =3D ppc_cpu_gdb_write_register; + cc->do_unaligned_access =3D ppc_cpu_do_unaligned_access; #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D ppc_cpu_handle_mmu_fault; #else --=20 2.17.1 From nobody Tue Feb 10 05:08:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530030118639164.9062971248278; Tue, 26 Jun 2018 09:21:58 -0700 (PDT) Received: from localhost ([::1]:53759 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqj7-0002Nt-QV for importer@patchew.org; Tue, 26 Jun 2018 12:21:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42456) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqgo-0000vU-EW for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXqgh-0005s1-M8 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:34 -0400 Received: from mail-pl0-x243.google.com ([2607:f8b0:400e:c01::243]:32934) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fXqgh-0005rX-Dl for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:27 -0400 Received: by mail-pl0-x243.google.com with SMTP id 6-v6so8787020plb.0 for ; Tue, 26 Jun 2018 09:19:27 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id 67-v6sm5054306pfm.171.2018.06.26.09.19.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 09:19:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WOYcyxwnPL/xtD/5GTSRIornVsPuNrgBFi3p9AwKaiI=; b=D0yLALaBrkn/ij2yCUYF1zHfJTVs87SHjGQnvINNUof5xBJjt5srj4kWEVEo9Kyim2 t83d3vxyXYZCgCVHy04MXWXgGFNUIR+7I9KUEVQljIQ5lhpl6D3GgXyd7UIQ5i55obfe z5NARFQRkoO2KDTehfreNvAQTrJ3ua6Mrh0wk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WOYcyxwnPL/xtD/5GTSRIornVsPuNrgBFi3p9AwKaiI=; b=n709gJMnpXi2N/gVK7PMpPnq9hSWQy/KgelogtxErc94YarsQSq4Njxmk8NWBghOif chCy3ucH+kIwXNh6E8laL8L9/TfnI1KPhiTzEN4vEHzbrEzAmMiECgJlW+yG1I17tJd4 75VQbp6Zg+RuAl+pDBBA4kLIwMas1nOFrU36CSUSUA69c63+zH0hAam9LtxdcZo/pUdT iCVBPBF+Sm1whCNJtvZHaSAfaUjpqun1artC7+Ug71ssqt6xqNTraXytXXkN64B3rlXZ BGHVVtMtExOjIv7mzuIPKSpM+t/AjbWc4cQSNv9fmgnCXdb31geoK6pOyVk8W9O8drWV 5KYg== X-Gm-Message-State: APt69E2NIpZLfG3IcteHZXjozUZ+5RosXZY3Jmz7AUuR0uQJErVvwoYi pN0EbcuHlnaV/ur48+Dh2ixkBUEuKZM= X-Google-Smtp-Source: ADUXVKL5YoYxRhVH5f0a7kHv8CiZIekknqx+m5o2cycAz3FbVlvFtlxmC84Y5SXNiYrXt3hJWNPTog== X-Received: by 2002:a17:902:321:: with SMTP id 30-v6mr2401447pld.122.1530029966250; Tue, 26 Jun 2018 09:19:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 09:19:10 -0700 Message-Id: <20180626161921.27941-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626161921.27941-1-richard.henderson@linaro.org> References: <20180626161921.27941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH 02/13] target/ppc: Use atomic load for LQ and LQARX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Section 1.4 of the Power ISA v3.0B states that both of these instructions are single-copy atomic. As we cannot (yet) issue 128-bit loads within TCG, use the generic helpers provided. Since TCG cannot (yet) return a 128-bit value, add a slot within CPUPPCState for returning the high half of a 128-bit return value. This solution is preferred to the helper assigning to architectural registers directly, as it avoids clobbering all TCG live values. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 3 ++ target/ppc/helper.h | 5 +++ target/ppc/mem_helper.c | 20 ++++++++- target/ppc/translate.c | 93 ++++++++++++++++++++++++++++++----------- 4 files changed, 95 insertions(+), 26 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c7f3fb6b73..973cf44cda 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1015,6 +1015,9 @@ struct CPUPPCState { /* Next instruction pointer */ target_ulong nip; =20 + /* High part of 128-bit helper return. */ + uint64_t retxh; + int access_type; /* when a memory exception occurs, the access type is stored here */ =20 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index d751f0e219..3f451a5d7e 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -799,3 +799,8 @@ DEF_HELPER_4(dscliq, void, env, fprp, fprp, i32) =20 DEF_HELPER_1(tbegin, void, env) DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, env) + +#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128) +DEF_HELPER_FLAGS_3(lq_le_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) +DEF_HELPER_FLAGS_3(lq_be_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) +#endif diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index a34e604db3..44a8f3445a 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -21,9 +21,9 @@ #include "exec/exec-all.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" - #include "helper_regs.h" #include "exec/cpu_ldst.h" +#include "tcg.h" #include "internal.h" =20 //#define DEBUG_OP @@ -215,6 +215,24 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulo= ng addr, uint32_t reg, return i; } =20 +#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128) +uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr, + uint32_t opidx) +{ + Int128 ret =3D helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC()); + env->retxh =3D int128_gethi(ret); + return int128_getlo(ret); +} + +uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr, + uint32_t opidx) +{ + Int128 ret =3D helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC()); + env->retxh =3D int128_gethi(ret); + return int128_getlo(ret); +} +#endif + /*************************************************************************= ****/ /* Altivec extension helpers */ #if defined(HOST_WORDS_BIGENDIAN) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3a215a1dc6..0923cc24e3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2607,7 +2607,7 @@ static void gen_ld(DisasContext *ctx) static void gen_lq(DisasContext *ctx) { int ra, rd; - TCGv EA; + TCGv EA, hi, lo; =20 /* lq is a legal user mode instruction starting in ISA 2.07 */ bool legal_in_user_mode =3D (ctx->insns_flags2 & PPC2_LSQ_ISA207) !=3D= 0; @@ -2633,16 +2633,35 @@ static void gen_lq(DisasContext *ctx) EA =3D tcg_temp_new(); gen_addr_imm_index(ctx, EA, 0x0F); =20 - /* We only need to swap high and low halves. gen_qemu_ld64_i64 does - necessary 64-bit byteswap already. */ - if (unlikely(ctx->le_mode)) { - gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); + /* Note that the low part is always in RD+1, even in LE mode. */ + lo =3D cpu_gpr[rd + 1]; + hi =3D cpu_gpr[rd]; + + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { +#ifdef CONFIG_ATOMIC128 + TCGv_i32 oi =3D tcg_temp_new_i32(); + if (ctx->le_mode) { + tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); + gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); + } else { + tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); + gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); + } + tcg_temp_free_i32(oi); + tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); +#else + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; +#endif + } else if (ctx->le_mode) { + tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); gen_addr_add(ctx, EA, EA, 8); - gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); + tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); } else { - gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); + tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); gen_addr_add(ctx, EA, EA, 8); - gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); + tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); } tcg_temp_free(EA); } @@ -3236,9 +3255,8 @@ STCX(stdcx_, DEF_MEMOP(MO_Q)) /* lqarx */ static void gen_lqarx(DisasContext *ctx) { - TCGv EA; int rd =3D rD(ctx->opcode); - TCGv gpr1, gpr2; + TCGv EA, hi, lo; =20 if (unlikely((rd & 1) || (rd =3D=3D rA(ctx->opcode)) || (rd =3D=3D rB(ctx->opcode)))) { @@ -3247,24 +3265,49 @@ static void gen_lqarx(DisasContext *ctx) } =20 gen_set_access_type(ctx, ACCESS_RES); - EA =3D tcg_temp_local_new(); + EA =3D tcg_temp_new(); gen_addr_reg_index(ctx, EA); - gen_check_align(ctx, EA, 15); - if (unlikely(ctx->le_mode)) { - gpr1 =3D cpu_gpr[rd+1]; - gpr2 =3D cpu_gpr[rd]; - } else { - gpr1 =3D cpu_gpr[rd]; - gpr2 =3D cpu_gpr[rd+1]; - } - tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); - tcg_gen_mov_tl(cpu_reserve, EA); - gen_addr_add(ctx, EA, EA, 8); - tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); =20 - tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); - tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); + /* Note that the low part is always in RD+1, even in LE mode. */ + lo =3D cpu_gpr[rd + 1]; + hi =3D cpu_gpr[rd]; + + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { +#ifdef CONFIG_ATOMIC128 + TCGv_i32 oi =3D tcg_temp_new_i32(); + if (ctx->le_mode) { + tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, + ctx->mem_idx)); + gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); + } else { + tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, + ctx->mem_idx)); + gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); + } + tcg_temp_free_i32(oi); + tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); +#else + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + tcg_temp_free(EA); + return; +#endif + } else if (ctx->le_mode) { + tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); + tcg_gen_mov_tl(cpu_reserve, EA); + gen_addr_add(ctx, EA, EA, 8); + tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); + } else { + tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); + tcg_gen_mov_tl(cpu_reserve, EA); + gen_addr_add(ctx, EA, EA, 8); + tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); + } tcg_temp_free(EA); + + tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); + tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); } =20 /* stqcx. */ --=20 2.17.1 From nobody Tue Feb 10 05:08:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id 67-v6sm5054306pfm.171.2018.06.26.09.19.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 09:19:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZLDLSIgWDyjMaIqCuJWD2ApdwCfXx57NZz00pzO3yA4=; b=a4bOINB4Xq6m7fRXFVtj9H6ua5FFTAT0TUy/CD5Pk/hUzzAHbGvA27C0XIf0KpBXOV FIh65tTy7WnIEYnfo9pVw+W921YPr5bCafx7eDhqbj6F58jnhGGSuBYXkTSm/NBjay4h +2XKmgZk2WXV4AHfnkmLqQDh9kBw1rbEYV7Ds= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZLDLSIgWDyjMaIqCuJWD2ApdwCfXx57NZz00pzO3yA4=; b=hUvBf6ghHRTNB/PZs2irFeGsfEKqpYK/xp7DSiPS6L/TYjbUxiy8bMHX8V89KssRRW BvhSfmFi6qGzWzd4Y6XII4JbVKaXb9dR7Im5xbASg0jiOixAEMDzs15RKFWkEXuRDCuB qCDiEdZW9bSvM2hKMArg3QFdOIeUoz1el0a72GxsOr3Z6P5dpgraHs8Les1tAkmLpslE d9cXOjQKttd6A/rmqpHMK5tZPI0/vRcgekbewAkIim9H5uWzBZhNMG6gRA5fk6rgsYcS /6oWDat3Rb1zg21QjSB7q/46q2XmtsbEMQVVa9pIAqKomxOwm8jSOQXN+yspZdKfvfOY 6MOw== X-Gm-Message-State: APt69E3XW+fSi/+WuvD2fz/utl7+wPgh1bNMmyYDxzDFX/lmFu1bZaFZ grNrasN5cBTsZ/uYDEGiNkLgkQ8WslE= X-Google-Smtp-Source: AAOMgpdRNZl/0mQ/6q0pMsHtB7EpRYDosGBVf3+KoXbLtWCBQVEh3exnNH1HRItelP1eB+SPVwDcSA== X-Received: by 2002:a62:234a:: with SMTP id j71-v6mr2161861pfj.221.1530029967682; Tue, 26 Jun 2018 09:19:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 09:19:11 -0700 Message-Id: <20180626161921.27941-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626161921.27941-1-richard.henderson@linaro.org> References: <20180626161921.27941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22c Subject: [Qemu-devel] [PATCH 03/13] target/ppc: Use atomic store for STQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Section 1.4 of the Power ISA v3.0B states that this insn is single-copy atomic. As we cannot (yet) issue 128-bit loads within TCG, use the generic helpers provided. Signed-off-by: Richard Henderson --- target/ppc/helper.h | 4 ++++ target/ppc/mem_helper.c | 14 ++++++++++++++ target/ppc/translate.c | 35 +++++++++++++++++++++++++++-------- 3 files changed, 45 insertions(+), 8 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 3f451a5d7e..cbc1228570 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -803,4 +803,8 @@ DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, e= nv) #if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128) DEF_HELPER_FLAGS_3(lq_le_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) DEF_HELPER_FLAGS_3(lq_be_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) +DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG, + void, env, tl, i64, i64, i32) +DEF_HELPER_FLAGS_5(stq_be_parallel, TCG_CALL_NO_WG, + void, env, tl, i64, i64, i32) #endif diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 44a8f3445a..57e301edc3 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -231,6 +231,20 @@ uint64_t helper_lq_be_parallel(CPUPPCState *env, targe= t_ulong addr, env->retxh =3D int128_gethi(ret); return int128_getlo(ret); } + +void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr, + uint64_t lo, uint64_t hi, uint32_t opidx) +{ + Int128 val =3D int128_make128(lo, hi); + helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC()); +} + +void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr, + uint64_t lo, uint64_t hi, uint32_t opidx) +{ + Int128 val =3D int128_make128(lo, hi); + helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); +} #endif =20 /*************************************************************************= ****/ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0923cc24e3..3d63a62269 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2760,6 +2760,7 @@ static void gen_std(DisasContext *ctx) if ((ctx->opcode & 0x3) =3D=3D 0x2) { /* stq */ bool legal_in_user_mode =3D (ctx->insns_flags2 & PPC2_LSQ_ISA207) = !=3D 0; bool le_is_supported =3D (ctx->insns_flags2 & PPC2_LSQ_ISA207) != =3D 0; + TCGv hi, lo; =20 if (!(ctx->insns_flags & PPC_64BX)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); @@ -2783,20 +2784,38 @@ static void gen_std(DisasContext *ctx) EA =3D tcg_temp_new(); gen_addr_imm_index(ctx, EA, 0x03); =20 - /* We only need to swap high and low halves. gen_qemu_st64_i64 does - necessary 64-bit byteswap already. */ - if (unlikely(ctx->le_mode)) { - gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); + /* Note that the low part is always in RS+1, even in LE mode. */ + lo =3D cpu_gpr[rs + 1]; + hi =3D cpu_gpr[rs]; + + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { +#ifdef CONFIG_ATOMIC128 + TCGv_i32 oi =3D tcg_temp_new_i32(); + if (ctx->le_mode) { + tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); + gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); + } else { + tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); + gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); + } + tcg_temp_free_i32(oi); +#else + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; +#endif + } else if (ctx->le_mode) { + tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); gen_addr_add(ctx, EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); + tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); } else { - gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); + tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); gen_addr_add(ctx, EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); + tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); } tcg_temp_free(EA); } else { - /* std / stdu*/ + /* std / stdu */ if (Rc(ctx->opcode)) { if (unlikely(rA(ctx->opcode) =3D=3D 0)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); --=20 2.17.1 From nobody Tue Feb 10 05:08:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153003065264827.527729842607073; Tue, 26 Jun 2018 09:30:52 -0700 (PDT) Received: from localhost ([::1]:53824 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqrj-0001S3-RW for importer@patchew.org; Tue, 26 Jun 2018 12:30:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42470) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqgp-0000vb-7p for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXqgl-0005tp-12 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:35 -0400 Received: from mail-pl0-x22d.google.com ([2607:f8b0:400e:c01::22d]:39942) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fXqgk-0005tU-Of for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:30 -0400 Received: by mail-pl0-x22d.google.com with SMTP id t6-v6so3431722plo.7 for ; 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id 67-v6sm5054306pfm.171.2018.06.26.09.19.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 09:19:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=11623Q9N35sn4n0cdJ5SZiaWyungWhuQfe2dol9yZ90=; b=czVVSGjzYHyIXvNhiRshj+Y5I+VsXZMrCrb/3GwOgM5ItP3hetBsOnnvXcnCL82/9C Zm/YhitbHO72LClY3Ef8Dx5Hgi71kFRVlY7WURGjUHSmkXXugodaV6zg2yRlSbOMyQ/w UiojWMYkEGKrN8+uypnliJTfqZBi7nqNrIhR8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=11623Q9N35sn4n0cdJ5SZiaWyungWhuQfe2dol9yZ90=; b=tVt4KXpu25NbEwdR19a6lEnrfjnDRySKMsdq0Slz6trKEdm68g2sbkQfgr+4ADrt8K TcjGZ/EDv+kl0rO8zR3G67vwiIvFRLkZoEMAPEZbzyDfx7YO/jL72sy5JE//dT7Odfb0 WHmyuQ2DVtleAwH6tBGIqOT55ZeS4QYQA9bzoITxwwKSsjfgyjNAd524H8XWVh4Lp+XK MCJWK292YHeSut1Bm13nWCYAkF3h36ZpX3/PCB7jJUzWdZDaIoHrn7MXawvGRVveAfu/ pQAsnnYVKhGGlqnKjD27PKVbOn3N/C/6XozZFQAmYy4lErqAogTVHJ9saQiLfWnB2lyj ygkw== X-Gm-Message-State: APt69E0TNNh6T2gcY67gzk1iJNg4cxtWLOwuyrDypGSuaw58paY3y1f9 +QWk0Em43Si30VDEYJec0fZCk6XTHz8= X-Google-Smtp-Source: ADUXVKLdds/BXplaHG5c6LTb+w8IAzhH7vr2GgNWh8P0lrQrYhtrFeyMTC2WkiwC+5TjeTrmrunZXg== X-Received: by 2002:a17:902:d688:: with SMTP id v8-v6mr2358559ply.59.1530029969493; Tue, 26 Jun 2018 09:19:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 09:19:12 -0700 Message-Id: <20180626161921.27941-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626161921.27941-1-richard.henderson@linaro.org> References: <20180626161921.27941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22d Subject: [Qemu-devel] [PATCH 04/13] target/ppc: Use atomic cmpxchg for STQCX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When running in a parallel context, we must use a helper in order to perform the 128-bit atomic operation. When running in a serial context, do the compare before the store. Signed-off-by: Richard Henderson --- target/ppc/helper.h | 2 + target/ppc/mem_helper.c | 38 +++++++++++++++++ target/ppc/translate.c | 95 ++++++++++++++++++++++++++--------------- 3 files changed, 101 insertions(+), 34 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index cbc1228570..5706c2497f 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -807,4 +807,6 @@ DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG, void, env, tl, i64, i64, i32) DEF_HELPER_FLAGS_5(stq_be_parallel, TCG_CALL_NO_WG, void, env, tl, i64, i64, i32) +DEF_HELPER_5(stqcx_le_parallel, i32, env, tl, i64, i64, i32) +DEF_HELPER_5(stqcx_be_parallel, i32, env, tl, i64, i64, i32) #endif diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 57e301edc3..8f0d86d104 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -245,6 +245,44 @@ void helper_stq_be_parallel(CPUPPCState *env, target_u= long addr, Int128 val =3D int128_make128(lo, hi); helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); } + +uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr, + uint64_t new_lo, uint64_t new_hi, + uint32_t opidx) +{ + bool success =3D false; + + if (likely(addr =3D=3D env->reserve_addr)) { + Int128 oldv, cmpv, newv; + + cmpv =3D int128_make128(env->reserve_val2, env->reserve_val); + newv =3D int128_make128(new_lo, new_hi); + oldv =3D helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, + opidx, GETPC()); + success =3D int128_eq(oldv, cmpv); + } + env->reserve_addr =3D -1; + return env->so + success * CRF_EQ_BIT; +} + +uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr, + uint64_t new_lo, uint64_t new_hi, + uint32_t opidx) +{ + bool success =3D false; + + if (likely(addr =3D=3D env->reserve_addr)) { + Int128 oldv, cmpv, newv; + + cmpv =3D int128_make128(env->reserve_val2, env->reserve_val); + newv =3D int128_make128(new_lo, new_hi); + oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, + opidx, GETPC()); + success =3D int128_eq(oldv, cmpv); + } + env->reserve_addr =3D -1; + return env->so + success * CRF_EQ_BIT; +} #endif =20 /*************************************************************************= ****/ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3d63a62269..c7b9d226eb 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3332,50 +3332,77 @@ static void gen_lqarx(DisasContext *ctx) /* stqcx. */ static void gen_stqcx_(DisasContext *ctx) { - TCGv EA; - int reg =3D rS(ctx->opcode); - int len =3D 16; -#if !defined(CONFIG_USER_ONLY) - TCGLabel *l1; - TCGv gpr1, gpr2; -#endif + int rs =3D rS(ctx->opcode); + TCGv EA, hi, lo; =20 - if (unlikely((rD(ctx->opcode) & 1))) { + if (unlikely(rs & 1)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); return; } + gen_set_access_type(ctx, ACCESS_RES); - EA =3D tcg_temp_local_new(); + EA =3D tcg_temp_new(); gen_addr_reg_index(ctx, EA); - if (len > 1) { - gen_check_align(ctx, EA, (len) - 1); - } =20 -#if defined(CONFIG_USER_ONLY) - gen_conditional_store(ctx, EA, reg, 16); + /* Note that the low part is always in RS+1, even in LE mode. */ + lo =3D cpu_gpr[rs + 1]; + hi =3D cpu_gpr[rs]; + + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + TCGv_i32 oi =3D tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); +#ifdef CONFIG_ATOMIC128 + if (ctx->le_mode) { + gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, = oi); + } else { + gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, = oi); + } #else - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - l1 =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); - tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); - - if (unlikely(ctx->le_mode)) { - gpr1 =3D cpu_gpr[reg + 1]; - gpr2 =3D cpu_gpr[reg]; - } else { - gpr1 =3D cpu_gpr[reg]; - gpr2 =3D cpu_gpr[reg + 1]; - } - tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); - gen_addr_add(ctx, EA, EA, 8); - tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); - - gen_set_label(l1); - tcg_gen_movi_tl(cpu_reserve, -1); + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; #endif - tcg_temp_free(EA); -} + tcg_temp_free(EA); + tcg_temp_free_i32(oi); + } else { + TCGLabel *lab_fail =3D gen_new_label(); + TCGLabel *lab_over =3D gen_new_label(); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); =20 + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); + tcg_temp_free(EA); + + gen_qemu_ld64_i64(ctx, t0, cpu_reserve); + tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode + ? offsetof(CPUPPCState, reserve_val2) + : offsetof(CPUPPCState, reserve_val))= ); + tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); + + tcg_gen_addi_i64(t0, cpu_reserve, 8); + gen_qemu_ld64_i64(ctx, t0, t0); + tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode + ? offsetof(CPUPPCState, reserve_val) + : offsetof(CPUPPCState, reserve_val2)= )); + tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); + + /* Success */ + gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); + tcg_gen_addi_i64(t0, cpu_reserve, 8); + gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); + + tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); + tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); + tcg_gen_br(lab_over); + + gen_set_label(lab_fail); + tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); + + gen_set_label(lab_over); + tcg_gen_movi_tl(cpu_reserve, -1); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + } +} #endif /* defined(TARGET_PPC64) */ =20 /* sync */ --=20 2.17.1 From nobody Tue Feb 10 05:08:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530030709436739.9949896563916; Tue, 26 Jun 2018 09:31:49 -0700 (PDT) Received: from localhost ([::1]:53826 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqse-0002AM-JD for importer@patchew.org; Tue, 26 Jun 2018 12:31:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42545) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqgs-0000zd-KY for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXqgm-0005ud-Ks for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:38 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:46409) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fXqgm-0005uA-Ce for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:32 -0400 Received: by mail-pl0-x244.google.com with SMTP id 30-v6so8763634pld.13 for ; Tue, 26 Jun 2018 09:19:32 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id 67-v6sm5054306pfm.171.2018.06.26.09.19.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 09:19:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pokBvmOFXHrOHjr/EsOMYde6oJaivnnQyUK2iRji43M=; b=Qwx2Q+rtrhrIRaE5/CjUBttjHHDVRyG1AkgHRDr5O31cL8u0UebdaAGgPjsz+4uwR0 0sOVrsaSt3mRZn6r5yXjLkfc3AuMIJrFuOcX/lLP9bGCbRRrqNSMGfCgva06KUQCfr2k aG/EVYHgr0J0mD3/2ZvjVIoteDH2P+gXu/xJw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pokBvmOFXHrOHjr/EsOMYde6oJaivnnQyUK2iRji43M=; b=HI86/q7XvRcRzD1UeEGnuaHQ86pZNwQlEKsK85txZj0HmBNJa3KRMIsuUKH1gb1vTX ZttYeD+GiIUOXWoGfLtEGg1SSl/KSs791wrj3YO356A89KkK8GAW/nuQ2Aed6+bI+6NH TkFKOl8UearGjP2na9mm5oNSzb5NNfrSPnNHvj6A1a7cRY1MGE+A2vuyPJh/dv48riqj zGsNu1FCBzOmmmYks6Gj4DidEtsgnMAeoXRcftxKWrKNyhM9SuPcDRPt4bE0W3B6IIPW EjmrpU6Flv+T2olm75/gJSp+CGbrv7/YDoucGeYLiaaMXhCAV0se0ZQUkocKvXCBwWKW kKBg== X-Gm-Message-State: APt69E0IPXdJS5Qnf2zCZqQXe5bCwLD/g0nsCq9o9TW3GF6g7VcZZ4WU /9nWrWIkpiiZ0MFEZFnbDLYpbh0dxTg= X-Google-Smtp-Source: ADUXVKLE7/rxqIIsJscIs5rXH4klVpF1O2wtgPEmqIM2n6VSNyuzKuMWq2IF0UhaSZQ6+pnm9Sdagw== X-Received: by 2002:a17:902:48c8:: with SMTP id u8-v6mr2344763plh.152.1530029971118; Tue, 26 Jun 2018 09:19:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 09:19:13 -0700 Message-Id: <20180626161921.27941-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626161921.27941-1-richard.henderson@linaro.org> References: <20180626161921.27941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH 05/13] target/ppc: Remove POWERPC_EXCP_STCX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Always use the gen_conditional_store implementation that uses atomic_cmpxchg. Make sure and clear reserve_addr across most interrupts crossing the cpu_loop. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 5 -- linux-user/ppc/cpu_loop.c | 123 +++++++------------------------------- target/ppc/translate.c | 14 ----- 3 files changed, 23 insertions(+), 119 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 973cf44cda..4edcf62cf7 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -196,7 +196,6 @@ enum { /* QEMU exceptions: special cases we want to stop translation = */ POWERPC_EXCP_SYNC =3D 0x202, /* context synchronizing instruct= ion */ POWERPC_EXCP_SYSCALL_USER =3D 0x203, /* System call in user mode only = */ - POWERPC_EXCP_STCX =3D 0x204 /* Conditional stores in user mode= */ }; =20 /* Exceptions error codes = */ @@ -994,10 +993,6 @@ struct CPUPPCState { /* Reservation value */ target_ulong reserve_val; target_ulong reserve_val2; - /* Reservation store address */ - target_ulong reserve_ea; - /* Reserved store source register and size */ - target_ulong reserve_info; =20 /* Those ones are used in supervisor mode only */ /* machine state register */ diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 2fb516cb00..133a87f349 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -65,99 +65,23 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32= _t val) return -1; } =20 -static int do_store_exclusive(CPUPPCState *env) -{ - target_ulong addr; - target_ulong page_addr; - target_ulong val, val2 __attribute__((unused)) =3D 0; - int flags; - int segv =3D 0; - - addr =3D env->reserve_ea; - page_addr =3D addr & TARGET_PAGE_MASK; - start_exclusive(); - mmap_lock(); - flags =3D page_get_flags(page_addr); - if ((flags & PAGE_READ) =3D=3D 0) { - segv =3D 1; - } else { - int reg =3D env->reserve_info & 0x1f; - int size =3D env->reserve_info >> 5; - int stored =3D 0; - - if (addr =3D=3D env->reserve_addr) { - switch (size) { - case 1: segv =3D get_user_u8(val, addr); break; - case 2: segv =3D get_user_u16(val, addr); break; - case 4: segv =3D get_user_u32(val, addr); break; -#if defined(TARGET_PPC64) - case 8: segv =3D get_user_u64(val, addr); break; - case 16: { - segv =3D get_user_u64(val, addr); - if (!segv) { - segv =3D get_user_u64(val2, addr + 8); - } - break; - } -#endif - default: abort(); - } - if (!segv && val =3D=3D env->reserve_val) { - val =3D env->gpr[reg]; - switch (size) { - case 1: segv =3D put_user_u8(val, addr); break; - case 2: segv =3D put_user_u16(val, addr); break; - case 4: segv =3D put_user_u32(val, addr); break; -#if defined(TARGET_PPC64) - case 8: segv =3D put_user_u64(val, addr); break; - case 16: { - if (val2 =3D=3D env->reserve_val2) { - if (msr_le) { - val2 =3D val; - val =3D env->gpr[reg+1]; - } else { - val2 =3D env->gpr[reg+1]; - } - segv =3D put_user_u64(val, addr); - if (!segv) { - segv =3D put_user_u64(val2, addr + 8); - } - } - break; - } -#endif - default: abort(); - } - if (!segv) { - stored =3D 1; - } - } - } - env->crf[0] =3D (stored << 1) | xer_so; - env->reserve_addr =3D (target_ulong)-1; - } - if (!segv) { - env->nip +=3D 4; - } - mmap_unlock(); - end_exclusive(); - return segv; -} - void cpu_loop(CPUPPCState *env) { CPUState *cs =3D CPU(ppc_env_get_cpu(env)); target_siginfo_t info; - int trapnr; + int trapnr, sig; target_ulong ret; =20 for(;;) { + bool arch_interrupt; + cpu_exec_start(cs); trapnr =3D cpu_exec(cs); cpu_exec_end(cs); process_queued_cpu_work(cs); =20 - switch(trapnr) { + arch_interrupt =3D true; + switch (trapnr) { case POWERPC_EXCP_NONE: /* Just go on */ break; @@ -524,26 +448,15 @@ void cpu_loop(CPUPPCState *env) } env->gpr[3] =3D ret; break; - case POWERPC_EXCP_STCX: - if (do_store_exclusive(env)) { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->nip; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_DEBUG: - { - int sig; - - sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) { - info.si_signo =3D sig; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } + sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) { + info.si_signo =3D sig; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } else { + arch_interrupt =3D false; } break; case EXCP_INTERRUPT: @@ -551,12 +464,22 @@ void cpu_loop(CPUPPCState *env) break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); + arch_interrupt =3D false; break; default: cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr); break; } process_pending_signals(env); + + /* Most of the traps imply a transition through kernel mode, + * which implies an REI instruction has been executed. Which + * means that RX and LOCK_ADDR should be cleared. But there + * are a few exceptions for traps internal to QEMU. + */ + if (arch_interrupt) { + env->reserve_addr =3D -1; + } } } =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c7b9d226eb..03e8c5df03 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3201,19 +3201,6 @@ ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) #endif =20 -#if defined(CONFIG_USER_ONLY) -static void gen_conditional_store(DisasContext *ctx, TCGv EA, - int reg, int memop) -{ - TCGv t0 =3D tcg_temp_new(); - - tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); - tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg); - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); - tcg_temp_free(t0); - gen_exception_err(ctx, POWERPC_EXCP_STCX, 0); -} -#else static void gen_conditional_store(DisasContext *ctx, TCGv EA, int reg, int memop) { @@ -3244,7 +3231,6 @@ static void gen_conditional_store(DisasContext *ctx, = TCGv EA, gen_set_label(l2); tcg_gen_movi_tl(cpu_reserve, -1); } -#endif =20 #define STCX(name, memop) \ static void gen_##name(DisasContext *ctx) \ --=20 2.17.1 From nobody Tue Feb 10 05:08:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530030850256410.1205441497075; Tue, 26 Jun 2018 09:34:10 -0700 (PDT) Received: from localhost ([::1]:53839 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXquv-0003ka-Fi for importer@patchew.org; Tue, 26 Jun 2018 12:34:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42502) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqgq-0000xh-TC for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXqgo-0005vM-25 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:36 -0400 Received: from mail-pg0-x22b.google.com ([2607:f8b0:400e:c05::22b]:32893) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fXqgn-0005v2-TK for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:34 -0400 Received: by mail-pg0-x22b.google.com with SMTP id e11-v6so7849502pgq.0 for ; Tue, 26 Jun 2018 09:19:33 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id 67-v6sm5054306pfm.171.2018.06.26.09.19.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 09:19:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lH6SYbZrp1nnxM5Q44b5Tfdrejt+qZBPLKp5dGcXBeE=; b=kPh4XGKgOSW+QNnDUjlZbvQMhmo6klxkDtdgr3Otpp2rLeEfO7lpEpriRpfCWlPm28 JL2zM6obpzZO1GuzjLLse6HarP51sN4L0/YIVmfroiX4KMn7512dQeTOj+FfTr0UWV0C qxgB5m9Ynz9STpT2TPTnblD84k37qb8ySlC9c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lH6SYbZrp1nnxM5Q44b5Tfdrejt+qZBPLKp5dGcXBeE=; b=tQeKc8dDzvLz923Id4whd4e4YE8p1iITOMWnQrE8QMrzMqEbjhhMng8uFm4YTOM3Rp x1ijCP8uSnlmL1NZO0d9V6KEQcLjDZL+kCHGS8pvoEeqTL30h1P7S7BcnoM5t6FZGlrN mRSa3QkjFMDOH49J6A1boJlWhUqX7xhe+AwX7EkDyONOKHOj5ckAk3Lz77IremDzG9nw trWRdNR0B/VjWkd0douJVkXIMVK+tDUxGCkhxp4+9NZOjh4xzvplxJkThkFzzarwogIY aDPXQkA6mEX3rmvHAVzQNxl46//6+3n+8aslj7WSyikA8TeS5LO6/jVFGGewQno6+955 2NCg== X-Gm-Message-State: APt69E22mO/EDTY4HjatU5y1qk4FlF9I8Z3lqYZndhuTxq7ookTSBp5X fvlyCfKqO5NG+Izh9kxcoaEEPNO13Bg= X-Google-Smtp-Source: ADUXVKJlEOpiaW1sXFyK5m6/28Olsuucf3QyJFbYDrMK2HcfyHlakCs+bQRfXxJP05+37swdbdXWjw== X-Received: by 2002:a63:ba43:: with SMTP id l3-v6mr1928478pgu.295.1530029972682; Tue, 26 Jun 2018 09:19:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 09:19:14 -0700 Message-Id: <20180626161921.27941-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626161921.27941-1-richard.henderson@linaro.org> References: <20180626161921.27941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22b Subject: [Qemu-devel] [PATCH 06/13] target/ppc: Tidy gen_conditional_store X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Leave only the minimal amount of code within the STCX macro, moving the rest of the code into gen_conditional_store. Remove the explicit call to gen_check_align; the matching LDAX will have already checked alignment, and we verify the same address. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 03e8c5df03..e751072404 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3201,14 +3201,17 @@ ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i3= 2) ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) #endif =20 -static void gen_conditional_store(DisasContext *ctx, TCGv EA, - int reg, int memop) +static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop) { TCGLabel *l1 =3D gen_new_label(); TCGLabel *l2 =3D gen_new_label(); - TCGv t0; + TCGv t0 =3D tcg_temp_new(); + int reg =3D rS(ctx->opcode); =20 - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); + gen_set_access_type(ctx, ACCESS_RES); + gen_addr_reg_index(ctx, t0); + tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); + tcg_temp_free(t0); =20 t0 =3D tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, @@ -3232,19 +3235,10 @@ static void gen_conditional_store(DisasContext *ctx= , TCGv EA, tcg_gen_movi_tl(cpu_reserve, -1); } =20 -#define STCX(name, memop) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv t0; \ - int len =3D MEMOP_GET_SIZE(memop); \ - gen_set_access_type(ctx, ACCESS_RES); \ - t0 =3D tcg_temp_local_new(); \ - gen_addr_reg_index(ctx, t0); \ - if (len > 1) { \ - gen_check_align(ctx, t0, (len) - 1); \ - } \ - gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \ - tcg_temp_free(t0); \ +#define STCX(name, memop) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + gen_conditional_store(ctx, memop); \ } =20 STCX(stbcx_, DEF_MEMOP(MO_UB)) --=20 2.17.1 From nobody Tue Feb 10 05:08:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530030139009263.88789704816475; Tue, 26 Jun 2018 09:22:19 -0700 (PDT) Received: from localhost ([::1]:53760 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqjS-0002aX-9D for importer@patchew.org; Tue, 26 Jun 2018 12:22:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42503) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqgq-0000xi-T1 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXqgp-0005wd-R8 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:36 -0400 Received: from mail-pl0-x22f.google.com ([2607:f8b0:400e:c01::22f]:38636) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fXqgp-0005w4-Kc for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:35 -0400 Received: by mail-pl0-x22f.google.com with SMTP id d10-v6so8792605plo.5 for ; Tue, 26 Jun 2018 09:19:35 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id 67-v6sm5054306pfm.171.2018.06.26.09.19.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 09:19:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uAlbnLmHMOKDyUSFoJ7XopmxrfJEtu2R4neeK2RMIio=; b=gMvYp74Dw0eJsmauoJ512whtdVp5Tewr0AuD7zV57TW9jidUyq104eNyBR/r7cTDEG 6mNCqpJ6JgrCwYhVfOnO7eGScPfC6UwAOJPktFdRchkABYCyYNz3R0491n4bcnHKZW5c t1L6tVJtUcgLoo2dVnikHSZnJRtjMFYuEGhXk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uAlbnLmHMOKDyUSFoJ7XopmxrfJEtu2R4neeK2RMIio=; b=s2dPH3AbFpp3LG4/Vgkw95mHaUSV38RsUtZiOS9k77OGXPfj2vZbPi/OcwkKDF6+OO VNJ5CDf39U2vvN899kelLI+HAjkHLkJsx218gVnr6RhCZpYKSOpt8DxwWAapfOUXIKh3 twqNC364XRRMOM/O5oEEtszdwtUBdTS8+tsoIMQaiXaIOoyLPenrZ06WpV5ZfhIn9vwW xTdWNWnv5j2TT2ZtLN5IgP6TgwcfFFrXzc2/MfoGfhBjVW7sGsguwUSkqVGGBPi7oj1z 6j9/DQDP+g6oxNk2MPfbjgEa/Glowxm3YP/v/phUyH95eGvOYv9WfLgwdTW9DSfe2lEJ 6dCQ== X-Gm-Message-State: APt69E1dpbYMOwzrbmmyze0bEDF5624npewl3IChuQwlQI9XKv/aUoBA R+HkYPOKGr5VYfTYM64XXkwxcdBkwg4= X-Google-Smtp-Source: ADUXVKJrVdrVB3VyM3PmL+lMb9aK90evgvWBoPpyDFAWiTliDBmz8E/Om1+J/+IQBNCLEV2DhZsIcQ== X-Received: by 2002:a17:902:7686:: with SMTP id m6-v6mr2355740pll.340.1530029974437; Tue, 26 Jun 2018 09:19:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 09:19:15 -0700 Message-Id: <20180626161921.27941-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626161921.27941-1-richard.henderson@linaro.org> References: <20180626161921.27941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22f Subject: [Qemu-devel] [PATCH 07/13] target/ppc: Split out gen_load_locked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Leave only the minimal amount of code within the LDAR macro, moving the rest of the code into gen_load_locked. Use MO_ALIGN and remove the explicit call to gen_check_align. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e751072404..f48fcbeefb 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3070,23 +3070,24 @@ static void gen_isync(DisasContext *ctx) =20 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) =20 -#define LARX(name, memop) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv t0; \ - TCGv gpr =3D cpu_gpr[rD(ctx->opcode)]; \ - int len =3D MEMOP_GET_SIZE(memop); \ - gen_set_access_type(ctx, ACCESS_RES); \ - t0 =3D tcg_temp_local_new(); \ - gen_addr_reg_index(ctx, t0); \ - if ((len) > 1) { \ - gen_check_align(ctx, t0, (len)-1); \ - } \ - tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \ - tcg_gen_mov_tl(cpu_reserve, t0); \ - tcg_gen_mov_tl(cpu_reserve_val, gpr); \ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \ - tcg_temp_free(t0); \ +static void gen_load_locked(DisasContext *ctx, TCGMemOp memop) +{ + TCGv gpr =3D cpu_gpr[rD(ctx->opcode)]; + TCGv t0 =3D tcg_temp_new(); + + gen_set_access_type(ctx, ACCESS_RES); + gen_addr_reg_index(ctx, t0); + tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); + tcg_gen_mov_tl(cpu_reserve, t0); + tcg_gen_mov_tl(cpu_reserve_val, gpr); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + tcg_temp_free(t0); +} + +#define LARX(name, memop) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + gen_load_locked(ctx, memop); \ } =20 /* lwarx */ --=20 2.17.1 From nobody Tue Feb 10 05:08:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530030337667419.2414033138359; Tue, 26 Jun 2018 09:25:37 -0700 (PDT) Received: from localhost ([::1]:53780 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqme-0005Bt-NM for importer@patchew.org; Tue, 26 Jun 2018 12:25:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42549) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqgt-0000zz-00 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXqgr-0005xv-Nr for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:38 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:36414) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fXqgr-0005xQ-G0 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:37 -0400 Received: by mail-pf0-x241.google.com with SMTP id u16-v6so4545630pfh.3 for ; Tue, 26 Jun 2018 09:19:37 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id 67-v6sm5054306pfm.171.2018.06.26.09.19.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 09:19:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5hcmVyiOT6a6zB+QxuPp45HBjX7dc7cUIiq5aJ23H4M=; b=T17Jf/zRefPlkmZzS0Z1xwTi+VVZQBtNd5MwhJoZL8ai0NSBM5DLqj9UFm9DZH+tpB R6iJyQqV0foGDs70YmYrp1fBFFCC4CPN0P/rxqGalmnkyKA0AsDeGJFGQXKljRW/FXTl HzEo/DyK4fqM3a8VSVaS79qTSnnps8A19F90o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5hcmVyiOT6a6zB+QxuPp45HBjX7dc7cUIiq5aJ23H4M=; b=IsvZoVJPOiRdDWGNFTYIWClQ37mIhS7T2qo6lGHmwdTZakWECCSPfBWvqvf4ynmWbt zFCThas2edpwLaYoXIlP9EXsD+Mk0aUjjfq8f6PFhFyxznToaNcLzaOqvF+TXj0YZQuz 6mfa2noh3xX0ue4AExt2FD2k+wvR4tYEdQFpUIERvfIBmWxGOkJXQR/7Es/iEhcVv9zA FSN6FkH5HDYXTp8cxjFXJk7gG5p1/Q97LJ2ZDnClSf5vs7zEnRY7VzVvdbNAO5ac29uB VyshiLtEwzbkwyr1Q6VYwlsTLLfz3lMmBdOF5N/59tWqJMX5AVf6KuPEwo7o08t/kG2z RV7Q== X-Gm-Message-State: APt69E0i/yo2hpHmusAfgUj2enq/F+ShJmGQIaEBg/VYu5XaTv6AoaJk wYL+Bbq04SuSoDIHulfLH8RoSi220cY= X-Google-Smtp-Source: AAOMgpedSMo+E7zdXqI0Jbt9qvYmXRPtyyXZtiv6ZvTAFA9zy94IHY5rK611wLjToEMIzhWuVwcOtQ== X-Received: by 2002:a65:490d:: with SMTP id p13-v6mr1948311pgs.84.1530029976271; Tue, 26 Jun 2018 09:19:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 09:19:16 -0700 Message-Id: <20180626161921.27941-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626161921.27941-1-richard.henderson@linaro.org> References: <20180626161921.27941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH 08/13] target/ppc: Split out gen_ld_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move the guts of LD_ATOMIC to a function. Use foo_tl for the operations instead of foo_i32 or foo_i64 specifically. Use MO_ALIGN instead of an explicit call to gen_check_align. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 105 ++++++++++++++++++++--------------------- 1 file changed, 52 insertions(+), 53 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index f48fcbeefb..361b178db8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3095,61 +3095,60 @@ LARX(lbarx, DEF_MEMOP(MO_UB)) LARX(lharx, DEF_MEMOP(MO_UW)) LARX(lwarx, DEF_MEMOP(MO_UL)) =20 -#define LD_ATOMIC(name, memop, tp, op, eop) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - int len =3D MEMOP_GET_SIZE(memop); \ - uint32_t gpr_FC =3D FC(ctx->opcode); \ - TCGv EA =3D tcg_temp_local_new(); \ - TCGv_##tp t0, t1; \ - \ - gen_addr_register(ctx, EA); \ - if (len > 1) { \ - gen_check_align(ctx, EA, len - 1); \ - } \ - t0 =3D tcg_temp_new_##tp(); \ - t1 =3D tcg_temp_new_##tp(); \ - tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ - \ - switch (gpr_FC) { \ - case 0: /* Fetch and add */ \ - tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 1: /* Fetch and xor */ \ - tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 2: /* Fetch and or */ \ - tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 3: /* Fetch and 'and' */ \ - tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 8: /* Swap */ \ - tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 4: /* Fetch and max unsigned */ \ - case 5: /* Fetch and max signed */ \ - case 6: /* Fetch and min unsigned */ \ - case 7: /* Fetch and min signed */ \ - case 16: /* compare and swap not equal */ \ - case 24: /* Fetch and increment bounded */ \ - case 25: /* Fetch and increment equal */ \ - case 28: /* Fetch and decrement bounded */ \ - gen_invalid(ctx); \ - break; \ - default: \ - /* invoke data storage error handler */ \ - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ - } \ - tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \ - tcg_temp_free_##tp(t0); \ - tcg_temp_free_##tp(t1); \ - tcg_temp_free(EA); \ +static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop) +{ + uint32_t gpr_FC =3D FC(ctx->opcode); + TCGv EA =3D tcg_temp_new(); + TCGv src, dst; + + gen_addr_register(ctx, EA); + dst =3D cpu_gpr[rD(ctx->opcode)]; + src =3D cpu_gpr[rD(ctx->opcode) + 1]; + + memop |=3D MO_ALIGN; + switch (gpr_FC) { + case 0: /* Fetch and add */ + tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 1: /* Fetch and xor */ + tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 2: /* Fetch and or */ + tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 3: /* Fetch and 'and' */ + tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 8: /* Swap */ + tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 4: /* Fetch and max unsigned */ + case 5: /* Fetch and max signed */ + case 6: /* Fetch and min unsigned */ + case 7: /* Fetch and min signed */ + case 16: /* compare and swap not equal */ + case 24: /* Fetch and increment bounded */ + case 25: /* Fetch and increment equal */ + case 28: /* Fetch and decrement bounded */ + gen_invalid(ctx); + break; + default: + /* invoke data storage error handler */ + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); + } + tcg_temp_free(EA); } =20 -LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl) -#if defined(TARGET_PPC64) -LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64) +static void gen_lwat(DisasContext *ctx) +{ + gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); +} + +#ifdef TARGET_PPC64 +static void gen_ldat(DisasContext *ctx) +{ + gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); +} #endif =20 #define ST_ATOMIC(name, memop, tp, op) \ --=20 2.17.1 From nobody Tue Feb 10 05:08:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id 67-v6sm5054306pfm.171.2018.06.26.09.19.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 09:19:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tFjnTJLVbY+jJvRfsPNl8toQbXZofsASxxO2hujRJVg=; b=F8BvS2uddGXwL/ewV5hCqD3FEdPquqUoJXROuXhw9I9hj7YMiB7R0yTytxA4Uh+cYI Eiz80ntKkqVpxNkfjo8faeCHu6MfqAoMYOdmLvtIrcUTGnT7JYoGJiCWc0LTRM4u3ODJ Str2AlLJw7mUoPy4DjUImzXFHFIrFES6N2Ahs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tFjnTJLVbY+jJvRfsPNl8toQbXZofsASxxO2hujRJVg=; b=LNt4EjWnkPfv3m32I1P4qES1Sz8l2/Ryci1V/B+Q4WLnsstUfl/UWb0yqnWaW+pcl3 12lsNJyYdin2/ryzaEVi0bG2Lqrn6lNBoF/ZPGo13YCD27MYEjo0o26IZiAIqVVkNgvz HQWRrvxYVCvFOhiQd9akopoaAV5PQYBpzGtMCewP6OCY9ba3EkxFRk48etEkOg6VYjAC hVy8oeTPFbEwq5zdewyd+X//BS3SH0WufTwePEribhIZj1/6mW0WCJdWEUDMUBHgl3Ks fKO6N9YOOrePiXa24gtP4NIa1o8PZYFJAIRMsrlGjoGe95SzBjgaq2jmkbqxu9aZWtWT lzdw== X-Gm-Message-State: APt69E3kUgZ306xGAxzQLZtAuPYKsfcGeulwUhK0gB5XX+IAeSBp57XW Zar2Fc0lD/oaEmb5Pg513ckG20e4UmU= X-Google-Smtp-Source: ADUXVKJhAqF+uN7s9FknntGK6fWD1tn99HCpPDCYGpa48QURgLkfYg04yfZerb0UZUA5ih55GJBTnQ== X-Received: by 2002:a63:686:: with SMTP id 128-v6mr1962095pgg.338.1530029977978; Tue, 26 Jun 2018 09:19:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 09:19:17 -0700 Message-Id: <20180626161921.27941-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626161921.27941-1-richard.henderson@linaro.org> References: <20180626161921.27941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PATCH 09/13] target/ppc: Split out gen_st_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move the guts of ST_ATOMIC to a function. Use foo_tl for the operations instead of foo_i32 or foo_i64 specifically. Use MO_ALIGN instead of an explicit call to gen_check_align. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 93 +++++++++++++++++++++--------------------- 1 file changed, 47 insertions(+), 46 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 361b178db8..53ca8f0114 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3151,54 +3151,55 @@ static void gen_ldat(DisasContext *ctx) } #endif =20 -#define ST_ATOMIC(name, memop, tp, op) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - int len =3D MEMOP_GET_SIZE(memop); \ - uint32_t gpr_FC =3D FC(ctx->opcode); \ - TCGv EA =3D tcg_temp_local_new(); \ - TCGv_##tp t0, t1; \ - \ - gen_addr_register(ctx, EA); \ - if (len > 1) { \ - gen_check_align(ctx, EA, len - 1); \ - } \ - t0 =3D tcg_temp_new_##tp(); \ - t1 =3D tcg_temp_new_##tp(); \ - tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ - \ - switch (gpr_FC) { \ - case 0: /* add and Store */ \ - tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 1: /* xor and Store */ \ - tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 2: /* Or and Store */ \ - tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 3: /* 'and' and Store */ \ - tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 4: /* Store max unsigned */ \ - case 5: /* Store max signed */ \ - case 6: /* Store min unsigned */ \ - case 7: /* Store min signed */ \ - case 24: /* Store twin */ \ - gen_invalid(ctx); \ - break; \ - default: \ - /* invoke data storage error handler */ \ - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ - } \ - tcg_temp_free_##tp(t0); \ - tcg_temp_free_##tp(t1); \ - tcg_temp_free(EA); \ +static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop) +{ + uint32_t gpr_FC =3D FC(ctx->opcode); + TCGv EA =3D tcg_temp_new(); + TCGv src, discard; + + gen_addr_register(ctx, EA); + src =3D cpu_gpr[rD(ctx->opcode)]; + discard =3D tcg_temp_new(); + + memop |=3D MO_ALIGN; + switch (gpr_FC) { + case 0: /* add and Store */ + tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 1: /* xor and Store */ + tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 2: /* Or and Store */ + tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 3: /* 'and' and Store */ + tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 4: /* Store max unsigned */ + case 5: /* Store max signed */ + case 6: /* Store min unsigned */ + case 7: /* Store min signed */ + case 24: /* Store twin */ + gen_invalid(ctx); + break; + default: + /* invoke data storage error handler */ + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); + } + tcg_temp_free(discard); + tcg_temp_free(EA); } =20 -ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) -#if defined(TARGET_PPC64) -ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) +static void gen_stwat(DisasContext *ctx) +{ + gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); +} + +#ifdef TARGET_PPC64 +static void gen_stdat(DisasContext *ctx) +{ + gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); +} #endif =20 static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop) --=20 2.17.1 From nobody Tue Feb 10 05:08:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530030393336591.5995010988296; Tue, 26 Jun 2018 09:26:33 -0700 (PDT) Received: from localhost ([::1]:53791 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqnY-00067g-Ik for importer@patchew.org; Tue, 26 Jun 2018 12:26:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42659) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqh0-00015w-FV for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXqgu-0005zH-PT for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:46 -0400 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:32934) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fXqgu-0005z2-KT for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:40 -0400 Received: by mail-pl0-x242.google.com with SMTP id 6-v6so8787362plb.0 for ; Tue, 26 Jun 2018 09:19:40 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id 67-v6sm5054306pfm.171.2018.06.26.09.19.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 09:19:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ar/LuwcbZ8J5O5K8SZ1WoMJNo3wCEOiOdReZe1rWBa4=; b=EbxOK6oj3qg5ICbxR16KAYkDtA4HqtdvD22tHDOIhkEjcTx3FQLoYTv1m7hwa455LG 0DxwVJdtbXLuROJb/8SuJoQNXSImRc15ingK/iUq6Wto+KCFrMP9b+JRMgFtpbP7GPP5 Xa2jxO2YpOlj4qOKJNV6FWHouhEdEAtuOAdLU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ar/LuwcbZ8J5O5K8SZ1WoMJNo3wCEOiOdReZe1rWBa4=; b=SX668Hpyr+jLjzAznk7FDQ0s90VghsihZQu3TttsIbgORMv7VRxu/gKp8ZVEh5EPqV zKvu663ed2oC6UnDPQt5WkXfU3ufpizX5f60FCHJvagwlWa4N/UdnKq6vJGjaqgRJq56 bz0V6IhQXLjFrOgA29tKTfrguBh8G5u3ssz4xtdThVMXPtErv5mRaJit3URzWYklJalo FLa4EkIPqvFTe4vY8h/i+YR7WBU9ms/vUvIikKx7mkqm8RIFm3rnFUizOpbjP5/O4+0j u82miuAJbEiXRI8kcj0eh+T1VghklHqBrEq1VePe5QSYJjtN2Q1tt4BJ2zn5K+DVz4MI JtTg== X-Gm-Message-State: APt69E27bcNOAcxTMV0aoeyN1yAGmzVTDl7NIvuW0eFUOilFjIEIgC2W 6lr52qxAWD2I0PADBTVEfS5awm4HPn8= X-Google-Smtp-Source: ADUXVKLmW824g7xtqbb1LZol2jEhOAu7EhWDTh5BT7DP/HYw7eGfpzGOoT5weFJ0HNNs2sI2DAXsJA== X-Received: by 2002:a17:902:68:: with SMTP id 95-v6mr2343350pla.178.1530029979530; Tue, 26 Jun 2018 09:19:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 09:19:18 -0700 Message-Id: <20180626161921.27941-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626161921.27941-1-richard.henderson@linaro.org> References: <20180626161921.27941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 10/13] target/ppc: Use MO_ALIGN for EXIWX and ECOWX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This avoids the need for gen_check_align entirely. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 53ca8f0114..c2a28be6d7 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2388,23 +2388,6 @@ static inline void gen_addr_add(DisasContext *ctx, T= CGv ret, TCGv arg1, } } =20 -static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) -{ - TCGLabel *l1 =3D gen_new_label(); - TCGv t0 =3D tcg_temp_new(); - TCGv_i32 t1, t2; - tcg_gen_andi_tl(t0, EA, mask); - tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); - t1 =3D tcg_const_i32(POWERPC_EXCP_ALIGN); - t2 =3D tcg_const_i32(ctx->opcode & 0x03FF0000); - gen_update_nip(ctx, ctx->base.pc_next - 4); - gen_helper_raise_exception_err(cpu_env, t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); - gen_set_label(l1); - tcg_temp_free(t0); -} - static inline void gen_align_no_le(DisasContext *ctx) { gen_exception_err(ctx, POWERPC_EXCP_ALIGN, @@ -4706,8 +4689,8 @@ static void gen_eciwx(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_EXT); t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_check_align(ctx, t0, 0x03); - gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); + tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, + DEF_MEMOP(MO_UL | MO_ALIGN)); tcg_temp_free(t0); } =20 @@ -4719,8 +4702,8 @@ static void gen_ecowx(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_EXT); t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_check_align(ctx, t0, 0x03); - gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); + tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, + DEF_MEMOP(MO_UL | MO_ALIGN)); tcg_temp_free(t0); } =20 --=20 2.17.1 From nobody Tue Feb 10 05:08:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530030506239187.4989579666775; Tue, 26 Jun 2018 09:28:26 -0700 (PDT) Received: from localhost ([::1]:53798 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqpN-0007gH-C6 for importer@patchew.org; Tue, 26 Jun 2018 12:28:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42624) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqgz-00014q-Gp for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXqgw-000606-LW for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:45 -0400 Received: from mail-pl0-x22f.google.com ([2607:f8b0:400e:c01::22f]:42590) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fXqgw-0005zr-Am for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:42 -0400 Received: by mail-pl0-x22f.google.com with SMTP id w17-v6so8772374pll.9 for ; Tue, 26 Jun 2018 09:19:42 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id 67-v6sm5054306pfm.171.2018.06.26.09.19.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 09:19:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UzITA4QAGKPzw7tA/BTTJSlBebGKm5+75IeNPY1PlJc=; b=ARimihTQnkmSSbz31KxonO3+9y9YQadlZwRILz62T5p/jkcyh0BGVNCxjnF5VpHPIJ TA0W+YDmYP9n6UCmfv1Mcq6l5iPXJU1R97gmJ+I0bWegso4vmUpAk9ZoHE93VLrSmkCO XtwH6dfAsvPtbjr6xXOxkXeBDfX+D5qSQbZsQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UzITA4QAGKPzw7tA/BTTJSlBebGKm5+75IeNPY1PlJc=; b=ZxNluWZ7eYEIzw9rcH2w9TyCIlOjxDl/cNNaZtCTVd60N1GlhOqJlxbHniQ6mifCzW xZdkM4Fls87ra/DdVBykClxZhBmdJBX7tPbwIgqhu0n+FWzCIbD/kTzlhiC8BOb2rM9T I+ymNbu9TU2Iax4tiLyHdFmCdHq9bF5hDwZNvbU2QEugrvOVofulq+asz4bTA9HGMAcX PxviEpemCvNpnNy8VK1KO13ADr+QcBZixAFepuNmuilT/ocUIeDV0dRMFpb9nVck/GEf OSVUT/SYbPTtXtDZd2KLIkA8yZ6g3Jpc+/UBm25Mz0feWnnrGjcRP7+jJnMZqJmmp7S8 mGLg== X-Gm-Message-State: APt69E2Rr9sJWTFMzauEE7Esple2XZOC3b1wxEEEf1uClE72KlW78Fq5 aZxGsynV+r7bAbHrNwFstL7ceyqc598= X-Google-Smtp-Source: ADUXVKJmgpYT5As5vfDB88tAimNpKxgbQr+sxgdCbV3jl/u8z+CJg1ABU5eWygvNV8SBUxmGeo+zuw== X-Received: by 2002:a17:902:1703:: with SMTP id i3-v6mr2262881pli.263.1530029981208; Tue, 26 Jun 2018 09:19:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 09:19:19 -0700 Message-Id: <20180626161921.27941-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626161921.27941-1-richard.henderson@linaro.org> References: <20180626161921.27941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22f Subject: [Qemu-devel] [PATCH 11/13] target/ppc: Use atomic min/max helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These operations were previously unimplemented for ppc. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c2a28be6d7..79285b6698 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3102,13 +3102,21 @@ static void gen_ld_atomic(DisasContext *ctx, TCGMem= Op memop) case 3: /* Fetch and 'and' */ tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); break; + case 4: /* Fetch and max unsigned */ + tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 5: /* Fetch and max signed */ + tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 6: /* Fetch and min unsigned */ + tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 7: /* Fetch and min signed */ + tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); + break; case 8: /* Swap */ tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); break; - case 4: /* Fetch and max unsigned */ - case 5: /* Fetch and max signed */ - case 6: /* Fetch and min unsigned */ - case 7: /* Fetch and min signed */ case 16: /* compare and swap not equal */ case 24: /* Fetch and increment bounded */ case 25: /* Fetch and increment equal */ @@ -3159,9 +3167,17 @@ static void gen_st_atomic(DisasContext *ctx, TCGMemO= p memop) tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); break; case 4: /* Store max unsigned */ + tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; case 5: /* Store max signed */ + tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; case 6: /* Store min unsigned */ + tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; case 7: /* Store min signed */ + tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; case 24: /* Store twin */ gen_invalid(ctx); break; --=20 2.17.1 From nobody Tue Feb 10 05:08:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530031136525124.83975668345374; Tue, 26 Jun 2018 09:38:56 -0700 (PDT) Received: from localhost ([::1]:53872 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqzX-0007j1-Nn for importer@patchew.org; Tue, 26 Jun 2018 12:38:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42634) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqgz-00015d-W2 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXqgy-00060o-PR for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:45 -0400 Received: from mail-pl0-x22c.google.com ([2607:f8b0:400e:c01::22c]:33541) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fXqgy-00060U-JZ for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:44 -0400 Received: by mail-pl0-x22c.google.com with SMTP id 6-v6so8787447plb.0 for ; Tue, 26 Jun 2018 09:19:44 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id 67-v6sm5054306pfm.171.2018.06.26.09.19.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 09:19:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vCbWV12C7Rm1WDLGSl608zFQKJGXdryQ+O/Dxik0j8Q=; b=NJqX5kFw8zW25KakevCG+/boqhd0uj+NT7Cj8X7FgP6eI5OHYXJIGv71/AT6loqafy VRPEHmL8BTsncocJj8KRHXYzJjfotAXIjdgqYAsSdgLhqDGwC2Z6aprxpakvPYVXKq+7 uZofry0Kb96i6J+MlJMNUCCMHle0qAnglGUgE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vCbWV12C7Rm1WDLGSl608zFQKJGXdryQ+O/Dxik0j8Q=; b=Y4BZGNm2pbSOdzsdZe4smUvwE5IAi6+3/GKhRS7MX1znfg1vezVvrMTRxowAoZrefI zygf1vwJFV91WHS5rprSV1O1acEjrx206UzTBJbQrmYVZxseNnanI/0ZJz9PhEGaknNh FDZ/c1gCpMI5yp1VdlgUMhlRqo6JpbUhbLp1+TeHc6IP9ioGAhBrUI8nuwwMNJBR5LsJ OgKXvjmudCaWTssrilrLt1k1tYTHBiG3WQ3WLlzimIdN8p6P6TootMl/3NcfFnpEjvA5 HXDjPOqGyf8gD5VWEf9bgjmhHGvrZlZ65urq5RlOrrIp8WvhkEYGzD0ANQYya25aeosL KyQA== X-Gm-Message-State: APt69E2B/gTg8wgrU/Dg9aUn2/U4zbyes+bbeFSTgeRUhl5sSqrAr3fG YCpoB5vdBrHv5YcRV0ll5LMBDt7GVyM= X-Google-Smtp-Source: ADUXVKIH3ou+xm8aNMx93GB+zwJfVSLMBwZa6bSI3MQ5uajp73e/rjo2+xhPVWeihQRJLElSB576GQ== X-Received: by 2002:a17:902:8a81:: with SMTP id p1-v6mr2266879plo.33.1530029983236; Tue, 26 Jun 2018 09:19:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 09:19:20 -0700 Message-Id: <20180626161921.27941-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626161921.27941-1-richard.henderson@linaro.org> References: <20180626161921.27941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22c Subject: [Qemu-devel] [PATCH 12/13] target/ppc: Implement the rest of gen_ld_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These cases were stubbed out. For now, implement them only within a serial context, forcing parallel execution to synchronize. It would be possible to implement these with cmpxchg loops, if we care. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 89 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 82 insertions(+), 7 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 79285b6698..597a37d3ec 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3078,16 +3078,45 @@ LARX(lbarx, DEF_MEMOP(MO_UB)) LARX(lharx, DEF_MEMOP(MO_UW)) LARX(lwarx, DEF_MEMOP(MO_UL)) =20 +static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop, + TCGv EA, TCGCond cond, int addend) +{ + TCGv t =3D tcg_temp_new(); + TCGv t2 =3D tcg_temp_new(); + TCGv u =3D tcg_temp_new(); + + tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); + tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); + tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); + tcg_gen_addi_tl(u, t, addend); + + /* E.g. for fetch and increment bounded... */ + /* mem(EA,s) =3D (t !=3D t2 ? u =3D t + 1 : t) */ + tcg_gen_movcond_tl(cond, u, t, t2, u, t); + tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); + + /* RT =3D (t !=3D t2 ? t : u =3D 1<<(s*8-1)) */ + tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); + tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); + + tcg_temp_free(t); + tcg_temp_free(t2); + tcg_temp_free(u); +} + static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop) { uint32_t gpr_FC =3D FC(ctx->opcode); TCGv EA =3D tcg_temp_new(); + int rt =3D rD(ctx->opcode); + bool need_serial; TCGv src, dst; =20 gen_addr_register(ctx, EA); - dst =3D cpu_gpr[rD(ctx->opcode)]; - src =3D cpu_gpr[rD(ctx->opcode) + 1]; + dst =3D cpu_gpr[rt]; + src =3D cpu_gpr[(rt + 1) & 31]; =20 + need_serial =3D false; memop |=3D MO_ALIGN; switch (gpr_FC) { case 0: /* Fetch and add */ @@ -3117,17 +3146,63 @@ static void gen_ld_atomic(DisasContext *ctx, TCGMem= Op memop) case 8: /* Swap */ tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); break; - case 16: /* compare and swap not equal */ - case 24: /* Fetch and increment bounded */ - case 25: /* Fetch and increment equal */ - case 28: /* Fetch and decrement bounded */ - gen_invalid(ctx); + + case 16: /* Compare and swap not equal */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); + if ((memop & MO_SIZE) =3D=3D MO_64 || TARGET_LONG_BITS =3D=3D = 32) { + tcg_gen_mov_tl(t1, src); + } else { + tcg_gen_ext32u_tl(t1, src); + } + tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, + cpu_gpr[(rt + 2) & 31], t0); + tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); + tcg_gen_mov_tl(dst, t0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + } break; + + case 24: /* Fetch and increment bounded */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); + } + break; + case 25: /* Fetch and increment equal */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); + } + break; + case 28: /* Fetch and decrement bounded */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); + } + break; + default: /* invoke data storage error handler */ gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); } tcg_temp_free(EA); + + if (need_serial) { + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + } } =20 static void gen_lwat(DisasContext *ctx) --=20 2.17.1 From nobody Tue Feb 10 05:08:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530030572687212.66912937337918; Tue, 26 Jun 2018 09:29:32 -0700 (PDT) Received: from localhost ([::1]:53803 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqqJ-0008Ra-MA for importer@patchew.org; Tue, 26 Jun 2018 12:29:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42683) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXqh1-00016u-5K for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXqh0-00061w-3q for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:47 -0400 Received: from mail-pl0-x22d.google.com ([2607:f8b0:400e:c01::22d]:38635) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fXqgz-00061M-T0 for qemu-devel@nongnu.org; Tue, 26 Jun 2018 12:19:46 -0400 Received: by mail-pl0-x22d.google.com with SMTP id d10-v6so8792861plo.5 for ; Tue, 26 Jun 2018 09:19:45 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id 67-v6sm5054306pfm.171.2018.06.26.09.19.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 09:19:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eHy18mSxSfmi7Mu0ivgDQ36YgURhjOjHU9AXE2YyG6M=; b=jFmJXqt1LmTa2UjUk4Q80b2OdQjfG9hDcu5zQnHZUXV7SfMT4657ABJPqkz9EYO6lW 6hwoGqc/EId1rjJYJDx6Y15DHWS/tNZ9A0c9FN/l0B/dWtw+478ZHO32FisjtPlT7/uq foB3iM0bBCfSYb7JZodb0e9GJcUvn97UZeiHk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eHy18mSxSfmi7Mu0ivgDQ36YgURhjOjHU9AXE2YyG6M=; b=t/YT71hh7AIDZN8oGFn0iX4e2T9oKw5d4xDZkBoN8punyGZqgpSigNYzOBpTHY1e8K hyg87hCYp21qxe9l9HU501Fs3yuNB4GgKS5j6YmjAYoK/U+51PxJu79PWBJ5DjIQXKCn NeFsdfit0tyHjdca6Bju6nopTOS/hfyNU4vu2FclkwtlWgSeOKc4rufVFdSNubcL7vwA vRzP59sR+CODaim57+e8+Zg12Q+CUOGcSrgoFjZPhtn5WKGdnVYNII0RY4EnENF3XDdw 0rFbIMDp+JBburtDndMH1Jrtykayelco7949cdTxAFo8sYY7+1eXssjsEnJ2lQ8h72Js 5Reg== X-Gm-Message-State: APt69E0tnmhn2zzdfWIJHyngZOjvcBBpsr+66slUrxpcMGtSvL3MbDpV P0YmUMKS2qjHbRT7+DoIyp6qIxW6QOo= X-Google-Smtp-Source: ADUXVKJu6TPG/bXZkMyfTbQ6adHCegXMDVy3S+CPnJJ07x/M3Ex2ZFOGqNhhMm5q1FhOaos3UIkmWQ== X-Received: by 2002:a17:902:6b86:: with SMTP id p6-v6mr2338869plk.75.1530029984775; Tue, 26 Jun 2018 09:19:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 26 Jun 2018 09:19:21 -0700 Message-Id: <20180626161921.27941-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626161921.27941-1-richard.henderson@linaro.org> References: <20180626161921.27941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22d Subject: [Qemu-devel] [PATCH 13/13] target/ppc: Implement the rest of gen_st_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The store twin case was stubbed out. For now, implement it only within a serial context, forcing parallel execution to synchronize. It would be possible to implement with a cmpxchg loop, if we care, but the loose alignment requirements (simply no crossing 32-byte boundary) might send us back to the serial context anyway. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 597a37d3ec..e120f2ed0b 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3254,7 +3254,31 @@ static void gen_st_atomic(DisasContext *ctx, TCGMemO= p memop) tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); break; case 24: /* Store twin */ - gen_invalid(ctx); + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + } else { + TCGv t =3D tcg_temp_new(); + TCGv t2 =3D tcg_temp_new(); + TCGv s =3D tcg_temp_new(); + TCGv s2 =3D tcg_temp_new(); + TCGv ea_plus_s =3D tcg_temp_new(); + + tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); + tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); + tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); + tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); + tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); + tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); + tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); + + tcg_temp_free(ea_plus_s); + tcg_temp_free(s2); + tcg_temp_free(s); + tcg_temp_free(t2); + tcg_temp_free(t); + } break; default: /* invoke data storage error handler */ --=20 2.17.1