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X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v3 3/5] target/arm: expose CPUID registers to userspace X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 A number of CPUID registers are exposed to userspace by modern Linux kernels thanks to the "ARM64 CPU Feature Registers" ABI. For CONFIG_USER_ONLY we don't emulate the kernels trap and emulate but instead just lower the read permission to PL0_R (hidden behind the PL1U_R macro). The ID_AA64PFR0_EL1 is a little special as the GIC version is hidden from userspace so we can define a ARM_CP_CONST version of the register for usermode. Signed-off-by: Alex Benn=C3=A9e squash! target/arm: expose CPUID registers to userspace --- target/arm/cpu.h | 7 +++++++ target/arm/helper.c | 39 +++++++++++++++++++++++++-------------- 2 files changed, 32 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a4507a2d6f..156c811654 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1924,6 +1924,13 @@ static inline bool cptype_valid(int cptype) #define PL0_R (0x02 | PL1_R) #define PL0_W (0x01 | PL1_W) =20 +/* for AArch64 HWCAP_CPUID to userspace */ +#ifdef CONFIG_USER_ONLY +#define PL1U_R PL0_R +#else +#define PL1U_R PL1_R +#endif + #define PL3_RW (PL3_R | PL3_W) #define PL2_RW (PL2_R | PL2_W) #define PL1_RW (PL1_R | PL1_W) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9d81feb124..1ea0dc4593 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2987,7 +2987,7 @@ static uint64_t mpidr_read(CPUARMState *env, const AR= MCPRegInfo *ri) static const ARMCPRegInfo mpidr_cp_reginfo[] =3D { { .name =3D "MPIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 5, - .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_NO_RAW }, + .access =3D PL1U_R, .readfn =3D mpidr_read, .type =3D ARM_CP_NO_RAW = }, REGINFO_SENTINEL }; =20 @@ -4776,6 +4776,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const = ARMCPRegInfo *ri) return pfr1; } =20 +#ifndef CONFIG_USER_ONLY static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu =3D arm_env_get_cpu(env); @@ -4786,6 +4787,7 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, co= nst ARMCPRegInfo *ri) } return pfr0; } +#endif =20 void register_cp_regs_for_features(ARMCPU *cpu) { @@ -4934,18 +4936,26 @@ void register_cp_regs_for_features(ARMCPU *cpu) * define new registers here. */ ARMCPRegInfo v8_idregs[] =3D { - /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't - * know the right value for the GIC field until after we - * define these regs. + /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST for system + * emulation because we don't know the right value for the + * GIC field until after we define these regs. For + * user-mode HWCAP_CPUID emulation the gic bits are masked + * anyway. */ { .name =3D "ID_AA64PFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 0, +#ifndef CONFIG_USER_ONLY .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .readfn =3D id_aa64pfr0_read, - .writefn =3D arm_cp_write_ignore }, + .writefn =3D arm_cp_write_ignore +#else + .access =3D PL0_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_aa64pfr0 +#endif + }, { .name =3D "ID_AA64PFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL1U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->id_aa64pfr1}, { .name =3D "ID_AA64PFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 2, @@ -4973,11 +4983,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D 0 }, { .name =3D "ID_AA64DFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL1U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->id_aa64dfr0 }, { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL1U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->id_aa64dfr1 }, { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, @@ -5005,11 +5015,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D 0 }, { .name =3D "ID_AA64ISAR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL1U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->id_aa64isar0 }, { .name =3D "ID_AA64ISAR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL1U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->id_aa64isar1 }, { .name =3D "ID_AA64ISAR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 2, @@ -5037,11 +5047,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D 0 }, { .name =3D "ID_AA64MMFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL1U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->id_aa64mmfr0 }, { .name =3D "ID_AA64MMFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL1U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->id_aa64mmfr1 }, { .name =3D "ID_AA64MMFR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, @@ -5335,7 +5345,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo id_v8_midr_cp_reginfo[] =3D { { .name =3D "MIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D = cpu->midr, + .access =3D PL1U_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D= cpu->midr, .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), .readfn =3D midr_read }, /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 4,7 : AArch32 aliases= of MIDR */ @@ -5347,7 +5357,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .resetvalue =3D cpu->midr }, { .name =3D "REVIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D c= pu->revidr }, + .access =3D PL1U_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->revidr }, REGINFO_SENTINEL }; ARMCPRegInfo id_cp_reginfo[] =3D { --=20 2.17.1