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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [RISU PATCH v4 21/22] risu_reginfo_aarch64: limit SVE_VQ_MAX to current architecture X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Richard Henderson The kernel headers optimistically assume it's going to grow but as we are never going to use that many on current hardware we limit SVE_VQ_MAX to what we will. Signed-off-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- risu_reginfo_aarch64.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/risu_reginfo_aarch64.h b/risu_reginfo_aarch64.h index b3701b3..c33b86f 100644 --- a/risu_reginfo_aarch64.h +++ b/risu_reginfo_aarch64.h @@ -31,6 +31,11 @@ struct sve_reginfo { }; #endif =20 +/* The kernel headers set this based on future arch extensions. + The current arch maximum is 16. Save space below. */ +#undef SVE_VQ_MAX +#define SVE_VQ_MAX 16 + struct reginfo { uint64_t fault_address; uint64_t regs[31]; --=20 2.17.1