From nobody Mon Feb 9 09:35:34 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529678572794523.6595101449391; Fri, 22 Jun 2018 07:42:52 -0700 (PDT) Received: from localhost ([::1]:34483 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWNGx-00068b-9Y for importer@patchew.org; Fri, 22 Jun 2018 10:42:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41824) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWMwy-0005wD-Gn for qemu-devel@nongnu.org; Fri, 22 Jun 2018 10:22:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWMww-0003YS-V3 for qemu-devel@nongnu.org; Fri, 22 Jun 2018 10:22:08 -0400 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:54514) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fWMww-0003XS-KQ for qemu-devel@nongnu.org; Fri, 22 Jun 2018 10:22:06 -0400 Received: by mail-wm0-x244.google.com with SMTP id o13-v6so2421348wmf.4 for ; Fri, 22 Jun 2018 07:22:06 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id n16-v6sm2022714wrq.43.2018.06.22.07.22.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Jun 2018 07:22:04 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 4103E3E0C98; Fri, 22 Jun 2018 15:12:06 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mWP40Stc1rcVLV+euOPJVniIvKfcUEsxA1LKizFB7t4=; b=M+0AoNUz42eJ5KLm0HLfWzlDB0m+qpF+1TabXLaYvc5Vnu1WsDCiDqBkHAHkJRypqZ xCW7sAiZRT2iBu3HAPGv5TaQDFNNEOC7ud0sO8ZosjJOaEOa9bV3ugJrefGxNx038i5/ gBfLaBB1strQr/DPCu0wqG3pia7hmM2VCQTG8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mWP40Stc1rcVLV+euOPJVniIvKfcUEsxA1LKizFB7t4=; b=mFGCfOMRrmZ0BAE2eODdpNJUrtStBs11qIikUzZx7JGkFO9KD/l4d3l7b5sT9UWh9H 7CFvv3d9+CG9wqnFV+J1/ORS4k/mDypT2F3DW8tm7+CN9dAk3BdLO3k8P5s8vxNgHQ1F 4pStR6zprZ9ciTINbFyA9GH9aagmzSiheLVFXr8AJqCvSyfe+ptYrACpZ5PlGcuc0PzA HIv2E89sYKFbwBTt0Rm+TI43DEKbNmiUqXJSq6XgN0evFmCx5PD0xjwnGPvJBov/qpmW kzZCMrWW/pKLM6KdWtDL4ERX848nH7H0brNQHXpv+nbEb4bepIa30wOrf4oOTs+DtfKN 3QHg== X-Gm-Message-State: APt69E2tU/tr6BIhjUr3EPjMTrTUDwENUYipkARjY5si7s9l/zcJsld5 gS/VtgyFV1WtE/ae4Wq7SdvbpQ== X-Google-Smtp-Source: ADUXVKKH9sN8cPS6adbitZDiYNH58mvNQ9zXZWTLqYYPzNMSPRc4J+Q4ck7Y9hUJljlKXdtkY0YdJA== X-Received: by 2002:a1c:3fd1:: with SMTP id m200-v6mr2032714wma.88.1529677325477; Fri, 22 Jun 2018 07:22:05 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Fri, 22 Jun 2018 15:12:02 +0100 Message-Id: <20180622141205.16306-20-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180622141205.16306-1-alex.bennee@linaro.org> References: <20180622141205.16306-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [RISU PATCH v4 19/22] risu_reginfo_aarch64: add support for copying SVE register state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Add the ability to save SVE registers from the signal context. This is controlled with an optional flag --test-sve. The whole thing is conditionally compiled when SVE support is in the sigcontext headers. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - support EXTRA_MAGIC contexts v3 - handle conditional bits - include in reginfo.h - move from helper function to main init function - (void *) cast for memcpy - additional ifdef SVE_MAGIC stuff --- risu_reginfo_aarch64.c | 107 ++++++++++++++++++++++++++++++++++++----- risu_reginfo_aarch64.h | 16 ++++++ 2 files changed, 110 insertions(+), 13 deletions(-) diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index 3ccaf0e..79db5dd 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -16,13 +16,26 @@ #include /* for FPSIMD_MAGIC */ #include #include -#include +#include =20 #include "risu.h" #include "risu_reginfo_aarch64.h" =20 +#ifndef SVE_MAGIC const struct option * const arch_long_opts; const char * const arch_extra_help; +#else + +/* Should we test SVE register state */ +static int test_sve; +static const struct option extra_opts[] =3D { + {"test-sve", no_argument, &test_sve, 1}, + {0, 0, 0, 0} +}; + +const struct option * const arch_long_opts =3D &extra_opts[0]; +const char * const arch_extra_help =3D " --test-sve Compare SVE re= gisters\n"; +#endif =20 void process_arch_opt(int opt, const char *arg) { @@ -31,8 +44,12 @@ void process_arch_opt(int opt, const char *arg) =20 const int reginfo_size(void) { - const int size =3D offsetof(struct reginfo, simd.end); - assert(sizeof(struct reginfo)=3D=3Dsize); + int size =3D offsetof(struct reginfo, simd.end); +#ifdef SVE_MAGIC + if (test_sve) { + size =3D offsetof(struct reginfo, sve.end); + } +#endif return size; } =20 @@ -40,8 +57,12 @@ const int reginfo_size(void) void reginfo_init(struct reginfo *ri, ucontext_t *uc) { int i; - struct _aarch64_ctx *ctx; - struct fpsimd_context *fp; + struct _aarch64_ctx *ctx, *extra =3D NULL; + struct fpsimd_context *fp =3D NULL; +#ifdef SVE_MAGIC + struct sve_context *sve =3D NULL; +#endif + /* necessary to be able to compare with memcmp later */ memset(ri, 0, sizeof(*ri)); =20 @@ -57,21 +78,81 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) ri->faulting_insn =3D *((uint32_t *) uc->uc_mcontext.pc); =20 ctx =3D (struct _aarch64_ctx *) &uc->uc_mcontext.__reserved[0]; - - while (ctx->magic !=3D FPSIMD_MAGIC && ctx->size !=3D 0) { - ctx +=3D (ctx->size + sizeof(*ctx) - 1) / sizeof(*ctx); + while (ctx) { + switch (ctx->magic) { + case FPSIMD_MAGIC: + fp =3D (void *)ctx; + break; +#ifdef SVE_MAGIC + case SVE_MAGIC: + sve =3D (void *)ctx; + break; + case EXTRA_MAGIC: + extra =3D (void *)((struct extra_context *)(ctx))->datap; + break; +#endif + case 0: + /* End of list. */ + ctx =3D extra; + extra =3D NULL; + continue; + default: + /* Unknown record -- skip it. */ + break; + } + ctx =3D (void *)ctx + ctx->size; } =20 - if (ctx->magic !=3D FPSIMD_MAGIC || ctx->size !=3D sizeof(*fp)) { - fprintf(stderr, - "risu_reginfo_aarch64: failed to get FP/SIMD state\n"); + if (!fp || fp->head.size !=3D sizeof(*fp)) { + fprintf(stderr, "risu_reginfo_aarch64: failed to get FP/SIMD state= \n"); return; } - - fp =3D (struct fpsimd_context *) ctx; ri->fpsr =3D fp->fpsr; ri->fpcr =3D fp->fpcr; =20 +#ifdef SVE_MAGIC + if (test_sve) { + int vq =3D sve_vq_from_vl(sve->vl); /* number of quads for whole v= l */ + + if (sve =3D=3D NULL) { + fprintf(stderr, "risu_reginfo_aarch64: failed to get SVE state= \n"); + return; + } + + ri->sve.vl =3D sve->vl; + + if (sve->head.size < SVE_SIG_CONTEXT_SIZE(vq)) { + if (sve->head.size =3D=3D sizeof(*sve)) { + /* SVE state is empty -- not an error. */ + } else { + fprintf(stderr, "risu_reginfo_aarch64: " + "failed to get complete SVE state\n"); + } + return; + } + + /* Copy ZREG's one at a time */ + for (i =3D 0; i < SVE_NUM_ZREGS; i++) { + memcpy(&ri->sve.zregs[i], + (void *)sve + SVE_SIG_ZREG_OFFSET(vq, i), + SVE_SIG_ZREG_SIZE(vq)); + } + + /* Copy PREG's one at a time */ + for (i =3D 0; i < SVE_NUM_PREGS; i++) { + memcpy(&ri->sve.pregs[i], + (void *)sve + SVE_SIG_PREG_OFFSET(vq, i), + SVE_SIG_PREG_SIZE(vq)); + } + + /* Finally the FFR */ + memcpy(&ri->sve.ffr,(void *)sve + SVE_SIG_FFR_OFFSET(vq), + SVE_SIG_FFR_SIZE(vq)); + + return; + } +#endif + for (i =3D 0; i < 32; i++) { ri->simd.vregs[i] =3D fp->vregs[i]; } diff --git a/risu_reginfo_aarch64.h b/risu_reginfo_aarch64.h index ef97622..b3701b3 100644 --- a/risu_reginfo_aarch64.h +++ b/risu_reginfo_aarch64.h @@ -13,11 +13,24 @@ #ifndef RISU_REGINFO_AARCH64_H #define RISU_REGINFO_AARCH64_H =20 +#include /* for SVE_MAGIC */ + struct simd_reginfo { __uint128_t vregs[32]; char end[0]; }; =20 +#ifdef SVE_MAGIC +struct sve_reginfo { + /* SVE */ + uint16_t vl; /* current VL */ + __uint128_t zregs[SVE_NUM_ZREGS][SVE_VQ_MAX]; + uint16_t pregs[SVE_NUM_PREGS][SVE_VQ_MAX]; + uint16_t ffr[SVE_VQ_MAX]; + char end[0]; +}; +#endif + struct reginfo { uint64_t fault_address; uint64_t regs[31]; @@ -32,6 +45,9 @@ struct reginfo { =20 union { struct simd_reginfo simd; +#ifdef SVE_MAGIC + struct sve_reginfo sve; +#endif }; }; =20 --=20 2.17.1