From nobody Tue Feb 10 10:59:08 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529665293381680.9509501763704; Fri, 22 Jun 2018 04:01:33 -0700 (PDT) Received: from localhost ([::1]:60827 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWJom-0005Aj-OR for importer@patchew.org; Fri, 22 Jun 2018 07:01:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45918) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWJPz-0000o9-JL for qemu-devel@nongnu.org; Fri, 22 Jun 2018 06:35:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWJPw-0003WY-GY for qemu-devel@nongnu.org; Fri, 22 Jun 2018 06:35:51 -0400 Received: from ozlabs.org ([203.11.71.1]:59847) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWJPv-0003Ts-Nz; Fri, 22 Jun 2018 06:35:48 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41Bw2K1VBtz9sBW; Fri, 22 Jun 2018 20:35:35 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1529663737; bh=3yGzj1my1DmrKY+VP1SfWC8fZuvEwWj1G6YqBzycQbY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ncigAUeMthW6T6sbMBuMOyyLowMIc+a7GNfPFzHoaXkK6+p4vR84OGajSBmsZdfqR 38F8e/NjsfPwtWq96va+eI5eXJGoZQ8FaNgKmb1T33StOfDim4ykUzZZdxyfVQKMBY N6pVacRObzZA56HnFxCh8WcjDnvWq4mvRp0DXekk= From: David Gibson To: peter.maydell@linaro.org Date: Fri, 22 Jun 2018 20:35:24 +1000 Message-Id: <20180622103528.28598-22-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180622103528.28598-1-david@gibson.dropbear.id.au> References: <20180622103528.28598-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 21/25] target/ppc: Add ppc_hash64_filter_pagesizes() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, agraf@suse.de, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The paravirtualized PAPR platform sometimes needs to restrict the guest to using only some of the page sizes actually supported by the host's MMU. At the moment this is handled in KVM specific code, but for consistency we want to apply the same limitations to all accelerators. This makes a start on this by providing a helper function in the cpu code to allow platform code to remove some of the cpu's page size definitions via a caller supplied callback. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- target/ppc/mmu-hash64.c | 59 +++++++++++++++++++++++++++++++++++++++++ target/ppc/mmu-hash64.h | 3 +++ 2 files changed, 62 insertions(+) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index aa200cba4c..276d9015e7 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1166,3 +1166,62 @@ const PPCHash64Options ppc_hash64_opts_POWER7 =3D { }, } }; + +void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu, + bool (*cb)(void *, uint32_t, uint32_t), + void *opaque) +{ + PPCHash64Options *opts =3D cpu->hash64_opts; + int i; + int n =3D 0; + bool ci_largepage =3D false; + + assert(opts); + + n =3D 0; + for (i =3D 0; i < ARRAY_SIZE(opts->sps); i++) { + PPCHash64SegmentPageSizes *sps =3D &opts->sps[i]; + int j; + int m =3D 0; + + assert(n <=3D i); + + if (!sps->page_shift) { + break; + } + + for (j =3D 0; j < ARRAY_SIZE(sps->enc); j++) { + PPCHash64PageSize *ps =3D &sps->enc[j]; + + assert(m <=3D j); + if (!ps->page_shift) { + break; + } + + if (cb(opaque, sps->page_shift, ps->page_shift)) { + if (ps->page_shift >=3D 16) { + ci_largepage =3D true; + } + sps->enc[m++] =3D *ps; + } + } + + /* Clear rest of the row */ + for (j =3D m; j < ARRAY_SIZE(sps->enc); j++) { + memset(&sps->enc[j], 0, sizeof(sps->enc[j])); + } + + if (m) { + n++; + } + } + + /* Clear the rest of the table */ + for (i =3D n; i < ARRAY_SIZE(opts->sps); i++) { + memset(&opts->sps[i], 0, sizeof(opts->sps[i])); + } + + if (!ci_largepage) { + opts->flags &=3D ~PPC_HASH64_CI_LARGEPAGE; + } +} diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 53dcec5b93..f11efc9cbc 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -20,6 +20,9 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val); void ppc_hash64_init(PowerPCCPU *cpu); void ppc_hash64_finalize(PowerPCCPU *cpu); +void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu, + bool (*cb)(void *, uint32_t, uint32_t), + void *opaque); #endif =20 /* --=20 2.17.1