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[98.147.121.51]) by smtp.gmail.com with ESMTPSA id a27-v6sm6187946pfc.18.2018.06.20.18.54.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Jun 2018 18:55:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=knsSl75J+cMYx24an5DGn279NUCI/wNVkLxKUvInCr0=; b=GO4WWikdwc74BHSAljIwlBGSvTkcetCiWOnbzCpa773a3vk+fsoO/MuyA0SOnKRETq mIWA17Tqhb9tTWt/IKfS4qUCO6IvGjMFJ1/hvFPECg/FKX9vMsLKvxRkkwq9MA+jmJPe ra3wvMhmC7Zim2aukV5tJpXOEyFIaSOVpF2l8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=knsSl75J+cMYx24an5DGn279NUCI/wNVkLxKUvInCr0=; b=WuxLD1iRrzGOLGguuoB/fJoNzzAv/EApF2+JICyKW2XVfLTl0Zsz0EusKJXJ2j5B4C 2e+YTjYmTLgyl5MKkknKbsvv0IfzLN3sgiuAsvaAPEEuN7wlcNJROgX4jidN3D17znqq cqpRe1Ds+IK4OLADZZu9HXbG2SrWN7TYy61g338ugdh3DiVj8XJP82XlvPCA2TbPiex6 tSLR9pQmvIGOJoC7HYB5eoJpUP/5G/RaLzQJ1EKr26RE+nnFOLODK3Mmhs9T0OiQLzwQ lKPQ+0jXi6iskiohLdlrEEpfoygxXxKqtSyk9utZrJk/UPj8DMYe2odQVrAbTOqiBBSL iNZw== X-Gm-Message-State: APt69E0OAvii7n8KkPt6nmEOKVM/shsHIRI6A6oEJNG9W1NqcCgMrvvI OkCjwMXrAmad4/FGVkin7GqhxuMWEHY= X-Google-Smtp-Source: ADUXVKJy4edaPKnJq4eEKTIKm1XCt1AIn2lMlAFke3rh4Xom97EhkIxTIihz9eN3aOQBwuMkbdD6vQ== X-Received: by 2002:aa7:83d1:: with SMTP id j17-v6mr25500360pfn.236.1529546100920; Wed, 20 Jun 2018 18:55:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 20 Jun 2018 15:53:53 -1000 Message-Id: <20180621015359.12018-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180621015359.12018-1-richard.henderson@linaro.org> References: <20180621015359.12018-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v5 29/35] target/arm: Implement SVE fp complex multiply add X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 4 + target/arm/sve_helper.c | 162 +++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 37 +++++++++ target/arm/sve.decode | 4 + 4 files changed, 207 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 0bd9fe2f28..023952a9a4 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -1115,6 +1115,10 @@ DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_h, TCG_CALL_NO_RW= G, void, env, ptr, i32) DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32) =20 +DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32) + DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(sve_ftmad_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index ee7fc23bb9..cd3dfc8b26 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -3729,6 +3729,168 @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *= vm, void *vg, } while (i !=3D 0); } =20 +/* + * FP Complex Multiply + */ + +QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 22 > 32); + +void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc) +{ + intptr_t j, i =3D simd_oprsz(desc); + unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT, 5); + unsigned rn =3D extract32(desc, SIMD_DATA_SHIFT + 5, 5); + unsigned rm =3D extract32(desc, SIMD_DATA_SHIFT + 10, 5); + unsigned ra =3D extract32(desc, SIMD_DATA_SHIFT + 15, 5); + unsigned rot =3D extract32(desc, SIMD_DATA_SHIFT + 20, 2); + bool flip =3D rot & 1; + float16 neg_imag, neg_real; + void *vd =3D &env->vfp.zregs[rd]; + void *vn =3D &env->vfp.zregs[rn]; + void *vm =3D &env->vfp.zregs[rm]; + void *va =3D &env->vfp.zregs[ra]; + uint64_t *g =3D vg; + + neg_imag =3D float16_set_sign(0, (rot & 2) !=3D 0); + neg_real =3D float16_set_sign(0, rot =3D=3D 1 || rot =3D=3D 2); + + do { + uint64_t pg =3D g[(i - 1) >> 6]; + do { + float16 e1, e2, e3, e4, nr, ni, mr, mi, d; + + /* I holds the real index; J holds the imag index. */ + j =3D i - sizeof(float16); + i -=3D 2 * sizeof(float16); + + nr =3D *(float16 *)(vn + H1_2(i)); + ni =3D *(float16 *)(vn + H1_2(j)); + mr =3D *(float16 *)(vm + H1_2(i)); + mi =3D *(float16 *)(vm + H1_2(j)); + + e2 =3D (flip ? ni : nr); + e1 =3D (flip ? mi : mr) ^ neg_real; + e4 =3D e2; + e3 =3D (flip ? mr : mi) ^ neg_imag; + + if (likely((pg >> (i & 63)) & 1)) { + d =3D *(float16 *)(va + H1_2(i)); + d =3D float16_muladd(e2, e1, d, 0, &env->vfp.fp_status_f16= ); + *(float16 *)(vd + H1_2(i)) =3D d; + } + if (likely((pg >> (j & 63)) & 1)) { + d =3D *(float16 *)(va + H1_2(j)); + d =3D float16_muladd(e4, e3, d, 0, &env->vfp.fp_status_f16= ); + *(float16 *)(vd + H1_2(j)) =3D d; + } + } while (i & 63); + } while (i !=3D 0); +} + +void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc) +{ + intptr_t j, i =3D simd_oprsz(desc); + unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT, 5); + unsigned rn =3D extract32(desc, SIMD_DATA_SHIFT + 5, 5); + unsigned rm =3D extract32(desc, SIMD_DATA_SHIFT + 10, 5); + unsigned ra =3D extract32(desc, SIMD_DATA_SHIFT + 15, 5); + unsigned rot =3D extract32(desc, SIMD_DATA_SHIFT + 20, 2); + bool flip =3D rot & 1; + float32 neg_imag, neg_real; + void *vd =3D &env->vfp.zregs[rd]; + void *vn =3D &env->vfp.zregs[rn]; + void *vm =3D &env->vfp.zregs[rm]; + void *va =3D &env->vfp.zregs[ra]; + uint64_t *g =3D vg; + + neg_imag =3D float32_set_sign(0, (rot & 2) !=3D 0); + neg_real =3D float32_set_sign(0, rot =3D=3D 1 || rot =3D=3D 2); + + do { + uint64_t pg =3D g[(i - 1) >> 6]; + do { + float32 e1, e2, e3, e4, nr, ni, mr, mi, d; + + /* I holds the real index; J holds the imag index. */ + j =3D i - sizeof(float32); + i -=3D 2 * sizeof(float32); + + nr =3D *(float32 *)(vn + H1_2(i)); + ni =3D *(float32 *)(vn + H1_2(j)); + mr =3D *(float32 *)(vm + H1_2(i)); + mi =3D *(float32 *)(vm + H1_2(j)); + + e2 =3D (flip ? ni : nr); + e1 =3D (flip ? mi : mr) ^ neg_real; + e4 =3D e2; + e3 =3D (flip ? mr : mi) ^ neg_imag; + + if (likely((pg >> (i & 63)) & 1)) { + d =3D *(float32 *)(va + H1_2(i)); + d =3D float32_muladd(e2, e1, d, 0, &env->vfp.fp_status); + *(float32 *)(vd + H1_2(i)) =3D d; + } + if (likely((pg >> (j & 63)) & 1)) { + d =3D *(float32 *)(va + H1_2(j)); + d =3D float32_muladd(e4, e3, d, 0, &env->vfp.fp_status); + *(float32 *)(vd + H1_2(j)) =3D d; + } + } while (i & 63); + } while (i !=3D 0); +} + +void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc) +{ + intptr_t j, i =3D simd_oprsz(desc); + unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT, 5); + unsigned rn =3D extract32(desc, SIMD_DATA_SHIFT + 5, 5); + unsigned rm =3D extract32(desc, SIMD_DATA_SHIFT + 10, 5); + unsigned ra =3D extract32(desc, SIMD_DATA_SHIFT + 15, 5); + unsigned rot =3D extract32(desc, SIMD_DATA_SHIFT + 20, 2); + bool flip =3D rot & 1; + float64 neg_imag, neg_real; + void *vd =3D &env->vfp.zregs[rd]; + void *vn =3D &env->vfp.zregs[rn]; + void *vm =3D &env->vfp.zregs[rm]; + void *va =3D &env->vfp.zregs[ra]; + uint64_t *g =3D vg; + + neg_imag =3D float64_set_sign(0, (rot & 2) !=3D 0); + neg_real =3D float64_set_sign(0, rot =3D=3D 1 || rot =3D=3D 2); + + do { + uint64_t pg =3D g[(i - 1) >> 6]; + do { + float64 e1, e2, e3, e4, nr, ni, mr, mi, d; + + /* I holds the real index; J holds the imag index. */ + j =3D i - sizeof(float64); + i -=3D 2 * sizeof(float64); + + nr =3D *(float64 *)(vn + H1_2(i)); + ni =3D *(float64 *)(vn + H1_2(j)); + mr =3D *(float64 *)(vm + H1_2(i)); + mi =3D *(float64 *)(vm + H1_2(j)); + + e2 =3D (flip ? ni : nr); + e1 =3D (flip ? mi : mr) ^ neg_real; + e4 =3D e2; + e3 =3D (flip ? mr : mi) ^ neg_imag; + + if (likely((pg >> (i & 63)) & 1)) { + d =3D *(float64 *)(va + H1_2(i)); + d =3D float64_muladd(e2, e1, d, 0, &env->vfp.fp_status); + *(float64 *)(vd + H1_2(i)) =3D d; + } + if (likely((pg >> (j & 63)) & 1)) { + d =3D *(float64 *)(va + H1_2(j)); + d =3D float64_muladd(e4, e3, d, 0, &env->vfp.fp_status); + *(float64 *)(vd + H1_2(j)) =3D d; + } + } while (i & 63); + } while (i !=3D 0); +} + /* * Load contiguous data, protected by a governing predicate. */ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 7a39be9bdd..6487fe760a 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3968,6 +3968,43 @@ DO_FMLA(FNMLS_zpzzz, fnmls_zpzzz) =20 #undef DO_FMLA =20 +static bool trans_FCMLA_zpzzz(DisasContext *s, + arg_FCMLA_zpzzz *a, uint32_t insn) +{ + static gen_helper_sve_fmla * const fns[3] =3D { + gen_helper_sve_fcmla_zpzzz_h, + gen_helper_sve_fcmla_zpzzz_s, + gen_helper_sve_fcmla_zpzzz_d, + }; + + if (a->esz =3D=3D 0) { + return false; + } + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + unsigned desc; + TCGv_i32 t_desc; + TCGv_ptr pg =3D tcg_temp_new_ptr(); + + /* We would need 7 operands to pass these arguments "properly". + * So we encode all the register numbers into the descriptor. + */ + desc =3D deposit32(a->rd, 5, 5, a->rn); + desc =3D deposit32(desc, 10, 5, a->rm); + desc =3D deposit32(desc, 15, 5, a->ra); + desc =3D deposit32(desc, 20, 2, a->rot); + desc =3D sextract32(desc, 0, 22); + desc =3D simd_desc(vsz, vsz, desc); + + t_desc =3D tcg_const_i32(desc); + tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); + fns[a->esz - 1](cpu_env, pg, t_desc); + tcg_temp_free_i32(t_desc); + tcg_temp_free_ptr(pg); + } + return true; +} + /* *** SVE Floating Point Unary Operations Prediated Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 7b5ada1311..da89697700 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -725,6 +725,10 @@ MUL_zzi 00100101 .. 110 000 110 ........ .....= @rdn_i8s FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \ rn=3D%reg_movprfx =20 +# SVE floating-point complex multiply-add (predicated) +FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \ + ra=3D%reg_movprfx + ### SVE FP Multiply-Add Indexed Group =20 # SVE floating-point multiply-add (indexed) --=20 2.17.1