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[98.147.121.51]) by smtp.gmail.com with ESMTPSA id a27-v6sm6187946pfc.18.2018.06.20.18.54.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Jun 2018 18:54:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=li9h4tydA6NYZ7tm8NAvM0RkuO1DvOT8U6gU0EDKrec=; b=IaRvnxPHffmQGsxyZo10mwgRGxXD2Jcri9Crz7ytPRU/yckYyxv7X/Na3029U8H4at dBnb8v8SHwsw1UyX5iyNkONbyYbr1xqIWKEG1BTMpGF0fy77OSFeTHQ4Gd8b568EiJ8g TBzhlhOS9cRrBd9C2WsM/G454UsJYsFrntSok= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=li9h4tydA6NYZ7tm8NAvM0RkuO1DvOT8U6gU0EDKrec=; b=DjtZdkzKUJL4+L9AlJzcns5NK7Lq0HbtKpnGJVvrclXmYLnSxvySM3pk4XKLTneDyH +neIHvye2t7AVk97z7RY/zBMMVwr0EXHMrKnIJrojxvEw5QzsHO5Mc4frRNG7gq+dnkc shMW2F8eY7dHjwChgHLr6VZclEjfNXlHxT7IGJokEyJbbPZsanmvUCnQ8oYoCXZDidEH x/7ZwfreiwsbvRnb/I0QJYRR4b23cDH2A+bz1G37WZmgsHxKJU7+f2o8xc0H3oJTwHuJ kJeA4OpA31fxlEHlOY68gjMXLcADvVkEgd1uWOaa5+zCbeGmvqDavJwyD0CdacqJYXhT ecSw== X-Gm-Message-State: APt69E3h5HECrMOjBi44rJs6TBE2oKuA9ZAkQbq0M386aJhfYVQZmOVb U+zOM7QztCYvl6tbyAzEY/sTK+S3Qxo= X-Google-Smtp-Source: ADUXVKKmMlFi5hbJLQHT4OiV7vvfRGSaCghBcVs1BdpqqqYGW7lKH2Cw1Wv33cJ/X9KL0gC5GRbxsw== X-Received: by 2002:a17:902:b18b:: with SMTP id s11-v6mr26452889plr.190.1529546098935; Wed, 20 Jun 2018 18:54:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 20 Jun 2018 15:53:52 -1000 Message-Id: <20180621015359.12018-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180621015359.12018-1-richard.henderson@linaro.org> References: <20180621015359.12018-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::235 Subject: [Qemu-devel] [PATCH v5 28/35] target/arm: Implement SVE floating-point complex add X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 7 +++ target/arm/sve_helper.c | 100 +++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 24 +++++++++ target/arm/sve.decode | 4 ++ 4 files changed, 135 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 891346a5ac..0bd9fe2f28 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -1092,6 +1092,13 @@ DEF_HELPER_FLAGS_6(sve_facgt_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_facgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_6(sve_fcadd_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sve_fcadd_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sve_fcadd_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 5309cf0866..ee7fc23bb9 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -3629,6 +3629,106 @@ void HELPER(sve_ftmad_d)(void *vd, void *vn, void *= vm, void *vs, uint32_t desc) } } =20 +/* + * FP Complex Add + */ + +void HELPER(sve_fcadd_h)(void *vd, void *vn, void *vm, void *vg, + void *vs, uint32_t desc) +{ + intptr_t j, i =3D simd_oprsz(desc); + uint64_t *g =3D vg; + float16 neg_imag =3D float16_set_sign(0, simd_data(desc)); + float16 neg_real =3D float16_chs(neg_imag); + + do { + uint64_t pg =3D g[(i - 1) >> 6]; + do { + float16 e0, e1, e2, e3; + + /* I holds the real index; J holds the imag index. */ + j =3D i - sizeof(float16); + i -=3D 2 * sizeof(float16); + + e0 =3D *(float16 *)(vn + H1_2(i)); + e1 =3D *(float16 *)(vm + H1_2(j)) ^ neg_real; + e2 =3D *(float16 *)(vn + H1_2(j)); + e3 =3D *(float16 *)(vm + H1_2(i)) ^ neg_imag; + + if (likely((pg >> (i & 63)) & 1)) { + *(float16 *)(vd + H1_2(i)) =3D float16_add(e0, e1, vs); + } + if (likely((pg >> (j & 63)) & 1)) { + *(float16 *)(vd + H1_2(j)) =3D float16_add(e2, e3, vs); + } + } while (i & 63); + } while (i !=3D 0); +} + +void HELPER(sve_fcadd_s)(void *vd, void *vn, void *vm, void *vg, + void *vs, uint32_t desc) +{ + intptr_t j, i =3D simd_oprsz(desc); + uint64_t *g =3D vg; + float32 neg_imag =3D float32_set_sign(0, simd_data(desc)); + float32 neg_real =3D float32_chs(neg_imag); + + do { + uint64_t pg =3D g[(i - 1) >> 6]; + do { + float32 e0, e1, e2, e3; + + /* I holds the real index; J holds the imag index. */ + j =3D i - sizeof(float32); + i -=3D 2 * sizeof(float32); + + e0 =3D *(float32 *)(vn + H1_2(i)); + e1 =3D *(float32 *)(vm + H1_2(j)) ^ neg_real; + e2 =3D *(float32 *)(vn + H1_2(j)); + e3 =3D *(float32 *)(vm + H1_2(i)) ^ neg_imag; + + if (likely((pg >> (i & 63)) & 1)) { + *(float32 *)(vd + H1_2(i)) =3D float32_add(e0, e1, vs); + } + if (likely((pg >> (j & 63)) & 1)) { + *(float32 *)(vd + H1_2(j)) =3D float32_add(e2, e3, vs); + } + } while (i & 63); + } while (i !=3D 0); +} + +void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg, + void *vs, uint32_t desc) +{ + intptr_t j, i =3D simd_oprsz(desc); + uint64_t *g =3D vg; + float64 neg_imag =3D float64_set_sign(0, simd_data(desc)); + float64 neg_real =3D float64_chs(neg_imag); + + do { + uint64_t pg =3D g[(i - 1) >> 6]; + do { + float64 e0, e1, e2, e3; + + /* I holds the real index; J holds the imag index. */ + j =3D i - sizeof(float64); + i -=3D 2 * sizeof(float64); + + e0 =3D *(float64 *)(vn + H1_2(i)); + e1 =3D *(float64 *)(vm + H1_2(j)) ^ neg_real; + e2 =3D *(float64 *)(vn + H1_2(j)); + e3 =3D *(float64 *)(vm + H1_2(i)) ^ neg_imag; + + if (likely((pg >> (i & 63)) & 1)) { + *(float64 *)(vd + H1_2(i)) =3D float64_add(e0, e1, vs); + } + if (likely((pg >> (j & 63)) & 1)) { + *(float64 *)(vd + H1_2(j)) =3D float64_add(e2, e3, vs); + } + } while (i & 63); + } while (i !=3D 0); +} + /* * Load contiguous data, protected by a governing predicate. */ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 067c219b54..7a39be9bdd 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3895,6 +3895,30 @@ DO_FPCMP(FACGT, facgt) =20 #undef DO_FPCMP =20 +static bool trans_FCADD(DisasContext *s, arg_FCADD *a, uint32_t insn) +{ + static gen_helper_gvec_4_ptr * const fns[3] =3D { + gen_helper_sve_fcadd_h, + gen_helper_sve_fcadd_s, + gen_helper_sve_fcadd_d + }; + + if (a->esz =3D=3D 0) { + return false; + } + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + pred_full_reg_offset(s, a->pg), + status, vsz, vsz, a->rot, fns[a->esz - 1]); + tcg_temp_free_ptr(status); + } + return true; +} + typedef void gen_helper_sve_fmla(TCGv_env, TCGv_ptr, TCGv_i32); =20 static bool do_fmla(DisasContext *s, arg_rprrr_esz *a, gen_helper_sve_fmla= *fn) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 85f2b39776..7b5ada1311 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -721,6 +721,10 @@ UMIN_zzi 00100101 .. 101 011 110 ........ .....= @rdn_i8u # SVE integer multiply immediate (unpredicated) MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s =20 +# SVE floating-point complex add (predicated) +FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \ + rn=3D%reg_movprfx + ### SVE FP Multiply-Add Indexed Group =20 # SVE floating-point multiply-add (indexed) --=20 2.17.1