From nobody Tue Feb 10 22:17:59 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529496716548368.01056192392093; Wed, 20 Jun 2018 05:11:56 -0700 (PDT) Received: from localhost ([::1]:49012 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbxr-00068y-MN for importer@patchew.org; Wed, 20 Jun 2018 08:11:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34919) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbtb-0002iZ-Pz for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:07:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbta-0003XR-9p for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:07:31 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.224]:59798) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbta-0003Tk-2j for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:07:30 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx4.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:07:22 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:06:55 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:49 +0100 Message-ID: <20180620120620.12806-5-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496400-298555-14288-41748-5 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 1.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.50 BSF_RULE_7582B META: Custom Rule 7582B 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=1.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_RULE_7582B, BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.224 Subject: [Qemu-devel] [PATCH 04/35] target/mips: Add decode_nanomips_opc() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nanoMIPS decoder. It covers P16 pool arithmetic and branch instructions. Signed-off-by: Yongbok Kim --- target/mips/translate.c | 293 ++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 292 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 27d5fb2..633d0b4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16200,6 +16200,293 @@ enum { NM_EVP =3D 0x01 }; =20 +static int mmreg_nanomips(int r) +{ + static const int map[] =3D { 16, 17, 18, 19, 4, 5, 6, 7 }; + + return map[r & 0x7]; +} + +static int mmreg4_nanomips(int r) +{ + static const int map[] =3D { 8, 9, 10, 11, 4, 5, 6, 7, + 16, 17, 18, 19, 20, 21, 22, 23 }; + + return map[r & 0xf]; +} + +/* Used for 16-bit store instructions. */ +static int mmreg4z_nanomips(int r) +{ + static const int map[] =3D { 8, 9, 10, 0, 4, 5, 6, 7, + 16, 17, 18, 19, 20, 21, 22, 23 }; + + return map[r & 0xf]; +} + +static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t op; + int rt =3D mmreg_nanomips(uMIPS_RD(ctx->opcode)); + int rs =3D mmreg_nanomips(uMIPS_RS(ctx->opcode)); + int rd =3D mmreg_nanomips(uMIPS_RS1(ctx->opcode)); + + /* make sure instructions are on a halfword boundary */ + if (ctx->base.pc_next & 0x1) { + env->CP0_BadVAddr =3D ctx->base.pc_next; + generate_exception_end(ctx, EXCP_AdEL); + return 2; + } + + op =3D (ctx->opcode >> 10) & 0x3f; + switch (op) { + case NM_P16_MV: + { + int rt =3D uMIPS_RD5(ctx->opcode); + if (rt !=3D 0) { + /* MOVE */ + int rs =3D uMIPS_RS5(ctx->opcode); + gen_arith(ctx, OPC_ADDU, rt, rs, 0); + } else { + /* P16.RI */ + switch ((ctx->opcode >> 3) & 0x3) { + case NM_P16_SYSCALL: + generate_exception_end(ctx, EXCP_SYSCALL); + break; + case NM_BREAK16: + generate_exception_end(ctx, EXCP_BREAK); + break; + case NM_SDBBP16: + if (is_uhi(extract32(ctx->opcode, 0, 3))) { + gen_helper_do_semihosting(cpu_env); + } else { + if (ctx->hflags & MIPS_HFLAG_SBRI) { + generate_exception_end(ctx, EXCP_RI); + } else { + generate_exception_end(ctx, EXCP_DBp); + } + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } + } + break; + case NM_P16_SHIFT: + { + int shift =3D (ctx->opcode) & 0x7; + uint32_t opc =3D 0; + shift =3D (shift =3D=3D 0) ? 8 : shift; + + switch ((ctx->opcode >> 3) & 1) { + case NM_SLL16: + opc =3D OPC_SLL; + break; + case NM_SRL16: + opc =3D OPC_SRL; + break; + } + gen_shift_imm(ctx, opc, rt, rs, shift); + } + break; + case NM_P16C: + break; + case NM_P16_A1: + switch ((ctx->opcode >> 6) & 1) { + case NM_ADDIUR1SP: + gen_arith_imm(ctx, OPC_ADDIU, rt, 29, + extract32(ctx->opcode, 0, 6) << 2); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P16_A2: + switch ((ctx->opcode >> 3) & 1) { + case NM_ADDIUR2: + { + uint8_t u =3D (uint8_t) extract32(ctx->opcode, 0, 3) << 2; + gen_arith_imm(ctx, OPC_ADDIU, rt, rs, u); + } + break; + case NM_P_ADDIURS5: + { + int rt =3D extract32(ctx->opcode, 5, 5); + if (rt !=3D 0) { + int s =3D (sextract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + /* s =3D sign_extend( s[3] . s[2:0] , from_nbits =3D 4)*/ + gen_arith_imm(ctx, OPC_ADDIU, rt, rt, s); + } + } + break; + } + break; + case NM_P16_ADDU: + switch (ctx->opcode & 0x1) { + case NM_ADDU16: + gen_arith(ctx, OPC_ADDU, rd, rs, rt); + break; + case NM_SUBU16: + gen_arith(ctx, OPC_SUBU, rd, rs, rt); + break; + } + break; + case NM_P16_4X4: + { + int rt =3D (extract32(ctx->opcode, 9, 1) << 3) | + extract32(ctx->opcode, 5, 3); + int rs =3D (extract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + rt =3D mmreg4_nanomips(rt); + rs =3D mmreg4_nanomips(rs); + + switch (((ctx->opcode >> 7) & 0x2) | ((ctx->opcode >> 3) & 0x1)) { + case NM_ADDU4X4: + gen_arith(ctx, OPC_ADDU, rt, rs, rt); + break; + case NM_MUL4X4: + gen_r6_muldiv(ctx, R6_OPC_MUL, rt, rs, rt); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } + break; + case NM_LI16: + { + int imm =3D extract32(ctx->opcode, 0, 7); + imm =3D (imm =3D=3D 0x7f ? -1 : imm); + if (rt !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[rt], imm); + } + } + break; + case NM_ANDI16: + { + uint32_t u =3D extract32(ctx->opcode, 0, 4); + u =3D (u =3D=3D 12) ? 0xff : + (u =3D=3D 13) ? 0xffff : u; + gen_logic_imm(ctx, OPC_ANDI, rt, rs, u); + } + break; + case NM_P16_LB: + break; + case NM_P16_LH: + break; + case NM_LW16: + break; + case NM_LWSP16: + break; + case NM_LW4X4: + break; + case NM_SW4X4: + break; + case NM_LWGP16: + break; + case NM_SWSP16: + break; + case NM_SW16: + break; + case NM_SWGP16: + break; + case NM_BC16: + gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, + (sextract32(ctx->opcode, 0, 1) << 10) | + (extract32(ctx->opcode, 1, 9) << 1), + 0); + break; + case NM_BALC16: + gen_compute_branch(ctx, OPC_BGEZAL, 2, 0, 0, + (sextract32(ctx->opcode, 0, 1) << 10) | + (extract32(ctx->opcode, 1, 9) << 1), + 0); + break; + case NM_BEQZC16: + case NM_BNEZC16: + gen_compute_branch(ctx, op =3D=3D NM_BNEZC16 ? OPC_BNE : OPC_BEQ, = 2, + rt, 0, + (sextract32(ctx->opcode, 0, 1) << 7) | + (extract32(ctx->opcode, 1, 6) << 1), + 0); + break; + case NM_P16_BR: + switch (ctx->opcode & 0xf) { + case 0: + /* P16.JRC */ + switch ((ctx->opcode >> 4) & 1) { + case NM_JRC: + gen_compute_branch(ctx, OPC_JR, 2, + extract32(ctx->opcode, 5, 5), 0, 0, 0); + break; + case NM_JALRC16: + gen_compute_branch(ctx, OPC_JALR, 2, + extract32(ctx->opcode, 5, 5), 31, 0, 0); + break; + } + break; + default: + /* P16.BRI */ + if (extract32(ctx->opcode, 4, 3) < extract32(ctx->opcode, 7, 3= )) { + /* BEQC16 */ + gen_compute_branch(ctx, OPC_BEQ, 2, rs, rt, + extract32(ctx->opcode, 0, 4) << 1, 0); + } else { + /* BNEC16 */ + gen_compute_branch(ctx, OPC_BNE, 2, rs, rt, + extract32(ctx->opcode, 0, 4) << 1, 0); + } + break; + } + break; + case NM_P16_SR: + break; + case NM_MOVEP: + case NM_MOVEPREV: + { + static const int gpr2reg1[] =3D {4, 5, 6, 7}; + static const int gpr2reg2[] =3D {5, 6, 7, 8}; + int re; + int rd2 =3D extract32(ctx->opcode, 3, 1) << 1 | + extract32(ctx->opcode, 8, 1); + int r1 =3D gpr2reg1[rd2]; + int r2 =3D gpr2reg2[rd2]; + int r3 =3D extract32(ctx->opcode, 4, 1) << 3 | + extract32(ctx->opcode, 0, 3); + int r4 =3D extract32(ctx->opcode, 9, 1) << 3 | + extract32(ctx->opcode, 5, 3); + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + if (op =3D=3D NM_MOVEP) { + rd =3D r1; + re =3D r2; + rs =3D mmreg4z_nanomips(r3); + rt =3D mmreg4z_nanomips(r4); + } else { + rd =3D mmreg4_nanomips(r3); + re =3D mmreg4_nanomips(r4); + rs =3D r1; + rt =3D r2; + } + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + tcg_gen_mov_tl(cpu_gpr[rd], t0); + tcg_gen_mov_tl(cpu_gpr[re], t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + default: + break; + } + + return 2; +} + /* SmartMIPS extension to MIPS32 */ =20 #if defined(TARGET_MIPS64) @@ -20950,7 +21237,11 @@ static void mips_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cs) decode_opc(env, ctx); } else if (ctx->insn_flags & ASE_MICROMIPS) { ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); - insn_bytes =3D decode_micromips_opc(env, ctx); + if (env->insn_flags & ISA_NANOMIPS32) { + insn_bytes =3D decode_nanomips_opc(env, ctx); + } else { + insn_bytes =3D decode_micromips_opc(env, ctx); + } } else if (ctx->insn_flags & ASE_MIPS16) { ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); insn_bytes =3D decode_mips16_opc(env, ctx); --=20 1.9.1