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X-Received-From: 64.235.150.224 Subject: [Qemu-devel] [PATCH 35/35] target/mips: Add I7200 CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add I7200 CPU Reference: https://www.mips.com/products/warrior/i-class-i7200-multiprocessor-core/ Signed-off-by: Yongbok Kim --- target/mips/translate_init.inc.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.= inc.c index c7ba6ee..262ff29 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -449,6 +449,43 @@ const mips_def_t mips_defs[] =3D .insn_flags =3D CPU_MIPS32R6 | ASE_MICROMIPS, .mmu_type =3D MMU_TYPE_R4000, }, + { + .name =3D "I7200", + .CP0_PRid =3D 0x00010000, + .CP0_Config0 =3D MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR= ) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 =3D MIPS_CONFIG1 | (15 << CP0C1_MMU) | (2 << CP0C1_IS= ) | + (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS)= | + (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC)= | + (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 =3D MIPS_CONFIG2, + .CP0_Config3 =3D MIPS_CONFIG3 | (1 << CP0C3_CMGCR) | (1 << CP0C3_B= I) | + (3 << CP0C3_MMAR) | (1 << CP0C3_ISA_ON_EXC) | + (1 << CP0C3_ISA) | (1 << CP0C3_ULRI) | + (1 << CP0C3_RXI) | + (1 << CP0C3_VInt) | (1U << CP0C3_M) | (1 << CP0C3_M= T), + .CP0_Config4 =3D MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | + (2 << CP0C4_IE) | (1U << CP0C4_M), + .CP0_Config5 =3D MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB= ), + .CP0_Config5_rw_bitmask =3D (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | + (1 << CP0C5_UFE), + .CP0_LLAddr_rw_bitmask =3D 0, + .CP0_LLAddr_shift =3D 0, + .SYNCI_Step =3D 32, + .CCRes =3D 2, + .CP0_Status_rw_bitmask =3D 0x3058FF1F, + .CP0_PageGrain =3D (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | + (1U << CP0PG_RIE), + .CP0_PageGrain_rw_bitmask =3D 0, + .CP1_fcr0 =3D (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_= F64) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV= ), + .CP1_fcr31 =3D (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), + .SEGBITS =3D 32, + .PABITS =3D 32, + .insn_flags =3D CPU_NANOMIPS32 | ASE_MICROMIPS, + .mmu_type =3D MMU_TYPE_R4000, + }, #if defined(TARGET_MIPS64) { .name =3D "R4000", --=20 1.9.1