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X-Received-From: 64.235.154.211 Subject: [Qemu-devel] [PATCH 24/35] target/mips: Add nanoMIPS CP0_BadInstrX register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add nanoMIPS CP0_BadInstrX register Signed-off-by: Stefan Markovic Signed-off-by: Yongbok Kim --- target/mips/cpu.h | 1 + target/mips/helper.c | 6 ++++++ target/mips/machine.c | 1 + target/mips/translate.c | 18 ++++++++++++++++++ 4 files changed, 26 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 18f193d..c87184f 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -323,6 +323,7 @@ struct CPUMIPSState { target_ulong CP0_BadVAddr; uint32_t CP0_BadInstr; uint32_t CP0_BadInstrP; + uint32_t CP0_BadInstrX; int32_t CP0_Count; target_ulong CP0_EntryHi; #define CP0EnHi_EHINV 10 diff --git a/target/mips/helper.c b/target/mips/helper.c index 5299f21..9535131 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -695,6 +695,12 @@ static inline void set_badinstr_registers(CPUMIPSState= *env) instr |=3D cpu_lduw_code(env, env->active_tc.PC + 2); } env->CP0_BadInstr =3D instr; + + if ((env->insn_flags & ISA_NANOMIPS32) && + ((instr & 0xFC000000) =3D=3D 0x60000000)) { + instr =3D cpu_lduw_code(env, env->active_tc.PC + 4) << 16; + env->CP0_BadInstrX =3D instr; + } } if ((env->CP0_Config3 & (1 << CP0C3_BP)) && (env->hflags & MIPS_HFLAG_BMASK)) { diff --git a/target/mips/machine.c b/target/mips/machine.c index 20100d5..58f3255 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -266,6 +266,7 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU), VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU), VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU), + VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU), VMSTATE_INT32(env.CP0_Count, MIPSCPU), VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), VMSTATE_INT32(env.CP0_Compare, MIPSCPU), diff --git a/target/mips/translate.c b/target/mips/translate.c index 8c20ba3..ece2293 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5429,6 +5429,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); rn =3D "BadInstrP"; break; + case 3: + CP0_CHECK(ctx->bi); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX)); + rn =3D "BadInstrX"; + break; default: goto cp0_unimplemented; } @@ -6098,6 +6103,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) /* ignored */ rn =3D "BadInstrP"; break; + case 3: + /* ignored */ + rn =3D "BadInstrX"; + break; default: goto cp0_unimplemented; } @@ -6781,6 +6790,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); rn =3D "BadInstrP"; break; + case 3: + CP0_CHECK(ctx->bi); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX)); + rn =3D "BadInstrX"; + break; default: goto cp0_unimplemented; } @@ -7433,6 +7447,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) /* ignored */ rn =3D "BadInstrP"; break; + case 3: + /* ignored */ + rn =3D "BadInstrX"; + break; default: goto cp0_unimplemented; } --=20 1.9.1