From nobody Tue Feb 10 22:18:42 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529496542567914.1319795434478; Wed, 20 Jun 2018 05:09:02 -0700 (PDT) Received: from localhost ([::1]:48993 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbuz-0003LZ-7T for importer@patchew.org; Wed, 20 Jun 2018 08:08:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34850) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVbtC-0002Vr-CE for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:07:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVbt8-0003Jp-De for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:07:06 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.224]:33281) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVbt8-0003HG-7L for qemu-devel@nongnu.org; Wed, 20 Jun 2018 08:07:02 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx4.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Wed, 20 Jun 2018 12:06:54 +0000 Received: from ubuntu1404.mipstec.com (192.168.40.13) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Wed, 20 Jun 2018 05:06:43 -0700 From: Yongbok Kim To: Date: Wed, 20 Jun 2018 13:05:46 +0100 Message-ID: <20180620120620.12806-2-yongbok.kim@mips.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.40.13] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1529496400-298555-14288-41748-2 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Envelope-From: Yongbok.Kim@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194221 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: qemu-devel@nongnu.org,aurelien@aurel32.net X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.150.224 Subject: [Qemu-devel] [PATCH 01/35] target/mips: Raise a RI when given fs is n/a from CTC1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Fix to raise a Reserved Instruction exception when given fs is not available from CTC1. Signed-off-by: Yongbok Kim Reviewed-by: Aleksandar Markovic --- target/mips/op_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 9025f42..41d3634 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2627,6 +2627,9 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1= , uint32_t fs, uint32_t rt) (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask= )); break; default: + if (env->insn_flags & ISA_MIPS32R6) { + do_raise_exception(env, EXCP_RI, GETPC()); + } return; } restore_fp_status(env); --=20 1.9.1