From nobody Tue Feb 10 05:44:05 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529410205651893.915374802479; Tue, 19 Jun 2018 05:10:05 -0700 (PDT) Received: from localhost ([::1]:41186 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVFSN-0002Cr-EK for importer@patchew.org; Tue, 19 Jun 2018 08:09:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41791) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVFNT-00077Y-33 for qemu-devel@nongnu.org; Tue, 19 Jun 2018 08:04:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVFNN-0001lz-48 for qemu-devel@nongnu.org; Tue, 19 Jun 2018 08:04:51 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:57902 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVFNM-0001ln-Vc; Tue, 19 Jun 2018 08:04:45 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7EF3787A7C; Tue, 19 Jun 2018 12:04:44 +0000 (UTC) Received: from localhost (dhcp-192-215.str.redhat.com [10.33.192.215]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2ECBF213ED6A; Tue, 19 Jun 2018 12:04:44 +0000 (UTC) From: Cornelia Huck To: Peter Maydell Date: Tue, 19 Jun 2018 14:04:24 +0200 Message-Id: <20180619120434.25062-3-cohuck@redhat.com> In-Reply-To: <20180619120434.25062-1-cohuck@redhat.com> References: <20180619120434.25062-1-cohuck@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.6 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Tue, 19 Jun 2018 12:04:44 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Tue, 19 Jun 2018 12:04:44 +0000 (UTC) for IP:'10.11.54.6' DOMAIN:'int-mx06.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'cohuck@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [PULL 02/12] vfio-ccw: add force unlimited prefetch property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , David Hildenbrand , Cornelia Huck , Alexander Graf , qemu-devel@nongnu.org, Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Halil Pasic There is at least one guest (OS) such that although it does not rely on the guarantees provided by ORB 1 word 9 bit (aka unlimited prefetch, aka P bit) not being set, it fails to tell this to the machine. Usually this ain't a big deal, as the original purpose of the P bit is to allow for performance optimizations. vfio-ccw however can not provide the guarantees required if the bit is not set. It is not possible to implement support for the P bit not set without transitioning to lower level protocols for vfio-ccw. So let's give the user the opportunity to force setting the P bit, if the user knows this is safe. For self modifying channel programs forcing the P bit is not safe. If the P bit is forced for a self modifying channel program things are expected to break in strange ways. Let's also avoid warning multiple about P bit not set in the ORB in case P bit is not told to be forced, and designate the affected vfio-ccw device. Signed-off-by: Halil Pasic Suggested-by: Dong Jia Shi Acked-by: Jason J. Herne Tested-by: Jason J. Herne Message-Id: <20180524175828.3143-2-pasic@linux.ibm.com> Signed-off-by: Cornelia Huck --- hw/s390x/css.c | 3 +-- hw/vfio/ccw.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/hw/s390x/css.c b/hw/s390x/css.c index 56c3fa8c89..39ae5bbf7e 100644 --- a/hw/s390x/css.c +++ b/hw/s390x/css.c @@ -1204,8 +1204,7 @@ static IOInstEnding sch_handle_start_func_passthrough= (SubchDev *sch) * Only support prefetch enable mode. * Only support 64bit addressing idal. */ - if (!(orb->ctrl0 & ORB_CTRL0_MASK_PFCH) || - !(orb->ctrl0 & ORB_CTRL0_MASK_C64)) { + if (!(orb->ctrl0 & ORB_CTRL0_MASK_C64)) { warn_report("vfio-ccw requires PFCH and C64 flags set"); sch_gen_unit_exception(sch); css_inject_io_interrupt(sch); diff --git a/hw/vfio/ccw.c b/hw/vfio/ccw.c index 76e4e8c652..351b305e1a 100644 --- a/hw/vfio/ccw.c +++ b/hw/vfio/ccw.c @@ -33,8 +33,30 @@ typedef struct VFIOCCWDevice { uint64_t io_region_offset; struct ccw_io_region *io_region; EventNotifier io_notifier; + bool force_orb_pfch; + bool warned_orb_pfch; } VFIOCCWDevice; =20 +static inline void warn_once(bool *warned, const char *fmt, ...) +{ + va_list ap; + + if (!warned || *warned) { + return; + } + *warned =3D true; + va_start(ap, fmt); + warn_vreport(fmt, ap); + va_end(ap); +} + +static inline void warn_once_pfch(VFIOCCWDevice *vcdev, SubchDev *sch, + const char *msg) +{ + warn_once(&vcdev->warned_orb_pfch, "vfio-ccw (devno %x.%x.%04x): %s", + sch->cssid, sch->ssid, sch->devno, msg); +} + static void vfio_ccw_compute_needs_reset(VFIODevice *vdev) { vdev->needs_reset =3D false; @@ -55,6 +77,18 @@ static IOInstEnding vfio_ccw_handle_request(SubchDev *sc= h) struct ccw_io_region *region =3D vcdev->io_region; int ret; =20 + if (!(sch->orb.ctrl0 & ORB_CTRL0_MASK_PFCH)) { + if (!(vcdev->force_orb_pfch)) { + warn_once_pfch(vcdev, sch, "requires PFCH flag set"); + sch_gen_unit_exception(sch); + css_inject_io_interrupt(sch); + return IOINST_CC_EXPECTED; + } else { + sch->orb.ctrl0 |=3D ORB_CTRL0_MASK_PFCH; + warn_once_pfch(vcdev, sch, "PFCH flag forced"); + } + } + QEMU_BUILD_BUG_ON(sizeof(region->orb_area) !=3D sizeof(ORB)); QEMU_BUILD_BUG_ON(sizeof(region->scsw_area) !=3D sizeof(SCSW)); QEMU_BUILD_BUG_ON(sizeof(region->irb_area) !=3D sizeof(IRB)); @@ -430,6 +464,7 @@ static void vfio_ccw_unrealize(DeviceState *dev, Error = **errp) =20 static Property vfio_ccw_properties[] =3D { DEFINE_PROP_STRING("sysfsdev", VFIOCCWDevice, vdev.sysfsdev), + DEFINE_PROP_BOOL("force-orb-pfch", VFIOCCWDevice, force_orb_pfch, fals= e), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.14.4