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X-Received-From: 2607:f8b0:4003:c06::232 Subject: [Qemu-devel] [PATCH 085/113] hw/intc/arm_gicv3: Fix APxR register dispatching X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Kiszka , qemu-stable@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Jan Kiszka There was a nasty flip in identifying which register group an access is targeting. The issue caused spuriously raised priorities of the guest when handing CPUs over in the Jailhouse hypervisor. Cc: qemu-stable@nongnu.org Signed-off-by: Jan Kiszka Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell (cherry picked from commit 887aae10f6150dfdc71c45d7588e8efe6c144019) Signed-off-by: Michael Roth --- hw/intc/arm_gicv3_cpuif.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 5cbafaf497..519d581bb6 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -431,7 +431,7 @@ static uint64_t icv_ap_read(CPUARMState *env, const ARM= CPRegInfo *ri) { GICv3CPUState *cs =3D icc_cs_from_env(env); int regno =3D ri->opc2 & 3; - int grp =3D ri->crm & 1 ? GICV3_G0 : GICV3_G1NS; + int grp =3D (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; uint64_t value =3D cs->ich_apr[grp][regno]; =20 trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), va= lue); @@ -443,7 +443,7 @@ static void icv_ap_write(CPUARMState *env, const ARMCPR= egInfo *ri, { GICv3CPUState *cs =3D icc_cs_from_env(env); int regno =3D ri->opc2 & 3; - int grp =3D ri->crm & 1 ? GICV3_G0 : GICV3_G1NS; + int grp =3D (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; =20 trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), v= alue); =20 @@ -1465,7 +1465,7 @@ static uint64_t icc_ap_read(CPUARMState *env, const A= RMCPRegInfo *ri) uint64_t value; =20 int regno =3D ri->opc2 & 3; - int grp =3D ri->crm & 1 ? GICV3_G0 : GICV3_G1; + int grp =3D (ri->crm & 1) ? GICV3_G1 : GICV3_G0; =20 if (icv_access(env, grp =3D=3D GICV3_G0 ? HCR_FMO : HCR_IMO)) { return icv_ap_read(env, ri); @@ -1487,7 +1487,7 @@ static void icc_ap_write(CPUARMState *env, const ARMC= PRegInfo *ri, GICv3CPUState *cs =3D icc_cs_from_env(env); =20 int regno =3D ri->opc2 & 3; - int grp =3D ri->crm & 1 ? GICV3_G0 : GICV3_G1; + int grp =3D (ri->crm & 1) ? GICV3_G1 : GICV3_G0; =20 if (icv_access(env, grp =3D=3D GICV3_G0 ? HCR_FMO : HCR_IMO)) { icv_ap_write(env, ri, value); @@ -2296,7 +2296,7 @@ static uint64_t ich_ap_read(CPUARMState *env, const A= RMCPRegInfo *ri) { GICv3CPUState *cs =3D icc_cs_from_env(env); int regno =3D ri->opc2 & 3; - int grp =3D ri->crm & 1 ? GICV3_G0 : GICV3_G1NS; + int grp =3D (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; uint64_t value; =20 value =3D cs->ich_apr[grp][regno]; @@ -2309,7 +2309,7 @@ static void ich_ap_write(CPUARMState *env, const ARMC= PRegInfo *ri, { GICv3CPUState *cs =3D icc_cs_from_env(env); int regno =3D ri->opc2 & 3; - int grp =3D ri->crm & 1 ? GICV3_G0 : GICV3_G1NS; + int grp =3D (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; =20 trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), v= alue); =20 --=20 2.11.0