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[98.147.121.51]) by smtp.gmail.com with ESMTPSA id i65-v6sm49457254pfd.17.2018.06.18.11.41.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jun 2018 11:41:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=V/jeWmFGQVVeKWPcvaBSAlQuL/FGCb4V1yNp9F8huX4=; b=jf5r+Wejt3mGA9xulBqhI0KH04CstPoTbBHq72G2R/EjBTx2Keg7JBfjQV/1pBcPVa fq3Ce9jLVb81bY2/nRyIpBjJTCvOw1XioqmeRlAvm7SKIQevh59XudMJIGFbvjyfN5/O J2yfGuV4byHOZ2hQixMMFrHcFQ0tqzA9L6LI8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V/jeWmFGQVVeKWPcvaBSAlQuL/FGCb4V1yNp9F8huX4=; b=etpoHGEgGorwLue1PxPF4ByJ8WtppHCLvvqasZdvJbXcrv21h4tYNvsJD4Tiz/F2Zj RDiX1TxF6v9Rj/QzQea6yqJqb7WIArTxtRX8p6fj4aNO1xr07M2NuNFbHfY216yQWC2Y 0GCtmk2JDVcVgKYFSeWqOUB526dZlfbvUm00LxvH88601aflFs4HIubDaSNgOFl7EmAj sw2AXBbxqf0WKyuKLi7O2J+lZI+ma9w/TAcUGBmeJhVDkjvDKXtdMIwS027+rTx5XeqJ Ah3/TiZFMovCft3JlGoTL4y/pGNdvgV3WsOwcmvFUzru6qa5mnnBNGMbqOZebz8bb0DT DIAQ== X-Gm-Message-State: APt69E2hEu079c9wIF1S4I44gHjLnyDrTQMmJnUN3Nxt5JrVnAUHc8pc Ai77d3/vse8kXIDVtr7wFRJRPptqHQQ= X-Google-Smtp-Source: ADUXVKImShD46e0rLRyakzkYqlX2npO1cTgn3ajP+PG+F+a+g3HjuZ1Df0OYthlIQ+8AsTspr4+uxw== X-Received: by 2002:a65:660a:: with SMTP id w10-v6mr11765294pgv.366.1529347280560; Mon, 18 Jun 2018 11:41:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Jun 2018 08:40:41 -1000 Message-Id: <20180618184046.6270-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180618184046.6270-1-richard.henderson@linaro.org> References: <20180618184046.6270-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::231 Subject: [Qemu-devel] [PATCH v2 17/22] target/openrisc: Increase the TLB size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The architecture supports 128 TLB entries. There is no reason not to provide all of them. In the process we need to fix a bug that failed to parameterize the configuration register that tells the operating system the number of entries. Signed-off-by: Richard Henderson --- v2: - Change VMState version. --- target/openrisc/cpu.h | 2 +- target/openrisc/cpu.c | 6 ++++-- target/openrisc/machine.c | 5 ++--- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 53abe965e8..8035654087 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,7 +222,7 @@ enum { =20 /* TLB size */ enum { - TLB_SIZE =3D 64, + TLB_SIZE =3D 128, TLB_MASK =3D TLB_SIZE - 1, }; =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 4c166c6329..677f02efa4 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -52,8 +52,10 @@ static void openrisc_cpu_reset(CPUState *s) =20 cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; - cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 <= < 2)); - cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 <= < 2)); + cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) + | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); + cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) + | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); =20 #ifndef CONFIG_USER_ONLY cpu->env.picmr =3D 0x00000000; diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 3fc837b925..1eedbf3dbe 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -38,9 +38,8 @@ static const VMStateDescription vmstate_tlb_entry =3D { =20 static const VMStateDescription vmstate_cpu_tlb =3D { .name =3D "cpu_tlb", - .version_id =3D 1, - .minimum_version_id =3D 1, - .minimum_version_id_old =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), --=20 2.17.1