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[98.147.121.51]) by smtp.gmail.com with ESMTPSA id i65-v6sm49457254pfd.17.2018.06.18.11.41.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jun 2018 11:41:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZBFXVHb8oEn5W3bnIqvhmT0QND9o29BCX1TtsvICkS0=; b=c9qdcke3dvmYy1K9qFBdbpRHj7ch8lUZC0i5uq/XmVaDWwqqlI0DLJS2SjQbUJIHCn bV2Ve0wtEHma+p6FczvnP1uiAV30dD97YlYAy8R6nYuPs/3HBFxWw9gVbzFrRE8TqO8y md3Q417q+YSq42eYQHnlF0da8RPHypNWrklIQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZBFXVHb8oEn5W3bnIqvhmT0QND9o29BCX1TtsvICkS0=; b=g8GyV7tL8bpnyhafX5kWLWTpK71dTqgf9Sdg+sVrEGg8lZakMRN8o3zpmrgF53s+D+ FfADy6vbjaHGgOGoej3Mo6e98Pkxxi3AWizhd+P8qsupPzplys17Q/Ot4WI9c5776aSh zjmzaBb2Za/FTRy/Mjq4d2JysBplU58IEdFGnth8F4gWhqkxkWVxycfFKiQOPGpKxNAw C6nwP5nuj6X899lFRVtOi2tWHNXuoXJeKoMT0G3sZo4pa+CbbECfeO67DkSowEvKlG59 qm3CQwnEF0P3y5H8bD6K3A3kK+FboXTCb1Gng13tQBRBTQHYNpK3QjJMlCzAe+mqRAbs TtvQ== X-Gm-Message-State: APt69E0D9GvLkZzIugtqYMrB2u0odMcCSmIBfjlneIB2EWzYl+p+oeyY +Vz0XtcTcw7yVBDSDT8vftmZyOeaalM= X-Google-Smtp-Source: ADUXVKKJeqPetFt22rjJRljrMYDiEoQl/7QO8BJYOCNyYaZ0ggxPEzPRVYoC9fy/c4MtV1AfkR6XVg== X-Received: by 2002:a17:902:6bc7:: with SMTP id m7-v6mr15591274plt.162.1529347278797; Mon, 18 Jun 2018 11:41:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Jun 2018 08:40:40 -1000 Message-Id: <20180618184046.6270-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180618184046.6270-1-richard.henderson@linaro.org> References: <20180618184046.6270-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::234 Subject: [Qemu-devel] [PATCH v2 16/22] target/openrisc: Log interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/openrisc/interrupt.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index e28042856a..138ad17f00 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -32,6 +32,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) #ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); CPUOpenRISCState *env =3D &cpu->env; + int exception =3D cs->exception_index; =20 env->epcr =3D env->pc; if (env->dflag) { @@ -41,12 +42,12 @@ void openrisc_cpu_do_interrupt(CPUState *cs) } else { env->sr &=3D ~SR_DSX; } - if (cs->exception_index =3D=3D EXCP_SYSCALL) { + if (exception =3D=3D EXCP_SYSCALL) { env->epcr +=3D 4; } /* When we have an illegal instruction the error effective address shall be set to the illegal instruction address. */ - if (cs->exception_index =3D=3D EXCP_ILLEGAL) { + if (exception =3D=3D EXCP_ILLEGAL) { env->eear =3D env->pc; } =20 @@ -60,8 +61,27 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->pmr &=3D ~PMR_SME; env->lock_addr =3D -1; =20 - if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { - hwaddr vect_pc =3D cs->exception_index << 8; + if (exception > 0 && exception < EXCP_NR) { + static const char * const int_name[EXCP_NR] =3D { + [EXCP_RESET] =3D "RESET", + [EXCP_BUSERR] =3D "BUSERR (bus error)", + [EXCP_DPF] =3D "DFP (data protection fault)", + [EXCP_IPF] =3D "IPF (code protection fault)", + [EXCP_TICK] =3D "TICK (timer interrupt)", + [EXCP_ALIGN] =3D "ALIGN", + [EXCP_ILLEGAL] =3D "ILLEGAL", + [EXCP_INT] =3D "INT (device interrupt)", + [EXCP_DTLBMISS] =3D "DTLBMISS (data tlb miss)", + [EXCP_ITLBMISS] =3D "ITLBMISS (code tlb miss)", + [EXCP_RANGE] =3D "RANGE", + [EXCP_SYSCALL] =3D "SYSCALL", + [EXCP_FPE] =3D "FPE", + [EXCP_TRAP] =3D "TRAP", + }; + + qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]); + + hwaddr vect_pc =3D exception << 8; if (env->cpucfgr & CPUCFGR_EVBARP) { vect_pc |=3D env->evbar; } @@ -70,7 +90,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) } env->pc =3D vect_pc; } else { - cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", exception); } #endif =20 --=20 2.17.1