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[98.147.121.51]) by smtp.gmail.com with ESMTPSA id i65-v6sm49457254pfd.17.2018.06.18.11.41.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jun 2018 11:41:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S79sZyivBkNyL4H4hbuunUzlbblK48JMQIvgdjiIie8=; b=i8Af3oZGml6nYFyGmIT1kpMRDc2XovuLKUbvFdHG8nc+IlNeNZbZuecNTIQNX0G/XG xLVJUSV4ILU+Y2bFdBK4TPFPvRfEK8RaCOb3ljSGZWOnUEf8VRAiRFV8+tFJFuxx3RvN ATwvYDR1kCHLjGyT4ZnOhfYeFMTR2G8eVb4fo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S79sZyivBkNyL4H4hbuunUzlbblK48JMQIvgdjiIie8=; b=ZC29pvjMhC9KjcyRsafD5S0KItJUO8Hx8qbGB8sb3MxZigyI8AZOL9J5B+OsXkkfwG TBMxzCjNabU/kfoB/wPPToB4bGphhcv8y+WZD9P+U0VrboK9mjncw/R/BysrIt81EP/6 REGD1SlluIEtwJ6Vs1bEHJunuGOM1XvORkCUCczwi+/VIeKTpX4PcexoUGeppkYu2kZo 2mqGdRN5cgW6Z3cKF0vV9eR5GWB/lMb3OI3ds3HmSquXbkd6n5Rkz0JbFOZVpTOXY5D+ BnIV7ARBOKV1thjL1wTitXCUsalNrXuS3qia7Tk64DDxbT5lj3V+TsfLoVTn2eSp7M1Y +j9Q== X-Gm-Message-State: APt69E1YPXYj1M3uk8KqBD3kRqDnVmjboPh8SuVDD+0bZpXu+tJYQZza ZZtS6LtX/HBR3mHGfwslwV/c7KySJpw= X-Google-Smtp-Source: ADUXVKKv8nvctFl6HNYF6o4nXOwlkB1dQx2BT4U/J9Lmvv1/vJkZ+VY8TpwPUUPFksgEZ4edsCYfOg== X-Received: by 2002:a62:993:: with SMTP id 19-v6mr3338238pfj.105.1529347275324; Mon, 18 Jun 2018 11:41:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Jun 2018 08:40:38 -1000 Message-Id: <20180618184046.6270-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180618184046.6270-1-richard.henderson@linaro.org> References: <20180618184046.6270-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PATCH v2 14/22] target/openrisc: Use identical sizes for ITLB and DTLB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 The sizes are already the same, however, we can improve things if they are identical by design. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 10 ++++------ target/openrisc/machine.c | 4 ++-- target/openrisc/mmu.c | 4 ++-- target/openrisc/sys_helper.c | 16 ++++++++-------- 4 files changed, 16 insertions(+), 18 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index c48802ad8f..53abe965e8 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,10 +222,8 @@ enum { =20 /* TLB size */ enum { - DTLB_SIZE =3D 64, - DTLB_MASK =3D (DTLB_SIZE-1), - ITLB_SIZE =3D 64, - ITLB_MASK =3D (ITLB_SIZE-1), + TLB_SIZE =3D 64, + TLB_MASK =3D TLB_SIZE - 1, }; =20 /* TLB prot */ @@ -254,8 +252,8 @@ typedef struct OpenRISCTLBEntry { =20 #ifndef CONFIG_USER_ONLY typedef struct CPUOpenRISCTLBContext { - OpenRISCTLBEntry itlb[ITLB_SIZE]; - OpenRISCTLBEntry dtlb[DTLB_SIZE]; + OpenRISCTLBEntry itlb[TLB_SIZE]; + OpenRISCTLBEntry dtlb[TLB_SIZE]; =20 int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, hwaddr *physical, diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index b795b56dc6..3fc837b925 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -42,9 +42,9 @@ static const VMStateDescription vmstate_cpu_tlb =3D { .minimum_version_id =3D 1, .minimum_version_id_old =3D 1, .fields =3D (VMStateField[]) { - VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, ITLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), - VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, DTLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), VMSTATE_END_OF_LIST() } diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index b293b64e98..a4613e9ae4 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -41,7 +41,7 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physic= al, int *prot, target_ulong address, int rw, bool supervisor) { int vpn =3D address >> TARGET_PAGE_BITS; - int idx =3D vpn & ITLB_MASK; + int idx =3D vpn & TLB_MASK; int right =3D 0; uint32_t mr =3D cpu->env.tlb.itlb[idx].mr; uint32_t tr =3D cpu->env.tlb.itlb[idx].tr; @@ -74,7 +74,7 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physic= al, int *prot, target_ulong address, int rw, bool supervisor) { int vpn =3D address >> TARGET_PAGE_BITS; - int idx =3D vpn & DTLB_MASK; + int idx =3D vpn & TLB_MASK; int right =3D 0; uint32_t mr =3D cpu->env.tlb.dtlb[idx].mr; uint32_t tr =3D cpu->env.tlb.dtlb[idx].tr; diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 0a74c9522f..7254aa9830 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -79,7 +79,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong sp= r, target_ulong rb) idx =3D (spr - 1024); env->shadow_gpr[idx / 32][idx % 32] =3D rb; =20 - case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ + case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-1= 27 */ idx =3D spr - TO_SPR(1, 512); mr =3D env->tlb.dtlb[idx].mr; if (mr & 1) { @@ -90,7 +90,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong sp= r, target_ulong rb) } env->tlb.dtlb[idx].mr =3D rb; break; - case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 = */ + case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-1= 27 */ idx =3D spr - TO_SPR(1, 640); env->tlb.dtlb[idx].tr =3D rb; break; @@ -102,7 +102,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong = spr, target_ulong rb) case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ break; =20 - case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-12= 7 */ + case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-1= 27 */ idx =3D spr - TO_SPR(2, 512); mr =3D env->tlb.itlb[idx].mr; if (mr & 1) { @@ -113,7 +113,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong = spr, target_ulong rb) } env->tlb.itlb[idx].mr =3D rb; break; - case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 = */ + case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-1= 27 */ idx =3D spr - TO_SPR(2, 640); env->tlb.itlb[idx].tr =3D rb; break; @@ -246,11 +246,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, tar= get_ulong rd, idx =3D (spr - 1024); return env->shadow_gpr[idx / 32][idx % 32]; =20 - case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ + case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-1= 27 */ idx =3D spr - TO_SPR(1, 512); return env->tlb.dtlb[idx].mr; =20 - case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 = */ + case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-1= 27 */ idx =3D spr - TO_SPR(1, 640); return env->tlb.dtlb[idx].tr; =20 @@ -262,11 +262,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, tar= get_ulong rd, case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ break; =20 - case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 = */ + case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-1= 27 */ idx =3D spr - TO_SPR(2, 512); return env->tlb.itlb[idx].mr; =20 - case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 = */ + case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-1= 27 */ idx =3D spr - TO_SPR(2, 640); return env->tlb.itlb[idx].tr; =20 --=20 2.17.1