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[98.147.121.51]) by smtp.gmail.com with ESMTPSA id i65-v6sm49457254pfd.17.2018.06.18.11.41.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jun 2018 11:41:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5z97SVwjEk4sNEX969oQIopbF5FDZsjnXfc9pzcx1EA=; b=Vr311plRX3TPKnnVInCjrFVf38k55izZuRJGEMcpiUwohS30IMoZiErXwym1xaZcRm r0jFdao+3f2n8FyzSBVXnRVbdT2bdb/uMS1CuIQqokxStsx0lzS6KjN6MfIFN0ZqNEha +vk6GkuCqfH3Otz3Isbg+vCYaXdlCM6W1VjvU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5z97SVwjEk4sNEX969oQIopbF5FDZsjnXfc9pzcx1EA=; b=Q6N8jQUV8/sO4sOUCYoK3MT1HB4qHJaYY1cK398fd9YcXKKCPfWVEgPqvR3E6WfjAM R6krVkMR0RKfEi8j+RSWXjM04ehVE6XKDyWjD65t4gfPq0Fh8I2U/FgBabhvKy1gRLc6 W/h4nHqXLLLPu8Vb90rlASPu7Q1kad2PHVVXh8oA3B1+qY05/0XtrL1OhVzpje7rFmQj jWUnydWUMePIUHS527pNIpngr1CaJv46DgR0lhZQgKS+fekKWfKUpPaIufO73ZinN3q9 myPpj+qs2/+AUTB8M7PWm9xvhCmYX77KVcFiTk87pbCE86tA/OTMNyfwrwzYe6D0S7aI bXkg== X-Gm-Message-State: APt69E3pTc+lP5Bz2v7g/MME6yJ7qV4MN0mfeM1E6Qr5QWj3RIxp+IVa cft4OW5caGqoB/16gHLTVeXoVhhd5M8= X-Google-Smtp-Source: ADUXVKL6mAsST7zSJwMDyunba6cjlQWh0lhRv/CY0ocNwaFnXqR7Hg0qpZgKvYNFXplLoWnV7KOAIg== X-Received: by 2002:a17:902:70ca:: with SMTP id l10-v6mr2332822plt.174.1529347272034; Mon, 18 Jun 2018 11:41:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Jun 2018 08:40:36 -1000 Message-Id: <20180618184046.6270-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180618184046.6270-1-richard.henderson@linaro.org> References: <20180618184046.6270-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::233 Subject: [Qemu-devel] [PATCH v2 12/22] target/openrisc: Fix tlb flushing in mtspr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The previous code was confused, avoiding the flush of the old entry if the new entry is invalid. We need to flush the old page if the old entry is valid and the new page if the new entry is valid. This bug was masked by over-flushing elsewhere. Signed-off-by: Richard Henderson --- target/openrisc/sys_helper.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 8ad7a7d898..e00aaa332e 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -32,6 +32,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong sp= r, target_ulong rb) #ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); CPUState *cs =3D CPU(cpu); + target_ulong mr; int idx; =20 switch (spr) { @@ -84,12 +85,15 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong = spr, target_ulong rb) =20 case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); - if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK); + mr =3D env->tlb.dtlb[idx].mr; + if (mr & 1) { + tlb_flush_page(cs, mr & TARGET_PAGE_MASK); + } + if (rb & 1) { + tlb_flush_page(cs, rb & TARGET_PAGE_MASK); } env->tlb.dtlb[idx].mr =3D rb; break; - case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 = */ idx =3D spr - TO_SPR(1, 640); env->tlb.dtlb[idx].tr =3D rb; @@ -101,14 +105,18 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulon= g spr, target_ulong rb) case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ break; + case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-12= 7 */ idx =3D spr - TO_SPR(2, 512); - if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK); + mr =3D env->tlb.itlb[idx].mr; + if (mr & 1) { + tlb_flush_page(cs, mr & TARGET_PAGE_MASK); + } + if (rb & 1) { + tlb_flush_page(cs, rb & TARGET_PAGE_MASK); } env->tlb.itlb[idx].mr =3D rb; break; - case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 = */ idx =3D spr - TO_SPR(2, 640); env->tlb.itlb[idx].tr =3D rb; @@ -120,6 +128,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong = spr, target_ulong rb) case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ break; + case TO_SPR(5, 1): /* MACLO */ env->mac =3D deposit64(env->mac, 0, 32, rb); break; --=20 2.17.1