From nobody Tue Feb 10 10:04:21 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1529333393806434.60512233077725; Mon, 18 Jun 2018 07:49:53 -0700 (PDT) Received: from localhost ([::1]:35162 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fUvTT-0007Yj-S7 for importer@patchew.org; Mon, 18 Jun 2018 10:49:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46383) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fUvS0-0006ou-Tb for qemu-devel@nongnu.org; Mon, 18 Jun 2018 10:48:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fUvRw-0004kw-4R for qemu-devel@nongnu.org; Mon, 18 Jun 2018 10:48:12 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:37330 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fUvRv-0004km-U4; Mon, 18 Jun 2018 10:48:08 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 62FC4818A6A2; Mon, 18 Jun 2018 14:48:07 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-240.ams2.redhat.com [10.36.117.240]) by smtp.corp.redhat.com (Postfix) with ESMTP id 956D42156880; Mon, 18 Jun 2018 14:48:05 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Mon, 18 Jun 2018 16:47:58 +0200 Message-Id: <20180618144800.555-3-david@redhat.com> In-Reply-To: <20180618144800.555-1-david@redhat.com> References: <20180618144800.555-1-david@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.6 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Mon, 18 Jun 2018 14:48:07 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Mon, 18 Jun 2018 14:48:07 +0000 (UTC) for IP:'10.11.54.6' DOMAIN:'int-mx06.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'david@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [PATCH v1 2/4] machine: factor out enforce_aligned_dimm into memory_device_align X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , "Michael S . Tsirkin" , David Hildenbrand , Alexander Graf , qemu-ppc@nongnu.org, Paolo Bonzini , Igor Mammedov , David Gibson , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We want to handle memory device address assignment without passing compatibility parameters ("*align"). As x86 and Power use different strategies to determine an alignment and we need clean support for compat handling, let's introduce an enum on the machine class level. This is the machine configuration on how to align memory devices in guest physical memory. The three introduced types represent what is being done on x86 and Power right now. Signed-off-by: David Hildenbrand --- hw/core/machine.c | 3 +++ hw/i386/pc.c | 13 +++++++------ hw/i386/pc_piix.c | 2 +- include/hw/boards.h | 13 +++++++++++++ include/hw/i386/pc.h | 3 --- 5 files changed, 24 insertions(+), 10 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index 617e5f8d75..d34b205125 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -531,6 +531,9 @@ static void machine_class_init(ObjectClass *oc, void *d= ata) mc->numa_mem_align_shift =3D 23; mc->numa_auto_assign_ram =3D numa_default_auto_assign_ram; =20 + /* Default: use memory region alignment as memory devices alignment */ + mc->memory_device_align =3D MEMORY_DEVICE_ALIGN_REGION; + object_class_property_add_str(oc, "accel", machine_get_accel, machine_set_accel, &error_abort); object_class_property_set_description(oc, "accel", diff --git a/hw/i386/pc.c b/hw/i386/pc.c index bf986baf91..04a97e89e7 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1331,6 +1331,7 @@ void pc_memory_init(PCMachineState *pcms, FWCfgState *fw_cfg; MachineState *machine =3D MACHINE(pcms); PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); + MachineClass *mc =3D MACHINE_GET_CLASS(machine); =20 assert(machine->ram_size =3D=3D pcms->below_4g_mem_size + pcms->above_4g_mem_size); @@ -1363,8 +1364,6 @@ void pc_memory_init(PCMachineState *pcms, if (!pcmc->has_reserved_memory && (machine->ram_slots || (machine->maxram_size > machine->ram_size))) { - MachineClass *mc =3D MACHINE_GET_CLASS(machine); - error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", mc->name); exit(EXIT_FAILURE); @@ -1394,7 +1393,7 @@ void pc_memory_init(PCMachineState *pcms, machine->device_memory->base =3D ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); =20 - if (pcmc->enforce_aligned_dimm) { + if (mc->memory_device_align !=3D MEMORY_DEVICE_ALIGN_PAGE) { /* size device region assuming 1G page max alignment per slot = */ device_mem_size +=3D (1ULL << 30) * machine->ram_slots; } @@ -1705,14 +1704,16 @@ static void pc_memory_plug(HotplugHandler *hotplug_= dev, HotplugHandlerClass *hhc; Error *local_err =3D NULL; PCMachineState *pcms =3D PC_MACHINE(hotplug_dev); - PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); + MachineClass *mc =3D MACHINE_GET_CLASS(hotplug_dev); PCDIMMDevice *dimm =3D PC_DIMM(dev); PCDIMMDeviceClass *ddc =3D PC_DIMM_GET_CLASS(dimm); MemoryRegion *mr =3D ddc->get_memory_region(dimm, &error_abort); uint64_t align =3D TARGET_PAGE_SIZE; bool is_nvdimm =3D object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); =20 - if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) { + + if (memory_region_get_alignment(mr) && + mc->memory_device_align !=3D MEMORY_DEVICE_ALIGN_PAGE) { align =3D memory_region_get_alignment(mr); } =20 @@ -2374,7 +2375,6 @@ static void pc_machine_class_init(ObjectClass *oc, vo= id *data) pcmc->gigabyte_align =3D true; pcmc->has_reserved_memory =3D true; pcmc->kvmclock_enabled =3D true; - pcmc->enforce_aligned_dimm =3D true; /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K rep= orted * to be used at the moment, 32K should be enough for a while. */ pcmc->acpi_data_size =3D 0x20000 + 0x8000; @@ -2398,6 +2398,7 @@ static void pc_machine_class_init(ObjectClass *oc, vo= id *data) hc->unplug =3D pc_machine_device_unplug_cb; nc->nmi_monitor_handler =3D x86_nmi; mc->default_cpu_type =3D TARGET_DEFAULT_CPU_TYPE; + mc->memory_device_align =3D MEMORY_DEVICE_ALIGN_REGION_OR_PAGE; =20 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", pc_machine_get_device_memory_region_size, NULL, diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 3b87f3cedb..cc11856c24 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -566,7 +566,7 @@ static void pc_i440fx_2_1_machine_options(MachineClass = *m) m->default_display =3D NULL; SET_MACHINE_COMPAT(m, PC_COMPAT_2_1); pcmc->smbios_uuid_encoded =3D false; - pcmc->enforce_aligned_dimm =3D false; + m->memory_device_align =3D MEMORY_DEVICE_ALIGN_PAGE; } =20 DEFINE_I440FX_MACHINE(v2_1, "pc-i440fx-2.1", pc_compat_2_1, diff --git a/include/hw/boards.h b/include/hw/boards.h index ef7457f5dd..3f151207c1 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -105,6 +105,15 @@ typedef struct { CPUArchId cpus[0]; } CPUArchIdList; =20 +typedef enum MemoryDeviceAlign { + /* use specified memory region alignment */ + MEMORY_DEVICE_ALIGN_REGION =3D 0, + /* use target page size as alignment */ + MEMORY_DEVICE_ALIGN_PAGE, + /* use target page size if no memory region alignment has been specifi= ed */ + MEMORY_DEVICE_ALIGN_REGION_OR_PAGE, +} MemoryDeviceAlign; + /** * MachineClass: * @max_cpus: maximum number of CPUs supported. Default: 1 @@ -156,6 +165,9 @@ typedef struct { * should instead use "unimplemented-device" for all memory ranges where * the guest will attempt to probe for a device that QEMU doesn't * implement and a stub device is required. + * @memory_device_align: The alignment that will be used as default when + * searching for a guest physical memory address while plugging a + * memory device. This is relevant for compatibility handling. */ struct MachineClass { /*< private >*/ @@ -202,6 +214,7 @@ struct MachineClass { const char **valid_cpu_types; strList *allowed_dynamic_sysbus_devices; bool auto_enable_numa_with_memhp; + MemoryDeviceAlign memory_device_align; void (*numa_auto_assign_ram)(MachineClass *mc, NodeInfo *nodes, int nb_nodes, ram_addr_t size); =20 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index fc8dedca12..ffb4654fc8 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -86,8 +86,6 @@ struct PCMachineState { * * Compat fields: * - * @enforce_aligned_dimm: check that DIMM's address/size is aligned by - * backend's alignment value if provided * @acpi_data_size: Size of the chunk of memory at the top of RAM * for the BIOS ACPI tables and other BIOS * datastructures. @@ -124,7 +122,6 @@ struct PCMachineClass { /* RAM / address space compat: */ bool gigabyte_align; bool has_reserved_memory; - bool enforce_aligned_dimm; bool broken_reserved_end; =20 /* TSC rate migration: */ --=20 2.17.1