From nobody Tue Feb 10 10:20:57 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528878724644532.8594315356812; Wed, 13 Jun 2018 01:32:04 -0700 (PDT) Received: from localhost ([::1]:60675 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fT1CF-0001mv-QF for importer@patchew.org; Wed, 13 Jun 2018 04:32:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52947) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fT1Am-00013q-1v for qemu-devel@nongnu.org; Wed, 13 Jun 2018 04:30:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fT1Ak-0003eh-7n for qemu-devel@nongnu.org; Wed, 13 Jun 2018 04:30:31 -0400 Received: from chuckie.co.uk ([82.165.15.123]:59847 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fT1Ak-0003dX-00; Wed, 13 Jun 2018 04:30:30 -0400 Received: from host86-191-128-6.range86-191.btcentralplus.com ([86.191.128.6] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1fT1Aw-0002OB-Sy; Wed, 13 Jun 2018 09:30:43 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, lvivier@redhat.com, david@gibson.dropbear.id.au Date: Wed, 13 Jun 2018 09:30:15 +0100 Message-Id: <20180613083015.15749-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180613083015.15749-1-mark.cave-ayland@ilande.co.uk> References: <20180613083015.15749-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.191.128.6 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 3/3] mos6522: expose mos6522_update_irq() through MOS6522DeviceClass X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In the case where we have an interrupt generated externally from inputs to bits 1 and 2 of port A and/or port B, it is necessary to expose mos6522_update_irq() so it can be called by the interrupt source. Signed-off-by: Mark Cave-Ayland --- hw/misc/mos6522.c | 1 + include/hw/misc/mos6522.h | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 8d5b419825..14cff26c61 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -463,6 +463,7 @@ static void mos6522_class_init(ObjectClass *oc, void *d= ata) mdc->set_sr_int =3D mos6522_set_sr_int; mdc->portB_write =3D mos6522_portB_write; mdc->portA_write =3D mos6522_portA_write; + mdc->update_irq =3D mos6522_update_irq; mdc->get_timer1_counter_value =3D mos6522_get_counter_value; mdc->get_timer2_counter_value =3D mos6522_get_counter_value; mdc->get_timer1_load_time =3D mos6522_get_load_time; diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h index f52b41920b..03d9f0c059 100644 --- a/include/hw/misc/mos6522.h +++ b/include/hw/misc/mos6522.h @@ -134,6 +134,7 @@ typedef struct MOS6522DeviceClass { void (*set_sr_int)(MOS6522State *dev); void (*portB_write)(MOS6522State *dev); void (*portA_write)(MOS6522State *dev); + void (*update_irq)(MOS6522State *dev); /* These are used to influence the CUDA MacOS timebase calibration */ uint64_t (*get_timer1_counter_value)(MOS6522State *dev, MOS6522Timer *= ti); uint64_t (*get_timer2_counter_value)(MOS6522State *dev, MOS6522Timer *= ti); --=20 2.11.0