From nobody Tue Apr 16 13:48:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528873310163801.4004355868474; Wed, 13 Jun 2018 00:01:50 -0700 (PDT) Received: from localhost ([::1]:60281 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSzmv-00068r-FX for importer@patchew.org; Wed, 13 Jun 2018 03:01:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34121) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSziY-0002vK-0Q for qemu-devel@nongnu.org; Wed, 13 Jun 2018 02:57:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fSziX-0006Wc-4Q for qemu-devel@nongnu.org; Wed, 13 Jun 2018 02:57:18 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:43575) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fSziW-0006U8-Df; Wed, 13 Jun 2018 02:57:17 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 415HcS62wQz9s19; Wed, 13 Jun 2018 16:57:12 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1528873032; bh=t2SKai8hWx1czkdeYdLk+xxLSH1sTqiUrSBWJLLoUtw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XuD5oH2ibWk+eXAILYtTCylMw9CwG112J/wTPxOQxpKT9oA3ConRbVvqna9LVFtnV TkKIRiCfQkPExRvO8e5vdiKwDr9CCjovmTwP2K9HFWK6juqtOY0rnhM3bpTtju+qlQ U+Lvdbhy57Q7K88twW4SxLY+eB0Xaiur4ozz7rSk= From: David Gibson To: groug@kaod.org Date: Wed, 13 Jun 2018 16:57:01 +1000 Message-Id: <20180613065707.30766-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180613065707.30766-1-david@gibson.dropbear.id.au> References: <20180613065707.30766-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PATCH 1/7] spapr: Clean up cpu realize/unrealize paths X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, clg@kaod.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" spapr_cpu_init() and spapr_cpu_destroy() are only called from the spapr cpu core realize/unrealize paths, and really can only be called from there. Those are all short functions, so fold the pairs together for simplicity. While we're there rename some functions and change some parameter types for brevity and clarity. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/spapr_cpu_core.c | 69 +++++++++++++++-------------------------- 1 file changed, 25 insertions(+), 44 deletions(-) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index f3e9b879b2..7fdb3b6667 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -83,26 +83,6 @@ void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_u= long nip, target_ulong r ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); } =20 -static void spapr_cpu_destroy(PowerPCCPU *cpu) -{ - qemu_unregister_reset(spapr_cpu_reset, cpu); -} - -static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, - Error **errp) -{ - CPUPPCState *env =3D &cpu->env; - - /* Set time-base frequency to 512 MHz */ - cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); - - cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); - kvmppc_set_papr(cpu); - - qemu_register_reset(spapr_cpu_reset, cpu); - spapr_cpu_reset(cpu); -} - /* * Return the sPAPR CPU core type for @model which essentially is the CPU * model specified with -cpu cmdline option. @@ -122,44 +102,47 @@ const char *spapr_get_cpu_core_type(const char *cpu_t= ype) return object_class_get_name(oc); } =20 -static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp) +static void spapr_unrealize_vcpu(PowerPCCPU *cpu) +{ + qemu_unregister_reset(spapr_cpu_reset, cpu); + object_unparent(cpu->intc); + cpu_remove_sync(CPU(cpu)); + object_unparent(OBJECT(cpu)); +} + +static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp) { sPAPRCPUCore *sc =3D SPAPR_CPU_CORE(OBJECT(dev)); CPUCore *cc =3D CPU_CORE(dev); int i; =20 for (i =3D 0; i < cc->nr_threads; i++) { - Object *obj =3D OBJECT(sc->threads[i]); - DeviceState *dev =3D DEVICE(obj); - CPUState *cs =3D CPU(dev); - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - - spapr_cpu_destroy(cpu); - object_unparent(cpu->intc); - cpu_remove_sync(cs); - object_unparent(obj); + spapr_unrealize_vcpu(sc->threads[i]); } g_free(sc->threads); } =20 -static void spapr_cpu_core_realize_child(Object *child, - sPAPRMachineState *spapr, Error *= *errp) +static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr, + Error **errp) { + CPUPPCState *env =3D &cpu->env; Error *local_err =3D NULL; - CPUState *cs =3D CPU(child); - PowerPCCPU *cpu =3D POWERPC_CPU(cs); =20 - object_property_set_bool(child, true, "realized", &local_err); + object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); if (local_err) { goto error; } =20 - spapr_cpu_init(spapr, cpu, &local_err); - if (local_err) { - goto error; - } + /* Set time-base frequency to 512 MHz */ + cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); + + cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); + kvmppc_set_papr(cpu); =20 - cpu->intc =3D icp_create(child, spapr->icp_type, XICS_FABRIC(spapr), + qemu_register_reset(spapr_cpu_reset, cpu); + spapr_cpu_reset(cpu); + + cpu->intc =3D icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spa= pr), &local_err); if (local_err) { goto error; @@ -220,9 +203,7 @@ static void spapr_cpu_core_realize(DeviceState *dev, Er= ror **errp) } =20 for (j =3D 0; j < cc->nr_threads; j++) { - obj =3D OBJECT(sc->threads[j]); - - spapr_cpu_core_realize_child(obj, spapr, &local_err); + spapr_realize_vcpu(sc->threads[j], spapr, &local_err); if (local_err) { goto err; } @@ -249,7 +230,7 @@ static void spapr_cpu_core_class_init(ObjectClass *oc, = void *data) sPAPRCPUCoreClass *scc =3D SPAPR_CPU_CORE_CLASS(oc); =20 dc->realize =3D spapr_cpu_core_realize; - dc->unrealize =3D spapr_cpu_core_unrealizefn; + dc->unrealize =3D spapr_cpu_core_unrealize; dc->props =3D spapr_cpu_core_properties; scc->cpu_type =3D data; } --=20 2.17.1 From nobody Tue Apr 16 13:48:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528873215071109.23045991037861; Wed, 13 Jun 2018 00:00:15 -0700 (PDT) Received: from localhost ([::1]:60263 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSzlE-0004ni-TG for importer@patchew.org; Wed, 13 Jun 2018 03:00:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34110) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSziX-0002vI-R7 for qemu-devel@nongnu.org; Wed, 13 Jun 2018 02:57:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fSziX-0006WR-1f for qemu-devel@nongnu.org; Wed, 13 Jun 2018 02:57:17 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:45089) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fSziW-0006UB-IL; Wed, 13 Jun 2018 02:57:16 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 415HcT0pjPz9s3C; Wed, 13 Jun 2018 16:57:12 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1528873033; bh=scMHodrsEvLAF619NVIY0xkWrwzTvHqzanOAQ/RLvOo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VVV9QlPwFjUIY3G35CRef0e/j6XH7BMweT7m8rQM55klUGkJrLtAgEWQUw9yzpjrz AFVpFFEZ1pEaKdFkq3hUOZwblOSBL1OibSrJP6/ntsWRWCpycnHNk8kxMufTynbrOG +a6fcbyW4yhRC4YF5VPYUCVYe/ngw2HrfJU0NIg0= From: David Gibson To: groug@kaod.org Date: Wed, 13 Jun 2018 16:57:02 +1000 Message-Id: <20180613065707.30766-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180613065707.30766-1-david@gibson.dropbear.id.au> References: <20180613065707.30766-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PATCH 2/7] pnv: Add missing error check during cpu realize() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, clg@kaod.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In pnv_core_realize() we call two functions with an Error * parameter in succession, which means if they both cause errors we'll lose the first one. Add an extra test/escape to fix this. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/pnv_core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 13ad7d9e04..efb68226bb 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -173,6 +173,9 @@ static void pnv_core_realize(DeviceState *dev, Error **= errp) =20 snprintf(name, sizeof(name), "thread[%d]", i); object_property_add_child(OBJECT(pc), name, obj, &local_err); + if (local_err) { + goto err; + } object_property_add_alias(obj, "core-pir", OBJECT(pc), "pir", &local_err); if (local_err) { --=20 2.17.1 From nobody Tue Apr 16 13:48:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528873387226301.63290484516597; Wed, 13 Jun 2018 00:03:07 -0700 (PDT) Received: from localhost ([::1]:60284 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSzo6-00073b-FO for importer@patchew.org; Wed, 13 Jun 2018 03:03:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34232) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSzib-0002wm-UY for qemu-devel@nongnu.org; Wed, 13 Jun 2018 02:57:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fSziX-0006Wx-C5 for qemu-devel@nongnu.org; Wed, 13 Jun 2018 02:57:22 -0400 Received: from ozlabs.org ([203.11.71.1]:33007) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fSziW-0006UR-OW; Wed, 13 Jun 2018 02:57:17 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 415HcT3Nxmz9s4r; Wed, 13 Jun 2018 16:57:12 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1528873033; bh=GpJhVqH3OHi9XCnRZWSCpHorBZhTL5XkeY4HedC0NxE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f21RFyyCj+Z41v1d7lcZqt8knAy+San5eHNZTMeF3pPYmhcQKUgIOrUx99CRAY4C7 SEAl/E68xC+PkavjsDT+jS6COvducWLvHuR/cf/zWci6YgxI06e9TniBUW49equD0f jipIiWv6lUxo9qftOdArPkBkeJkUZ7tuEX0Nsej4= From: David Gibson To: groug@kaod.org Date: Wed, 13 Jun 2018 16:57:03 +1000 Message-Id: <20180613065707.30766-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180613065707.30766-1-david@gibson.dropbear.id.au> References: <20180613065707.30766-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PATCH 3/7] pnv_core: Allocate cpu thread objects individually X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, clg@kaod.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently, we allocate space for all the cpu objects within a single core in one big block. This was copied from an older version of the spapr code and requires some ugly pointer manipulation to extract the individual objects. This design was due to a misunderstanding of qemu lifetime conventions and has already been changed in spapr (in 94ad93bd "spapr_cpu_core: instantiate CPUs separately". Make an equivalent change in pnv_core to get rid of the nasty pointer arithmetic. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/pnv.c | 4 ++-- hw/ppc/pnv_core.c | 11 +++++------ include/hw/ppc/pnv_core.h | 2 +- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0314881316..0b9508d94d 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -121,9 +121,9 @@ static int get_cpus_node(void *fdt) */ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) { - CPUState *cs =3D CPU(DEVICE(pc->threads)); + PowerPCCPU *cpu =3D pc->threads[0]; + CPUState *cs =3D CPU(cpu); DeviceClass *dc =3D DEVICE_GET_CLASS(cs); - PowerPCCPU *cpu =3D POWERPC_CPU(cs); int smt_threads =3D CPU_CORE(pc)->nr_threads; CPUPPCState *env =3D &cpu->env; PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cs); diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index efb68226bb..59309e149c 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -151,7 +151,6 @@ static void pnv_core_realize(DeviceState *dev, Error **= errp) PnvCore *pc =3D PNV_CORE(OBJECT(dev)); CPUCore *cc =3D CPU_CORE(OBJECT(dev)); const char *typename =3D pnv_core_cpu_typename(pc); - size_t size =3D object_type_get_instance_size(typename); Error *local_err =3D NULL; void *obj; int i, j; @@ -165,11 +164,11 @@ static void pnv_core_realize(DeviceState *dev, Error = **errp) return; } =20 - pc->threads =3D g_malloc0(size * cc->nr_threads); + pc->threads =3D g_new(PowerPCCPU *, cc->nr_threads); for (i =3D 0; i < cc->nr_threads; i++) { - obj =3D pc->threads + i * size; + obj =3D object_new(typename); =20 - object_initialize(obj, size, typename); + pc->threads[i] =3D POWERPC_CPU(obj); =20 snprintf(name, sizeof(name), "thread[%d]", i); object_property_add_child(OBJECT(pc), name, obj, &local_err); @@ -185,7 +184,7 @@ static void pnv_core_realize(DeviceState *dev, Error **= errp) } =20 for (j =3D 0; j < cc->nr_threads; j++) { - obj =3D pc->threads + j * size; + obj =3D OBJECT(pc->threads[j]); =20 pnv_core_realize_child(obj, XICS_FABRIC(xi), &local_err); if (local_err) { @@ -200,7 +199,7 @@ static void pnv_core_realize(DeviceState *dev, Error **= errp) =20 err: while (--i >=3D 0) { - obj =3D pc->threads + i * size; + obj =3D OBJECT(pc->threads[i]); object_unparent(obj); } g_free(pc->threads); diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index e337af7a3a..447ae761f7 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -34,7 +34,7 @@ typedef struct PnvCore { CPUCore parent_obj; =20 /*< public >*/ - void *threads; + PowerPCCPU **threads; uint32_t pir; =20 MemoryRegion xscom_regs; --=20 2.17.1 From nobody Tue Apr 16 13:48:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528873152221586.1456819057969; Tue, 12 Jun 2018 23:59:12 -0700 (PDT) Received: from localhost ([::1]:60262 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSzkN-00040m-FL for importer@patchew.org; Wed, 13 Jun 2018 02:59:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34130) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSziY-0002vM-Be for qemu-devel@nongnu.org; Wed, 13 Jun 2018 02:57:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fSziX-0006Ws-BW for qemu-devel@nongnu.org; Wed, 13 Jun 2018 02:57:18 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:36437) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fSziW-0006UP-LJ; Wed, 13 Jun 2018 02:57:17 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 415HcT2Cxzz9s4Y; Wed, 13 Jun 2018 16:57:13 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1528873033; bh=Sy3HVi8nvjgEZnza88h/d1ip4GgQasewWRrWDM/NyYI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d3Si2SWz/nW6k2b3xI2zstFzJQblYkhRUpS6GOWuPgIEdVs5jIb3YVdv6/QovNkqX NbtNko7Pa2wzizagDdjuhIoJAykWpgz8RaOZw4k4qk+qY1mdUIrDJHwLNVREd3/TyB aHHxlN6A9C7RzJ8ZkegNW3NS0vavu+ofKVYA1NII= From: David Gibson To: groug@kaod.org Date: Wed, 13 Jun 2018 16:57:04 +1000 Message-Id: <20180613065707.30766-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180613065707.30766-1-david@gibson.dropbear.id.au> References: <20180613065707.30766-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PATCH 4/7] pnv: Clean up cpu realize path X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, clg@kaod.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" pnv_cpu_init() is only called from the the pnv cpu core realize path, and really only can be called from there. So fold it into its caller, which we also rename for brevity. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/pnv_core.c | 56 ++++++++++++++++++----------------------------- 1 file changed, 21 insertions(+), 35 deletions(-) diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 59309e149c..c9648fd1ad 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -54,28 +54,6 @@ static void pnv_cpu_reset(void *opaque) env->msr |=3D MSR_HVB; /* Hypervisor mode */ } =20 -static void pnv_cpu_init(PowerPCCPU *cpu, Error **errp) -{ - CPUPPCState *env =3D &cpu->env; - int core_pir; - int thread_index =3D 0; /* TODO: TCG supports only one thread */ - ppc_spr_t *pir =3D &env->spr_cb[SPR_PIR]; - - core_pir =3D object_property_get_uint(OBJECT(cpu), "core-pir", &error_= abort); - - /* - * The PIR of a thread is the core PIR + the thread index. We will - * need to find a way to get the thread index when TCG supports - * more than 1. We could use the object name ? - */ - pir->default_value =3D core_pir + thread_index; - - /* Set time-base frequency to 512 MHz */ - cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); - - qemu_register_reset(pnv_cpu_reset, cpu); -} - /* * These values are read by the PowerNV HW monitors under Linux */ @@ -121,29 +99,39 @@ static const MemoryRegionOps pnv_core_xscom_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **= errp) +static void pnv_realize_vcpu(PowerPCCPU *cpu, XICSFabric *xi, Error **errp) { + CPUPPCState *env =3D &cpu->env; + int core_pir; + int thread_index =3D 0; /* TODO: TCG supports only one thread */ + ppc_spr_t *pir =3D &env->spr_cb[SPR_PIR]; Error *local_err =3D NULL; - CPUState *cs =3D CPU(child); - PowerPCCPU *cpu =3D POWERPC_CPU(cs); =20 - object_property_set_bool(child, true, "realized", &local_err); + object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); if (local_err) { error_propagate(errp, local_err); return; } =20 - cpu->intc =3D icp_create(child, TYPE_PNV_ICP, xi, &local_err); + cpu->intc =3D icp_create(OBJECT(cpu), TYPE_PNV_ICP, xi, &local_err); if (local_err) { error_propagate(errp, local_err); return; } =20 - pnv_cpu_init(cpu, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } + core_pir =3D object_property_get_uint(OBJECT(cpu), "core-pir", &error_= abort); + + /* + * The PIR of a thread is the core PIR + the thread index. We will + * need to find a way to get the thread index when TCG supports + * more than 1. We could use the object name ? + */ + pir->default_value =3D core_pir + thread_index; + + /* Set time-base frequency to 512 MHz */ + cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); + + qemu_register_reset(pnv_cpu_reset, cpu); } =20 static void pnv_core_realize(DeviceState *dev, Error **errp) @@ -184,9 +172,7 @@ static void pnv_core_realize(DeviceState *dev, Error **= errp) } =20 for (j =3D 0; j < cc->nr_threads; j++) { - obj =3D OBJECT(pc->threads[j]); - - pnv_core_realize_child(obj, XICS_FABRIC(xi), &local_err); + pnv_realize_vcpu(pc->threads[j], XICS_FABRIC(xi), &local_err); if (local_err) { goto err; } --=20 2.17.1 From nobody Tue Apr 16 13:48:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528873308411304.1143290163934; Wed, 13 Jun 2018 00:01:48 -0700 (PDT) Received: from localhost ([::1]:60278 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSzmq-00063d-BS for importer@patchew.org; Wed, 13 Jun 2018 03:01:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34241) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSzic-0002xK-B3 for qemu-devel@nongnu.org; Wed, 13 Jun 2018 02:57:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fSziZ-0006a1-Rk for qemu-devel@nongnu.org; Wed, 13 Jun 2018 02:57:22 -0400 Received: from ozlabs.org ([203.11.71.1]:42469) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fSziZ-0006XE-FM; Wed, 13 Jun 2018 02:57:19 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 415HcT5Qntz9s5N; Wed, 13 Jun 2018 16:57:13 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1528873033; bh=VB7RM/qAOXmwnX8iVcTJRRAIeMF9Fr0+jIopit6BXxk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jPC6lkC3A9bNYsVN5V2HYR51WHdbmvLedMPgKxHaQN3+iEED4Iu1K3Ye2e3BE1ZeW GQ4DDBDin+/xU1JqGpPwNQ/cXV3iOzbe23Rnn7WbzrKV5HYUJXhoeiTgy6sNZD00aM qsFHgAKXlRJqpkz4dDyV4TLIqmPt1saiesALGQsU= From: David Gibson To: groug@kaod.org Date: Wed, 13 Jun 2018 16:57:05 +1000 Message-Id: <20180613065707.30766-6-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180613065707.30766-1-david@gibson.dropbear.id.au> References: <20180613065707.30766-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PATCH 5/7] pnv: Add cpu unrealize path X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, clg@kaod.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently we don't have any unrealize path for pnv cpu cores. We get away with this because we don't yet support cpu hotplug for pnv. However, we're going to want it eventually, and in the meantime, it makes it non-obvious why there are a bunch of allocations on the realize() path that don't have matching frees. So, implement the missing unrealize path. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/pnv_core.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index c9648fd1ad..c70dbbe056 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -192,6 +192,26 @@ err: error_propagate(errp, local_err); } =20 +static void pnv_unrealize_vcpu(PowerPCCPU *cpu) +{ + qemu_unregister_reset(pnv_cpu_reset, cpu); + object_unparent(cpu->intc); + cpu_remove_sync(CPU(cpu)); + object_unparent(OBJECT(cpu)); +} + +static void pnv_core_unrealize(DeviceState *dev, Error **errp) +{ + PnvCore *pc =3D PNV_CORE(dev); + CPUCore *cc =3D CPU_CORE(dev); + int i; + + for (i =3D 0; i < cc->nr_threads; i++) { + pnv_unrealize_vcpu(pc->threads[i]); + } + g_free(pc->threads); +} + static Property pnv_core_properties[] =3D { DEFINE_PROP_UINT32("pir", PnvCore, pir, 0), DEFINE_PROP_END_OF_LIST(), @@ -202,6 +222,7 @@ static void pnv_core_class_init(ObjectClass *oc, void *= data) DeviceClass *dc =3D DEVICE_CLASS(oc); =20 dc->realize =3D pnv_core_realize; + dc->unrealize =3D pnv_core_unrealize; dc->props =3D pnv_core_properties; } =20 --=20 2.17.1 From nobody Tue Apr 16 13:48:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152887353091984.84040375326413; Wed, 13 Jun 2018 00:05:30 -0700 (PDT) Received: from localhost ([::1]:60298 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSzqK-0000V6-R2 for importer@patchew.org; Wed, 13 Jun 2018 03:05:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34263) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSzid-0002ya-1o for qemu-devel@nongnu.org; Wed, 13 Jun 2018 02:57:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fSzia-0006aS-7o for qemu-devel@nongnu.org; Wed, 13 Jun 2018 02:57:23 -0400 Received: from ozlabs.org ([203.11.71.1]:33287) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fSziZ-0006XF-H7; Wed, 13 Jun 2018 02:57:20 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 415HcT4prgz9s4n; Wed, 13 Jun 2018 16:57:13 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1528873033; bh=o06TpuYP++LAGIt9OipAhRnVl1AyqX/NxRpsOeIATvs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X6/aI0lWNV9GN/HUT6K6Wmlw1WJGVKNpTKyjm9AlILYP7TiKolLsh/TC9U5KFkf9p ltjAy6tNoY9LffMWdaJ91l+wydDV5haLqOf6PplPxtUMQnsXNngx3qDGEAdateFsCO qVIc1oju4NI3ILCe2q/a5p319Hz94R+AG0qnMqiY= From: David Gibson To: groug@kaod.org Date: Wed, 13 Jun 2018 16:57:06 +1000 Message-Id: <20180613065707.30766-7-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180613065707.30766-1-david@gibson.dropbear.id.au> References: <20180613065707.30766-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PATCH 6/7] target/ppc: Replace intc pointer with a general machine_data pointer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, clg@kaod.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" PowerPCCPU contains an (Object *)intc used to point to the cpu's interrupt controller. Or more precisely to the "presentation" component of the interrupt controller relevant to this cpu. Really, this field is machine specific. The machines which use it can point it to different types of object depending on their needs, and most machines don't use it at all (since they have older style PICs which don't have per-cpu presentation components). There's also other information that's per-cpu, but platform/machine specific. So replace the intc pointer with a (void *)machine_data which can be managed as the machine type likes to conveniently store per cpu information. Signed-off-by: David Gibson Reviewed-by: Greg Kurz --- hw/intc/xics.c | 5 +++-- hw/intc/xics_spapr.c | 16 +++++++++++----- hw/ppc/pnv.c | 4 ++-- hw/ppc/pnv_core.c | 11 +++++++++-- hw/ppc/spapr.c | 8 ++++---- hw/ppc/spapr_cpu_core.c | 13 ++++++++++--- include/hw/ppc/pnv_core.h | 9 +++++++++ include/hw/ppc/spapr_cpu_core.h | 10 ++++++++++ include/hw/ppc/xics.h | 4 ++-- target/ppc/cpu.h | 2 +- 10 files changed, 61 insertions(+), 21 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index e73e623e3b..689ad44e5f 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -383,7 +383,8 @@ static const TypeInfo icp_info =3D { .class_size =3D sizeof(ICPStateClass), }; =20 -Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **= errp) +ICPState *icp_create(Object *cpu, const char *type, XICSFabric *xi, + Error **errp) { Error *local_err =3D NULL; Object *obj; @@ -401,7 +402,7 @@ Object *icp_create(Object *cpu, const char *type, XICSF= abric *xi, Error **errp) obj =3D NULL; } =20 - return obj; + return ICP(obj); } =20 /* diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 2e27b92b87..01c76717cf 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -31,6 +31,7 @@ #include "trace.h" #include "qemu/timer.h" #include "hw/ppc/spapr.h" +#include "hw/ppc/spapr_cpu_core.h" #include "hw/ppc/xics.h" #include "hw/ppc/fdt.h" #include "qapi/visitor.h" @@ -43,8 +44,9 @@ static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineS= tate *spapr, target_ulong opcode, target_ulong *args) { target_ulong cppr =3D args[0]; + sPAPRCPUState *spapr_cpu =3D spapr_cpu_state(cpu); =20 - icp_set_cppr(ICP(cpu->intc), cppr); + icp_set_cppr(spapr_cpu->icp, cppr); return H_SUCCESS; } =20 @@ -65,7 +67,8 @@ static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineSt= ate *spapr, static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { - uint32_t xirr =3D icp_accept(ICP(cpu->intc)); + sPAPRCPUState *spapr_cpu =3D spapr_cpu_state(cpu); + uint32_t xirr =3D icp_accept(spapr_cpu->icp); =20 args[0] =3D xirr; return H_SUCCESS; @@ -74,7 +77,8 @@ static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineS= tate *spapr, static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { - uint32_t xirr =3D icp_accept(ICP(cpu->intc)); + sPAPRCPUState *spapr_cpu =3D spapr_cpu_state(cpu); + uint32_t xirr =3D icp_accept(spapr_cpu->icp); =20 args[0] =3D xirr; args[1] =3D cpu_get_host_ticks(); @@ -84,9 +88,10 @@ static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachi= neState *spapr, static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { + sPAPRCPUState *spapr_cpu =3D spapr_cpu_state(cpu); target_ulong xirr =3D args[0]; =20 - icp_eoi(ICP(cpu->intc), xirr); + icp_eoi(spapr_cpu->icp, xirr); return H_SUCCESS; } =20 @@ -94,7 +99,8 @@ static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachine= State *spapr, target_ulong opcode, target_ulong *args) { uint32_t mfrr; - uint32_t xirr =3D icp_ipoll(ICP(cpu->intc), &mfrr); + sPAPRCPUState *spapr_cpu =3D spapr_cpu_state(cpu); + uint32_t xirr =3D icp_ipoll(spapr_cpu->icp, &mfrr); =20 args[0] =3D xirr; args[1] =3D mfrr; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0b9508d94d..3a36c6ac6a 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1013,7 +1013,7 @@ static ICPState *pnv_icp_get(XICSFabric *xi, int pir) { PowerPCCPU *cpu =3D ppc_get_vcpu_by_pir(pir); =20 - return cpu ? ICP(cpu->intc) : NULL; + return cpu ? pnv_cpu_state(cpu)->icp : NULL; } =20 static void pnv_pic_print_info(InterruptStatsProvider *obj, @@ -1026,7 +1026,7 @@ static void pnv_pic_print_info(InterruptStatsProvider= *obj, CPU_FOREACH(cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); =20 - icp_pic_print_info(ICP(cpu->intc), mon); + icp_pic_print_info(pnv_cpu_state(cpu)->icp, mon); } =20 for (i =3D 0; i < pnv->num_chips; i++) { diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index c70dbbe056..86448ade87 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -105,6 +105,7 @@ static void pnv_realize_vcpu(PowerPCCPU *cpu, XICSFabri= c *xi, Error **errp) int core_pir; int thread_index =3D 0; /* TODO: TCG supports only one thread */ ppc_spr_t *pir =3D &env->spr_cb[SPR_PIR]; + PnvCPUState *pnv_cpu; Error *local_err =3D NULL; =20 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); @@ -113,7 +114,9 @@ static void pnv_realize_vcpu(PowerPCCPU *cpu, XICSFabri= c *xi, Error **errp) return; } =20 - cpu->intc =3D icp_create(OBJECT(cpu), TYPE_PNV_ICP, xi, &local_err); + cpu->machine_data =3D pnv_cpu =3D g_new0(PnvCPUState, 1); + + pnv_cpu->icp =3D icp_create(OBJECT(cpu), TYPE_PNV_ICP, xi, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -194,8 +197,12 @@ err: =20 static void pnv_unrealize_vcpu(PowerPCCPU *cpu) { + PnvCPUState *pnv_cpu =3D pnv_cpu_state(cpu); + qemu_unregister_reset(pnv_cpu_reset, cpu); - object_unparent(cpu->intc); + object_unparent(OBJECT(pnv_cpu->icp)); + cpu->machine_data =3D NULL; + g_free(pnv_cpu); cpu_remove_sync(CPU(cpu)); object_unparent(OBJECT(cpu)); } diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f59999daac..cbab6b6b7e 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1745,8 +1745,8 @@ static int spapr_post_load(void *opaque, int version_= id) if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { CPUState *cs; CPU_FOREACH(cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - icp_resend(ICP(cpu->intc)); + sPAPRCPUState *spapr_cpu =3D spapr_cpu_state(POWERPC_CPU(cs)); + icp_resend(spapr_cpu->icp); } } =20 @@ -3783,7 +3783,7 @@ static ICPState *spapr_icp_get(XICSFabric *xi, int vc= pu_id) { PowerPCCPU *cpu =3D spapr_find_cpu(vcpu_id); =20 - return cpu ? ICP(cpu->intc) : NULL; + return cpu ? spapr_cpu_state(cpu)->icp : NULL; } =20 #define ICS_IRQ_FREE(ics, srcno) \ @@ -3925,7 +3925,7 @@ static void spapr_pic_print_info(InterruptStatsProvid= er *obj, CPU_FOREACH(cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); =20 - icp_pic_print_info(ICP(cpu->intc), mon); + icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon); } =20 ics_pic_print_info(spapr->ics, mon); diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 7fdb3b6667..544bda93e2 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -104,8 +104,12 @@ const char *spapr_get_cpu_core_type(const char *cpu_ty= pe) =20 static void spapr_unrealize_vcpu(PowerPCCPU *cpu) { + sPAPRCPUState *spapr_cpu =3D spapr_cpu_state(cpu); + qemu_unregister_reset(spapr_cpu_reset, cpu); - object_unparent(cpu->intc); + object_unparent(OBJECT(spapr_cpu->icp)); + cpu->machine_data =3D NULL; + g_free(spapr_cpu); cpu_remove_sync(CPU(cpu)); object_unparent(OBJECT(cpu)); } @@ -127,12 +131,15 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPR= MachineState *spapr, { CPUPPCState *env =3D &cpu->env; Error *local_err =3D NULL; + sPAPRCPUState *spapr_cpu; =20 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); if (local_err) { goto error; } =20 + spapr_cpu =3D cpu->machine_data =3D g_new0(sPAPRCPUState, 1); + /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); =20 @@ -142,8 +149,8 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMa= chineState *spapr, qemu_register_reset(spapr_cpu_reset, cpu); spapr_cpu_reset(cpu); =20 - cpu->intc =3D icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spa= pr), - &local_err); + spapr_cpu->icp =3D icp_create(OBJECT(cpu), spapr->icp_type, + XICS_FABRIC(spapr), &local_err); if (local_err) { goto error; } diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index 447ae761f7..f81dff28aa 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -47,4 +47,13 @@ typedef struct PnvCoreClass { #define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE #define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX =20 +typedef struct PnvCPUState { + ICPState *icp; +} PnvCPUState; + +static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu) +{ + return cpu->machine_data; +} + #endif /* _PPC_PNV_CORE_H */ diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_cor= e.h index 47dcfda12b..e3d2aa45a4 100644 --- a/include/hw/ppc/spapr_cpu_core.h +++ b/include/hw/ppc/spapr_cpu_core.h @@ -41,4 +41,14 @@ typedef struct sPAPRCPUCoreClass { const char *spapr_get_cpu_core_type(const char *cpu_type); void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_u= long r3); =20 +typedef struct ICPState ICPState; +typedef struct sPAPRCPUState { + ICPState *icp; +} sPAPRCPUState; + +static inline sPAPRCPUState *spapr_cpu_state(PowerPCCPU *cpu) +{ + return (sPAPRCPUState *)cpu->machine_data; +} + #endif diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 6cebff47a7..48930d91e5 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -207,7 +207,7 @@ typedef struct sPAPRMachineState sPAPRMachineState; int xics_kvm_init(sPAPRMachineState *spapr, Error **errp); void xics_spapr_init(sPAPRMachineState *spapr); =20 -Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, - Error **errp); +ICPState *icp_create(Object *cpu, const char *type, XICSFabric *xi, + Error **errp); =20 #endif /* XICS_H */ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index a91f1a8777..abf0bf0224 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1204,7 +1204,7 @@ struct PowerPCCPU { int vcpu_id; uint32_t compat_pvr; PPCVirtualHypervisor *vhyp; - Object *intc; + void *machine_data; int32_t node_id; /* NUMA node this CPU belongs to */ PPCHash64Options *hash64_opts; =20 --=20 2.17.1 From nobody Tue Apr 16 13:48:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528873467770543.6790289358912; Wed, 13 Jun 2018 00:04:27 -0700 (PDT) Received: from localhost ([::1]:60294 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSzpT-00085d-2p for importer@patchew.org; Wed, 13 Jun 2018 03:04:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34256) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSzic-0002yE-Q4 for qemu-devel@nongnu.org; Wed, 13 Jun 2018 02:57:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fSzia-0006ae-A3 for qemu-devel@nongnu.org; Wed, 13 Jun 2018 02:57:22 -0400 Received: from ozlabs.org ([203.11.71.1]:59631) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fSziZ-0006XL-Jt; Wed, 13 Jun 2018 02:57:20 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 415HcT69Klz9s52; Wed, 13 Jun 2018 16:57:13 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1528873033; bh=yC1fqGpsQuaGB/R4g6+khh7qEP6zICHz1Fm6/+XhcFA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GyUaVEhS2ZLHcWCl3k36ztJNUsHj9og3/4ArSWQ1moL+QjHPoT2v5883H3+R/fw9X yUCvzl3Y4SDDsqH3mTeTgAK01wxoKwbyS+imBlafF41AYbwndU4Vw3iLskvAvcBdIh 2wG+OIt9tXW5uE87+rMctpBdGRnRqDMJTpKu4/hI= From: David Gibson To: groug@kaod.org Date: Wed, 13 Jun 2018 16:57:07 +1000 Message-Id: <20180613065707.30766-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180613065707.30766-1-david@gibson.dropbear.id.au> References: <20180613065707.30766-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PATCH 7/7] target/ppc, spapr: Move VPA information to machine_data X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, clg@kaod.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" CPUPPCState currently contains a number of fields containing the state of the VPA. The VPA is a PAPR specific concept covering several guest/host shared memory areas used to communicate some information with the hypervisor. As a PAPR concept this is really machine specific information, although it is per-cpu, so it doesn't really belong in the core CPU state structure. So, move it to the PAPR specific 'machine_data' structure. Signed-off-by: David Gibson Reviewed-by: Greg Kurz --- hw/ppc/spapr_cpu_core.c | 7 +++ hw/ppc/spapr_hcall.c | 77 ++++++++++++++++++--------------- include/hw/ppc/spapr_cpu_core.h | 3 ++ target/ppc/cpu.h | 6 --- target/ppc/translate_init.inc.c | 8 ---- 5 files changed, 52 insertions(+), 49 deletions(-) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 544bda93e2..f642c95967 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -28,6 +28,7 @@ static void spapr_cpu_reset(void *opaque) CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + sPAPRCPUState *spapr_cpu =3D spapr_cpu_state(cpu); target_ulong lpcr; =20 cpu_reset(cs); @@ -69,6 +70,12 @@ static void spapr_cpu_reset(void *opaque) =20 /* Set a full AMOR so guest can use the AMR as it sees fit */ env->spr[SPR_AMOR] =3D 0xffffffffffffffffull; + + spapr_cpu->vpa_addr =3D 0; + spapr_cpu->slb_shadow_addr =3D 0; + spapr_cpu->slb_shadow_size =3D 0; + spapr_cpu->dtl_addr =3D 0; + spapr_cpu->dtl_size =3D 0; } =20 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_u= long r3) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 8b9a4b577f..ae913d070f 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -8,6 +8,7 @@ #include "exec/exec-all.h" #include "helper_regs.h" #include "hw/ppc/spapr.h" +#include "hw/ppc/spapr_cpu_core.h" #include "mmu-hash64.h" #include "cpu-models.h" #include "trace.h" @@ -908,9 +909,11 @@ unmap_out: #define VPA_SHARED_PROC_OFFSET 0x9 #define VPA_SHARED_PROC_VAL 0x2 =20 -static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) +static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D CPU(cpu); + CPUPPCState *env =3D &cpu->env; + sPAPRCPUState *spapr_cpu =3D spapr_cpu_state(cpu); uint16_t size; uint8_t tmp; =20 @@ -935,32 +938,34 @@ static target_ulong register_vpa(CPUPPCState *env, ta= rget_ulong vpa) return H_PARAMETER; } =20 - env->vpa_addr =3D vpa; + spapr_cpu->vpa_addr =3D vpa; =20 - tmp =3D ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); + tmp =3D ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET= ); tmp |=3D VPA_SHARED_PROC_VAL; - stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); + stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); =20 return H_SUCCESS; } =20 -static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) +static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) { - if (env->slb_shadow_addr) { + sPAPRCPUState *spapr_cpu =3D spapr_cpu_state(cpu); + + if (spapr_cpu->slb_shadow_addr) { return H_RESOURCE; } =20 - if (env->dtl_addr) { + if (spapr_cpu->dtl_addr) { return H_RESOURCE; } =20 - env->vpa_addr =3D 0; + spapr_cpu->vpa_addr =3D 0; return H_SUCCESS; } =20 -static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong add= r) +static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + sPAPRCPUState *spapr_cpu =3D spapr_cpu_state(cpu); uint32_t size; =20 if (addr =3D=3D 0) { @@ -968,7 +973,7 @@ static target_ulong register_slb_shadow(CPUPPCState *en= v, target_ulong addr) return H_HARDWARE; } =20 - size =3D ldl_be_phys(cs->as, addr + 0x4); + size =3D ldl_be_phys(CPU(cpu)->as, addr + 0x4); if (size < 0x8) { return H_PARAMETER; } @@ -977,26 +982,28 @@ static target_ulong register_slb_shadow(CPUPPCState *= env, target_ulong addr) return H_PARAMETER; } =20 - if (!env->vpa_addr) { + if (!spapr_cpu->vpa_addr) { return H_RESOURCE; } =20 - env->slb_shadow_addr =3D addr; - env->slb_shadow_size =3D size; + spapr_cpu->slb_shadow_addr =3D addr; + spapr_cpu->slb_shadow_size =3D size; =20 return H_SUCCESS; } =20 -static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong a= ddr) +static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong ad= dr) { - env->slb_shadow_addr =3D 0; - env->slb_shadow_size =3D 0; + sPAPRCPUState *spapr_cpu =3D spapr_cpu_state(cpu); + + spapr_cpu->slb_shadow_addr =3D 0; + spapr_cpu->slb_shadow_size =3D 0; return H_SUCCESS; } =20 -static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) +static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + sPAPRCPUState *spapr_cpu =3D spapr_cpu_state(cpu); uint32_t size; =20 if (addr =3D=3D 0) { @@ -1004,26 +1011,28 @@ static target_ulong register_dtl(CPUPPCState *env, = target_ulong addr) return H_HARDWARE; } =20 - size =3D ldl_be_phys(cs->as, addr + 0x4); + size =3D ldl_be_phys(CPU(cpu)->as, addr + 0x4); =20 if (size < 48) { return H_PARAMETER; } =20 - if (!env->vpa_addr) { + if (!spapr_cpu->vpa_addr) { return H_RESOURCE; } =20 - env->dtl_addr =3D addr; - env->dtl_size =3D size; + spapr_cpu->dtl_addr =3D addr; + spapr_cpu->dtl_size =3D size; =20 return H_SUCCESS; } =20 -static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) +static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) { - env->dtl_addr =3D 0; - env->dtl_size =3D 0; + sPAPRCPUState *spapr_cpu =3D spapr_cpu_state(cpu); + + spapr_cpu->dtl_addr =3D 0; + spapr_cpu->dtl_size =3D 0; =20 return H_SUCCESS; } @@ -1035,38 +1044,36 @@ static target_ulong h_register_vpa(PowerPCCPU *cpu,= sPAPRMachineState *spapr, target_ulong procno =3D args[1]; target_ulong vpa =3D args[2]; target_ulong ret =3D H_PARAMETER; - CPUPPCState *tenv; PowerPCCPU *tcpu; =20 tcpu =3D spapr_find_cpu(procno); if (!tcpu) { return H_PARAMETER; } - tenv =3D &tcpu->env; =20 switch (flags) { case FLAGS_REGISTER_VPA: - ret =3D register_vpa(tenv, vpa); + ret =3D register_vpa(tcpu, vpa); break; =20 case FLAGS_DEREGISTER_VPA: - ret =3D deregister_vpa(tenv, vpa); + ret =3D deregister_vpa(tcpu, vpa); break; =20 case FLAGS_REGISTER_SLBSHADOW: - ret =3D register_slb_shadow(tenv, vpa); + ret =3D register_slb_shadow(tcpu, vpa); break; =20 case FLAGS_DEREGISTER_SLBSHADOW: - ret =3D deregister_slb_shadow(tenv, vpa); + ret =3D deregister_slb_shadow(tcpu, vpa); break; =20 case FLAGS_REGISTER_DTL: - ret =3D register_dtl(tenv, vpa); + ret =3D register_dtl(tcpu, vpa); break; =20 case FLAGS_DEREGISTER_DTL: - ret =3D deregister_dtl(tenv, vpa); + ret =3D deregister_dtl(tcpu, vpa); break; } =20 diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_cor= e.h index e3d2aa45a4..40129cc452 100644 --- a/include/hw/ppc/spapr_cpu_core.h +++ b/include/hw/ppc/spapr_cpu_core.h @@ -44,6 +44,9 @@ void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ul= ong nip, target_ulong r typedef struct ICPState ICPState; typedef struct sPAPRCPUState { ICPState *icp; + uint64_t vpa_addr; + uint64_t slb_shadow_addr, slb_shadow_size; + uint64_t dtl_addr, dtl_size; } sPAPRCPUState; =20 static inline sPAPRCPUState *spapr_cpu_state(PowerPCCPU *cpu) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index abf0bf0224..6c2f4d29f2 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1091,12 +1091,6 @@ struct CPUPPCState { target_ulong rmls; #endif =20 -#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) - uint64_t vpa_addr; - uint64_t slb_shadow_addr, slb_shadow_size; - uint64_t dtl_addr, dtl_size; -#endif /* TARGET_PPC64 */ - int error_code; uint32_t pending_interrupts; #if !defined(CONFIG_USER_ONLY) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index bb9296f5a3..76d6f3fd5e 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10316,14 +10316,6 @@ static void ppc_cpu_reset(CPUState *s) s->exception_index =3D POWERPC_EXCP_NONE; env->error_code =3D 0; =20 -#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) - env->vpa_addr =3D 0; - env->slb_shadow_addr =3D 0; - env->slb_shadow_size =3D 0; - env->dtl_addr =3D 0; - env->dtl_size =3D 0; -#endif /* TARGET_PPC64 */ - for (i =3D 0; i < ARRAY_SIZE(env->spr_cb); i++) { ppc_spr_t *spr =3D &env->spr_cb[i]; =20 --=20 2.17.1