From nobody Mon Feb 9 13:24:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152827763349853.99703570746749; Wed, 6 Jun 2018 02:33:53 -0700 (PDT) Received: from localhost ([::1]:51030 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQUpE-0002ny-DN for importer@patchew.org; Wed, 06 Jun 2018 05:33:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33882) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQUnJ-0001jM-I3 for qemu-devel@nongnu.org; Wed, 06 Jun 2018 05:31:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fQUnI-0003k9-6S for qemu-devel@nongnu.org; Wed, 06 Jun 2018 05:31:53 -0400 Received: from greensocs.com ([193.104.36.180]:53737) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQUnD-0003h6-CU; Wed, 06 Jun 2018 05:31:47 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id DBC5244355F; Wed, 6 Jun 2018 11:31:40 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id p0Ovs-wvChz5; Wed, 6 Jun 2018 11:31:39 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id F22D144354B; Wed, 6 Jun 2018 11:31:38 +0200 (CEST) Received: from michell-laptop.bar.greensocs.com (antfield.tima.u-ga.fr [147.171.129.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 74EB344355E; Wed, 6 Jun 2018 11:31:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1528277500; bh=CMmVzt4a3RYYkoxTChm+EUJm/11QFvwCw2sxhsnogis=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=yUmO7zdN5nziO+ryCfJ5RRkQMs/bNzRljyrVV5ZdjYrsJp/obm4g4RJZiURmzrkLm Jj7JKZ5kxn8mAC/hnKXnhC75RTTWcCAs13oYmQuou1o16fejNZSjVtgsMng6dc7BBk V36jxhwA7Otz1kgbFVZr2WWHUNENp9xMkOPZzTUk= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=Cz+c3ZY4; dkim=pass (1024-bit key) header.d=greensocs.com header.b=Cz+c3ZY4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1528277498; bh=CMmVzt4a3RYYkoxTChm+EUJm/11QFvwCw2sxhsnogis=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Cz+c3ZY4hwSorA02wdw3JshB8XyBD+2TNKpmUthoxf9bs71S/frU5TLAXeXs5NRH6 BwTFDViglBUZO2xIrKNbrjMm1yVbxZadXQ0awop9yAqcF6fQrJ4EOvGrtwq7TSo9tj VtwlveRaL9jE3BKcbUrX3snViF4bDJK/yn3e9jmY= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1528277498; bh=CMmVzt4a3RYYkoxTChm+EUJm/11QFvwCw2sxhsnogis=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Cz+c3ZY4hwSorA02wdw3JshB8XyBD+2TNKpmUthoxf9bs71S/frU5TLAXeXs5NRH6 BwTFDViglBUZO2xIrKNbrjMm1yVbxZadXQ0awop9yAqcF6fQrJ4EOvGrtwq7TSo9tj VtwlveRaL9jE3BKcbUrX3snViF4bDJK/yn3e9jmY= From: luc.michel@greensocs.com To: qemu-devel@nongnu.org Date: Wed, 6 Jun 2018 11:31:00 +0200 Message-Id: <20180606093101.30518-6-luc.michel@greensocs.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180606093101.30518-1-luc.michel@greensocs.com> References: <20180606093101.30518-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH 5/6] intc/arm_gic: Improve traces X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc MICHEL Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Luc MICHEL Add some traces to the ARM GIC to catch register accesses (distributor, (v)cpu interface and virtual interface), and to take into account virtualization extensions (print `vcpu` instead of `cpu` when needed). Also add some virtualization extensions specific traces: LR updating and maintenance IRQ generation. Signed-off-by: Luc MICHEL Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/arm_gic.c | 31 +++++++++++++++++++++++++------ hw/intc/trace-events | 12 ++++++++++-- 2 files changed, 35 insertions(+), 8 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 6105f930c4..a0ffd85fdf 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -179,8 +179,10 @@ static inline void gic_update_internal(GICState *s, bo= ol virt) } =20 if (best_irq !=3D 1023) { - trace_gic_update_bestirq(cpu, best_irq, best_prio, - s->priority_mask[cpu_iface], s->running_priority[cpu_iface= ]); + trace_gic_update_bestirq(virt ? "vcpu" : "cpu", cpu, + best_irq, best_prio, + s->priority_mask[cpu_iface], + s->running_priority[cpu_iface]); } =20 irq_level =3D fiq_level =3D 0; @@ -268,6 +270,7 @@ static void gic_update_maintenance(GICState *s) gic_compute_misr(s, cpu); maint_level =3D (s->h_hcr[cpu] & GICH_HCR_EN) && s->h_misr[cpu]; =20 + trace_gic_update_maintenance_irq(cpu, maint_level); qemu_set_irq(s->maintenance_irq[cpu], maint_level); } } @@ -524,7 +527,8 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemT= xAttrs attrs) * is in the wrong group. */ irq =3D gic_get_current_pending_irq(s, cpu, attrs); - trace_gic_acknowledge_irq(gic_get_vcpu_real_id(cpu), irq); + trace_gic_acknowledge_irq(gic_is_vcpu(cpu) ? "vcpu" : "cpu", + gic_get_vcpu_real_id(cpu), irq); =20 if (irq >=3D GIC_MAXIRQ) { DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); @@ -1002,20 +1006,23 @@ static MemTxResult gic_dist_read(void *opaque, hwad= dr offset, uint64_t *data, switch (size) { case 1: *data =3D gic_dist_readb(opaque, offset, attrs); - return MEMTX_OK; + break; case 2: *data =3D gic_dist_readb(opaque, offset, attrs); *data |=3D gic_dist_readb(opaque, offset + 1, attrs) << 8; - return MEMTX_OK; + break; case 4: *data =3D gic_dist_readb(opaque, offset, attrs); *data |=3D gic_dist_readb(opaque, offset + 1, attrs) << 8; *data |=3D gic_dist_readb(opaque, offset + 2, attrs) << 16; *data |=3D gic_dist_readb(opaque, offset + 3, attrs) << 24; - return MEMTX_OK; + break; default: return MEMTX_ERROR; } + + trace_gic_dist_read(offset, size, *data); + return MEMTX_OK; } =20 static void gic_dist_writeb(void *opaque, hwaddr offset, @@ -1309,6 +1316,8 @@ static void gic_dist_writel(void *opaque, hwaddr offs= et, static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t da= ta, unsigned size, MemTxAttrs attrs) { + trace_gic_dist_write(offset, size, data); + switch (size) { case 1: gic_dist_writeb(opaque, offset, data, attrs); @@ -1463,12 +1472,18 @@ static MemTxResult gic_cpu_read(GICState *s, int cp= u, int offset, *data =3D 0; break; } + + trace_gic_cpu_read(gic_is_vcpu(cpu) ? "vcpu" : "cpu", + gic_get_vcpu_real_id(cpu), offset, *data); return MEMTX_OK; } =20 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value, MemTxAttrs attrs) { + trace_gic_cpu_write(gic_is_vcpu(cpu) ? "vcpu" : "cpu", + gic_get_vcpu_real_id(cpu), offset, value); + switch (offset) { case 0x00: /* Control */ gic_set_cpu_control(s, cpu, value, attrs); @@ -1679,6 +1694,7 @@ static void gic_set_lr_entry(GICState *s, int cpu, in= t lr_num, uint32_t entry) } =20 s->h_lr[lr_num][cpu] =3D entry; + trace_gic_lr_entry(cpu, lr_num, entry); is_free =3D gic_lr_update(s, lr_num, cpu); =20 if (!is_free) { @@ -1749,6 +1765,7 @@ static MemTxResult gic_hyp_read(void *opaque, hwaddr = addr, uint64_t *data, return MEMTX_OK; } =20 + trace_gic_hyp_read(addr, *data); return MEMTX_OK; } =20 @@ -1759,6 +1776,8 @@ static MemTxResult gic_hyp_write(void *opaque, hwaddr= addr, uint64_t value, int cpu =3D gic_get_current_cpu(s); int vcpu =3D gic_get_current_vcpu(s); =20 + trace_gic_hyp_write(addr, value); + switch (addr) { case 0x0: /* Hypervisor Control */ s->h_hcr[cpu] =3D value & 0xf80000ff; diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 55e8c2570c..16d02fa8cf 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -92,9 +92,17 @@ aspeed_vic_write(uint64_t offset, unsigned size, uint32_= t data) "To 0x%" PRIx64 gic_enable_irq(int irq) "irq %d enabled" gic_disable_irq(int irq) "irq %d disabled" gic_set_irq(int irq, int level, int cpumask, int target) "irq %d level %d = cpumask 0x%x target 0x%x" -gic_update_bestirq(int cpu, int irq, int prio, int priority_mask, int runn= ing_priority) "cpu %d irq %d priority %d cpu priority mask %d cpu running p= riority %d" +gic_update_bestirq(const char *s, int cpu, int irq, int prio, int priority= _mask, int running_priority) "%s %d irq %d priority %d cpu priority mask %d= cpu running priority %d" gic_update_set_irq(int cpu, const char *name, int level) "cpu[%d]: %s =3D = %d" -gic_acknowledge_irq(int cpu, int irq) "cpu %d acknowledged irq %d" +gic_acknowledge_irq(const char *s, int cpu, int irq) "%s %d acknowledged i= rq %d" +gic_cpu_write(const char *s, int cpu, int addr, uint32_t val) "%s %d iface= write at 0x%08x 0x%08" PRIx32 +gic_cpu_read(const char *s, int cpu, int addr, uint32_t val) "%s %d iface = write at 0x%08x: 0x%08" PRIx32 +gic_hyp_read(int addr, uint32_t val) "hyp read at 0x%08x: 0x%08" PRIx32 +gic_hyp_write(int addr, uint32_t val) "hyp write at 0x%08x: 0x%08" PRIx32 +gic_dist_read(int addr, unsigned int size, uint32_t val) "dist read at 0x%= 08x size %u: 0x%08" PRIx32 +gic_dist_write(int addr, unsigned int size, uint32_t val) "dist write at 0= x%08x size %u: 0x%08" PRIx32 +gic_lr_entry(int cpu, int entry, uint32_t val) "cpu %d: new lr entry %d: 0= x%08" PRIx32 +gic_update_maintenance_irq(int cpu, int val) "cpu %d: maintenance =3D %d" =20 # hw/intc/arm_gicv3_cpuif.c gicv3_icc_pmr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_PMR read cpu 0x%= x value 0x%" PRIx64 --=20 2.17.0