From nobody Sun Nov 2 12:01:45 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1527973002787690.7419165170363; Sat, 2 Jun 2018 13:56:42 -0700 (PDT) Received: from localhost ([::1]:32778 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fPDZf-0003fi-Uw for importer@patchew.org; Sat, 02 Jun 2018 16:56:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39798) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fPDYd-0003Jm-Ng for qemu-devel@nongnu.org; Sat, 02 Jun 2018 16:55:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fPDYa-00085S-It for qemu-devel@nongnu.org; Sat, 02 Jun 2018 16:55:27 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:39314) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fPDYa-00085K-D6; Sat, 02 Jun 2018 16:55:24 -0400 Received: by mail-qk0-x243.google.com with SMTP id g14-v6so10204908qkm.6; Sat, 02 Jun 2018 13:55:24 -0700 (PDT) Received: from x1.local ([138.117.48.222]) by smtp.gmail.com with ESMTPSA id b12-v6sm34679400qtb.57.2018.06.02.13.55.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 02 Jun 2018 13:55:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=tbsZRzCEBpr8bRJLDMRDqDaMOoyT4vgHKL9jHD/ablE=; b=obzbiX4c+yI1Z25Ebh5F00ujs8sMdDzQczFdkwEWD2dxBB8eljZn9DKGGKKptqE5Ys xcsFs4otvD/IfcnXGs+Fp4NcgyTom5a11FMnHhnwHowghocikhSwK/4iZ1K91pYmuWIr TFRiauCNd6mS98/moVPf3IDwAzs6WYHNCLUvTw50aHiaGkM1uMyapWU4bjtK7EwfJ4g2 VJfIzkz7FkbocAUCOohUjUYDeNSghog13RG5nEc5IKyHvkKvfreI1rchH/MmK3pUH2zE H2dWDVglyeZ3V0FLbFXQgfGqe52GJ6uwerPl3Z0ch/e1v4ngwR1bW2DB2dXsbn6qf4Tu X9og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=tbsZRzCEBpr8bRJLDMRDqDaMOoyT4vgHKL9jHD/ablE=; b=HzKZhvRJ1mLyEqoxn23c2r136Prur+4Z9Pp8pAYn8L+A6MCSrKWg/XnBABWofF0/+L D+T80qWnYIOJ526L/9cnqLycxv7Eq1G6EUKuMa+/aujucNMei2akqdt11ecHWArk57GQ 1a5m/TaEyTzjrwV5fFYWRLqBhxAogQRoukgnSLAwPGLP1d4nRmuOPxQdnRDoLfSnsagx UJctz3y1hCWSKUP1Nl7EOQCPbTUzrel+gpB1unHWIW8yLYkH+i65WrlpebkxYgwUzxYk pCJwkPYf9tKhTv9zu+7xyCqyL0w2ONVKjSH/uu4DXCmMtF9bxL+w0XxY75sntCm961WO TWdA== X-Gm-Message-State: APt69E3Y03mepNkRwOc6KayBKodaVu0y0FXF31dMww65Ewi8kn1mliL4 /3naN/p0G5T1t8FNQDBqtuM= X-Google-Smtp-Source: ADUXVKJMJrCjbKgpvdKLQGaJV9RdHNe0amyOQIlKJTmmo7vXw8IheRp2k8RRfRPdRKpE60rhyKfUgA== X-Received: by 2002:a37:4946:: with SMTP id w67-v6mr1781113qka.394.1527972923447; Sat, 02 Jun 2018 13:55:23 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Alistair Francis , Eric Blake , Peter Maydell , "Edgar E. Iglesias" Date: Sat, 2 Jun 2018 17:55:11 -0300 Message-Id: <20180602205511.6077-1-f4bug@amsat.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [RFC PATCH] hw/registerfields: Deposit fields "in place" X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 These macros are always used to deposit a field in place. Update them to take the pointer argument. As these macros are constructed using compound statements, it is easy to not use the return value, and the compiler doesn't warn. Thus this change makes these macros safer. This also helps having a simpler/shorter code to review. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/smmuv3-internal.h | 2 +- include/hw/registerfields.h | 14 +++++----- hw/arm/smmuv3.c | 28 +++++++++---------- hw/dma/xlnx-zdma.c | 6 ++-- hw/sd/sd.c | 4 +-- hw/sd/sdhci.c | 56 ++++++++++++++++++------------------- 6 files changed, 53 insertions(+), 57 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index a9d714b56e..2f020e2e90 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -203,7 +203,7 @@ static inline bool smmuv3_eventq_enabled(SMMUv3State *s) =20 static inline void smmu_write_cmdq_err(SMMUv3State *s, uint32_t err_type) { - s->cmdq.cons =3D FIELD_DP32(s->cmdq.cons, CMDQ_CONS, ERR, err_type); + FIELD_DP32(&s->cmdq.cons, CMDQ_CONS, ERR, err_type); } =20 /* Commands */ diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index 2659a58737..14a12f6a48 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -45,7 +45,7 @@ #define ARRAY_FIELD_EX32(regs, reg, field) \ FIELD_EX32((regs)[R_ ## reg], reg, field) =20 -/* Deposit a register field. +/* Deposit a register field (in place). * Assigning values larger then the target field will result in * compilation warnings. */ @@ -54,20 +54,20 @@ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ } v =3D { .v =3D val }; = \ uint32_t d; \ - d =3D deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, = \ - R_ ## reg ## _ ## field ## _LENGTH, v.v); \ - d; }) + d =3D deposit32(*(storage), R_ ## reg ## _ ## field ## _SHIFT, = \ + R_ ## reg ## _ ## field ## _LENGTH, v.v); = \ + *(storage) =3D d; }) #define FIELD_DP64(storage, reg, field, val) ({ \ struct { \ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ } v =3D { .v =3D val }; = \ uint64_t d; \ - d =3D deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, = \ + d =3D deposit64(*(storage), R_ ## reg ## _ ## field ## _SHIFT, = \ R_ ## reg ## _ ## field ## _LENGTH, v.v); \ - d; }) + *(storage) =3D d; }) =20 /* Deposit a field to array of registers. */ #define ARRAY_FIELD_DP32(regs, reg, field, val) \ - (regs)[R_ ## reg] =3D FIELD_DP32((regs)[R_ ## reg], reg, field, val); + FIELD_DP32(&(regs)[R_ ## reg], reg, field, val); =20 #endif diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 42dc521c13..6406b69d68 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -238,25 +238,25 @@ static void smmuv3_init_regs(SMMUv3State *s) * IDR0: stage1 only, AArch64 only, coherent access, 16b ASID, * multi-level stream table */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, S1P, 1); /* stage 1 supporte= d */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only= */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, COHACC, 1); /* IO coherent */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, TTENDIAN, 2); /* little endi= an */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, 1); /* No stall= */ + FIELD_DP32(&s->idr[0], IDR0, S1P, 1); /* stage 1 supported */ + FIELD_DP32(&s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only */ + FIELD_DP32(&s->idr[0], IDR0, COHACC, 1); /* IO coherent */ + FIELD_DP32(&s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */ + FIELD_DP32(&s->idr[0], IDR0, TTENDIAN, 2); /* little endian */ + FIELD_DP32(&s->idr[0], IDR0, STALL_MODEL, 1); /* No stall */ /* terminated transaction will always be aborted/error returned */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, TERM_MODEL, 1); + FIELD_DP32(&s->idr[0], IDR0, TERM_MODEL, 1); /* 2-level stream table supported */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, STLEVEL, 1); + FIELD_DP32(&s->idr[0], IDR0, STLEVEL, 1); =20 - s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SIDSIZE, SMMU_IDR1_SIDSIZE); - s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS); - s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS); + FIELD_DP32(&s->idr[1], IDR1, SIDSIZE, SMMU_IDR1_SIDSIZE); + FIELD_DP32(&s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS); + FIELD_DP32(&s->idr[1], IDR1, CMDQS, SMMU_CMDQS); =20 /* 4K and 64K granule support */ - s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1); - s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); - s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 b= its */ + FIELD_DP32(&s->idr[5], IDR5, GRAN4K, 1); + FIELD_DP32(&s->idr[5], IDR5, GRAN64K, 1); + FIELD_DP32(&s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */ =20 s->cmdq.base =3D deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS); s->cmdq.prod =3D 0; diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c index 8eea757aff..82fa3ea672 100644 --- a/hw/dma/xlnx-zdma.c +++ b/hw/dma/xlnx-zdma.c @@ -426,10 +426,8 @@ static void zdma_write_dst(XlnxZDMA *s, uint8_t *buf, = uint32_t len) } =20 /* Write back to buffered descriptor. */ - s->dsc_dst.words[2] =3D FIELD_DP32(s->dsc_dst.words[2], - ZDMA_CH_DST_DSCR_WORD2, - SIZE, - dst_size); + FIELD_DP32(&s->dsc_dst.words[2], + ZDMA_CH_DST_DSCR_WORD2, SIZE, dst_size); } } =20 diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 7af19fa06c..0f41028e91 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -301,10 +301,10 @@ static void sd_ocr_powerup(void *opaque) assert(!FIELD_EX32(sd->ocr, OCR, CARD_POWER_UP)); =20 /* card power-up OK */ - sd->ocr =3D FIELD_DP32(sd->ocr, OCR, CARD_POWER_UP, 1); + FIELD_DP32(&sd->ocr, OCR, CARD_POWER_UP, 1); =20 if (sd->size > 1 * G_BYTE) { - sd->ocr =3D FIELD_DP32(sd->ocr, OCR, CARD_CAPACITY, 1); + FIELD_DP32(&sd->ocr, OCR, CARD_CAPACITY, 1); } } =20 diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 63c44a4ee8..d42492f60a 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -94,21 +94,21 @@ static void sdhci_check_capareg(SDHCIState *s, Error **= errp) case 4: val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); trace_sdhci_capareg("64-bit system bus (v4)", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); + FIELD_DP64(&msk, SDHC_CAPAB, BUS64BIT_V4, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); trace_sdhci_capareg("UHS-II", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); + FIELD_DP64(&msk, SDHC_CAPAB, UHS_II, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); trace_sdhci_capareg("ADMA3", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); + FIELD_DP64(&msk, SDHC_CAPAB, ADMA3, 0); =20 /* fallthrough */ case 3: val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); trace_sdhci_capareg("async interrupt", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); + FIELD_DP64(&msk, SDHC_CAPAB, ASYNC_INT, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); if (val) { @@ -116,70 +116,70 @@ static void sdhci_check_capareg(SDHCIState *s, Error = **errp) return; } trace_sdhci_capareg("slot type", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); + FIELD_DP64(&msk, SDHC_CAPAB, SLOT_TYPE, 0); =20 if (val !=3D 2) { val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); trace_sdhci_capareg("8-bit bus", val); } - msk =3D FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); + FIELD_DP64(&msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); trace_sdhci_capareg("bus speed mask", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); + FIELD_DP64(&msk, SDHC_CAPAB, BUS_SPEED, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); trace_sdhci_capareg("driver strength mask", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); + FIELD_DP64(&msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); trace_sdhci_capareg("timer re-tuning", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); + FIELD_DP64(&msk, SDHC_CAPAB, TIMER_RETUNING, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); trace_sdhci_capareg("use SDR50 tuning", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); + FIELD_DP64(&msk, SDHC_CAPAB, SDR50_TUNING, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); trace_sdhci_capareg("re-tuning mode", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); + FIELD_DP64(&msk, SDHC_CAPAB, RETUNING_MODE, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); trace_sdhci_capareg("clock multiplier", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); + FIELD_DP64(&msk, SDHC_CAPAB, CLOCK_MULT, 0); =20 /* fallthrough */ case 2: /* default version */ val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); trace_sdhci_capareg("ADMA2", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); + FIELD_DP64(&msk, SDHC_CAPAB, ADMA2, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); trace_sdhci_capareg("ADMA1", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); + FIELD_DP64(&msk, SDHC_CAPAB, ADMA1, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); trace_sdhci_capareg("64-bit system bus (v3)", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); + FIELD_DP64(&msk, SDHC_CAPAB, BUS64BIT, 0); =20 /* fallthrough */ case 1: y =3D FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); + FIELD_DP64(&msk, SDHC_CAPAB, TOUNIT, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val); if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { return; } - msk =3D FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); + FIELD_DP64(&msk, SDHC_CAPAB, TOCLKFREQ, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val); if (sdhci_check_capab_freq_range(s, "base", val, errp)) { return; } - msk =3D FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); + FIELD_DP64(&msk, SDHC_CAPAB, BASECLKFREQ, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); if (val >=3D 3) { @@ -187,31 +187,31 @@ static void sdhci_check_capareg(SDHCIState *s, Error = **errp) return; } trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); + FIELD_DP64(&msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); trace_sdhci_capareg("high speed", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); + FIELD_DP64(&msk, SDHC_CAPAB, HIGHSPEED, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); trace_sdhci_capareg("SDMA", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); + FIELD_DP64(&msk, SDHC_CAPAB, SDMA, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); trace_sdhci_capareg("suspend/resume", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); + FIELD_DP64(&msk, SDHC_CAPAB, SUSPRESUME, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, V33); trace_sdhci_capareg("3.3v", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, V33, 0); + FIELD_DP64(&msk, SDHC_CAPAB, V33, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, V30); trace_sdhci_capareg("3.0v", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, V30, 0); + FIELD_DP64(&msk, SDHC_CAPAB, V30, 0); =20 val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, V18); trace_sdhci_capareg("1.8v", val); - msk =3D FIELD_DP64(msk, SDHC_CAPAB, V18, 0); + FIELD_DP64(&msk, SDHC_CAPAB, V18, 0); break; =20 default: @@ -1017,10 +1017,8 @@ static uint64_t sdhci_read(void *opaque, hwaddr offs= et, unsigned size) break; case SDHC_PRNSTS: ret =3D s->prnsts; - ret =3D FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL, - sdbus_get_dat_lines(&s->sdbus)); - ret =3D FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL, - sdbus_get_cmd_line(&s->sdbus)); + FIELD_DP32(&ret, SDHC_PRNSTS, DAT_LVL, sdbus_get_dat_lines(&s->sdb= us)); + FIELD_DP32(&ret, SDHC_PRNSTS, CMD_LVL, sdbus_get_cmd_line(&s->sdbu= s)); break; case SDHC_HOSTCTL: ret =3D s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | --=20 2.17.1