From nobody Wed Feb 11 04:01:00 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1527949028606605.7581015115073; Sat, 2 Jun 2018 07:17:08 -0700 (PDT) Received: from localhost ([::1]:59996 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fP7L9-0002Xs-HS for importer@patchew.org; Sat, 02 Jun 2018 10:17:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42866) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fP7J6-0001H5-65 for qemu-devel@nongnu.org; Sat, 02 Jun 2018 10:15:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fP7J5-0007Du-Ap for qemu-devel@nongnu.org; Sat, 02 Jun 2018 10:15:00 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:59816 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fP7J2-00074j-3K; Sat, 02 Jun 2018 10:14:56 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 9548B818BAFB; Sat, 2 Jun 2018 14:14:55 +0000 (UTC) Received: from localhost (ovpn-116-55.ams2.redhat.com [10.36.116.55]) by smtp.corp.redhat.com (Postfix) with ESMTP id 857F61C707; Sat, 2 Jun 2018 14:14:52 +0000 (UTC) From: Stefan Hajnoczi To: Date: Sat, 2 Jun 2018 15:14:45 +0100 Message-Id: <20180602141446.29982-2-stefanha@redhat.com> In-Reply-To: <20180602141446.29982-1-stefanha@redhat.com> References: <20180602141446.29982-1-stefanha@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Sat, 02 Jun 2018 14:14:55 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Sat, 02 Jun 2018 14:14:55 +0000 (UTC) for IP:'10.11.54.5' DOMAIN:'int-mx05.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'stefanha@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [RFC 1/2] target/arm: add "cortex-m0" CPU model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , jim@groklearning.com, mail@steffen-goertz.de, qemu-arm@nongnu.org, joel@jms.id.au, Stefan Hajnoczi , jusual@mail.ru Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Define a "cortex-m0" ARMv6-M CPU model. Most of the register reset values set by other CPU models are not relevant for the cut-down ARMv6-M architecture. Signed-off-by: Stefan Hajnoczi --- target/arm/cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5d60893a07..aac224d809 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1215,6 +1215,16 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_auxcr =3D 1; } =20 +static void cortex_m0_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_M); + + /* TODO ARMv6-M doesn't support coprocessors, so how is this value acc= essed? */ + cpu->midr =3D 0x410cc200; +} + static void cortex_m3_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -1796,6 +1806,8 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "arm1136", .initfn =3D arm1136_initfn }, { .name =3D "arm1176", .initfn =3D arm1176_initfn }, { .name =3D "arm11mpcore", .initfn =3D arm11mpcore_initfn }, + { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, + .class_init =3D arm_v7m_class_init /* TODO re= name? */ }, { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, --=20 2.17.0