From nobody Tue Feb 10 04:16:58 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1527788490708308.5876604848539; Thu, 31 May 2018 10:41:30 -0700 (PDT) Received: from localhost ([::1]:45413 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fORZp-0000c4-Tc for importer@patchew.org; Thu, 31 May 2018 13:41:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58754) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fOR8k-0003sL-A0 for qemu-devel@nongnu.org; Thu, 31 May 2018 13:13:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fOR8j-0000Oy-0q for qemu-devel@nongnu.org; Thu, 31 May 2018 13:13:30 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:45860 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fOR8i-0000OS-RA for qemu-devel@nongnu.org; Thu, 31 May 2018 13:13:28 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7FDB476F91; Thu, 31 May 2018 17:13:28 +0000 (UTC) Received: from donizetti.redhat.com (ovpn-117-47.ams2.redhat.com [10.36.117.47]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9662F2026DEF; Thu, 31 May 2018 17:13:27 +0000 (UTC) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Thu, 31 May 2018 19:12:35 +0200 Message-Id: <20180531171253.21012-36-pbonzini@redhat.com> In-Reply-To: <20180531171253.21012-1-pbonzini@redhat.com> References: <20180531171253.21012-1-pbonzini@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.4 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Thu, 31 May 2018 17:13:28 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Thu, 31 May 2018 17:13:28 +0000 (UTC) for IP:'10.11.54.4' DOMAIN:'int-mx04.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'pbonzini@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [PULL 35/53] WHPX: fix some compiler warnings X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucian Petrut , Alessandro Pilotti , Justin Terry Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Lucian Petrut This patch fixes a few compiler warnings, especially in case of x86 targets, where the number of registers was not properly handled and could cause an overflow. Signed-off-by: Alessandro Pilotti Signed-off-by: Justin Terry (VM) Signed-off-by: Lucian Petrut Message-Id: <1526405722-10887-3-git-send-email-lpetrut@cloudbasesolutions.c= om> Signed-off-by: Paolo Bonzini --- target/i386/whpx-all.c | 49 ++++++++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 14 deletions(-) diff --git a/target/i386/whpx-all.c b/target/i386/whpx-all.c index 32695d47f9..6b42096698 100644 --- a/target/i386/whpx-all.c +++ b/target/i386/whpx-all.c @@ -223,24 +223,31 @@ static void whpx_set_registers(CPUState *cpu) struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); struct CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); X86CPU *x86_cpu =3D X86_CPU(cpu); - struct whpx_register_set vcxt =3D {0}; + struct whpx_register_set vcxt; HRESULT hr; - int idx =3D 0; + int idx; + int idx_next; int i; int v86, r86; =20 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); =20 + memset(&vcxt, 0, sizeof(struct whpx_register_set)); + v86 =3D (env->eflags & VM_MASK); r86 =3D !(env->cr[0] & CR0_PE_MASK); =20 vcpu->tpr =3D cpu_get_apic_tpr(x86_cpu->apic_state); vcpu->apic_base =3D cpu_get_apic_base(x86_cpu->apic_state); =20 + idx =3D 0; + /* Indexes for first 16 registers match between HV and QEMU definition= s */ - for (idx =3D 0; idx < CPU_NB_REGS64; idx +=3D 1) { - vcxt.values[idx].Reg64 =3D env->regs[idx]; + idx_next =3D 16; + for (idx =3D 0; idx < CPU_NB_REGS; idx +=3D 1) { + vcxt.values[idx].Reg64 =3D (uint64_t)env->regs[idx]; } + idx =3D idx_next; =20 /* Same goes for RIP and RFLAGS */ assert(whpx_register_names[idx] =3D=3D WHvX64RegisterRip); @@ -287,10 +294,12 @@ static void whpx_set_registers(CPUState *cpu) =20 /* 16 XMM registers */ assert(whpx_register_names[idx] =3D=3D WHvX64RegisterXmm0); - for (i =3D 0; i < 16; i +=3D 1, idx +=3D 1) { + idx_next =3D idx + 16; + for (i =3D 0; i < sizeof(env->xmm_regs) / sizeof(ZMMReg); i +=3D 1, id= x +=3D 1) { vcxt.values[idx].Reg128.Low64 =3D env->xmm_regs[i].ZMM_Q(0); vcxt.values[idx].Reg128.High64 =3D env->xmm_regs[i].ZMM_Q(1); } + idx =3D idx_next; =20 /* 8 FP registers */ assert(whpx_register_names[idx] =3D=3D WHvX64RegisterFpMmx0); @@ -381,7 +390,8 @@ static void whpx_get_registers(CPUState *cpu) struct whpx_register_set vcxt; uint64_t tpr, apic_base; HRESULT hr; - int idx =3D 0; + int idx; + int idx_next; int i; =20 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); @@ -396,10 +406,14 @@ static void whpx_get_registers(CPUState *cpu) hr); } =20 + idx =3D 0; + /* Indexes for first 16 registers match between HV and QEMU definition= s */ - for (idx =3D 0; idx < CPU_NB_REGS64; idx +=3D 1) { + idx_next =3D 16; + for (idx =3D 0; idx < CPU_NB_REGS; idx +=3D 1) { env->regs[idx] =3D vcxt.values[idx].Reg64; } + idx =3D idx_next; =20 /* Same goes for RIP and RFLAGS */ assert(whpx_register_names[idx] =3D=3D WHvX64RegisterRip); @@ -446,10 +460,12 @@ static void whpx_get_registers(CPUState *cpu) =20 /* 16 XMM registers */ assert(whpx_register_names[idx] =3D=3D WHvX64RegisterXmm0); - for (i =3D 0; i < 16; i +=3D 1, idx +=3D 1) { + idx_next =3D idx + 16; + for (i =3D 0; i < sizeof(env->xmm_regs) / sizeof(ZMMReg); i +=3D 1, id= x +=3D 1) { env->xmm_regs[i].ZMM_Q(0) =3D vcxt.values[idx].Reg128.Low64; env->xmm_regs[i].ZMM_Q(1) =3D vcxt.values[idx].Reg128.High64; } + idx =3D idx_next; =20 /* 8 FP registers */ assert(whpx_register_names[idx] =3D=3D WHvX64RegisterFpMmx0); @@ -698,11 +714,14 @@ static void whpx_vcpu_pre_run(CPUState *cpu) X86CPU *x86_cpu =3D X86_CPU(cpu); int irq; uint8_t tpr; - WHV_X64_PENDING_INTERRUPTION_REGISTER new_int =3D {0}; + WHV_X64_PENDING_INTERRUPTION_REGISTER new_int; UINT32 reg_count =3D 0; - WHV_REGISTER_VALUE reg_values[3] =3D {0}; + WHV_REGISTER_VALUE reg_values[3]; WHV_REGISTER_NAME reg_names[3]; =20 + memset(&new_int, 0, sizeof(new_int)); + memset(reg_values, 0, sizeof(reg_values)); + qemu_mutex_lock_iothread(); =20 /* Inject NMI */ @@ -925,11 +944,13 @@ static int whpx_vcpu_run(CPUState *cpu) break; =20 case WHvRunVpExitReasonX64Cpuid: { - WHV_REGISTER_VALUE reg_values[5] =3D {0}; + WHV_REGISTER_VALUE reg_values[5]; WHV_REGISTER_NAME reg_names[5]; UINT32 reg_count =3D 5; UINT64 rip, rax, rcx, rdx, rbx; =20 + memset(reg_values, 0, sizeof(reg_values)); + rip =3D vcpu->exit_ctx.VpContext.Rip + vcpu->exit_ctx.VpContext.InstructionLength; switch (vcpu->exit_ctx.CpuidAccess.Rax) { @@ -1200,7 +1221,7 @@ static void whpx_update_mapping(hwaddr start_pa, ram_= addr_t size, error_report("WHPX: Failed to %s GPA range '%s' PA:%p, Size:%p byt= es," " Host:%p, hr=3D%08lx", (add ? "MAP" : "UNMAP"), name, - (void *)start_pa, (void *)size, host_va, hr); + (void *)(uintptr_t)start_pa, (void *)size, host_va, h= r); } } =20 @@ -1231,8 +1252,8 @@ static void whpx_process_section(MemoryRegionSection = *section, int add) host_va =3D (uintptr_t)memory_region_get_ram_ptr(mr) + section->offset_within_region + delta; =20 - whpx_update_mapping(start_pa, size, (void *)host_va, add, - memory_region_is_rom(mr), mr->name); + whpx_update_mapping(start_pa, size, (void *)(uintptr_t)host_va, add, + memory_region_is_rom(mr), mr->name); } =20 static void whpx_region_add(MemoryListener *listener, --=20 2.17.0